CN102820411B - Light-emitting diode chip for backlight unit, preparation method and method for packing - Google Patents
Light-emitting diode chip for backlight unit, preparation method and method for packing Download PDFInfo
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- CN102820411B CN102820411B CN201210312384.1A CN201210312384A CN102820411B CN 102820411 B CN102820411 B CN 102820411B CN 201210312384 A CN201210312384 A CN 201210312384A CN 102820411 B CN102820411 B CN 102820411B
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- 238000000034 method Methods 0.000 title claims abstract description 90
- 238000012856 packing Methods 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title description 15
- 239000010410 layer Substances 0.000 claims abstract description 172
- 239000011241 protective layer Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 16
- 239000003292 glue Substances 0.000 claims description 14
- 238000007639 printing Methods 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 26
- 238000001465 metallisation Methods 0.000 abstract description 14
- 238000004806 packaging method and process Methods 0.000 abstract description 11
- 230000002950 deficient Effects 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- 229910052737 gold Inorganic materials 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000004064 recycling Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000000007 visual effect Effects 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
The method for packing of a kind of light-emitting diode chip for backlight unit, step comprises: form a protective layer on an encapsulating carrier plate；Pattern this protective layer, to form a perforation running through this protective layer；Etch this encapsulating carrier plate, form the opening groove more than this perforation, make this protective layer of part of this perforation adjacent convexedly stretch in this groove；Form a metal level on this protective layer and this groove, wherein this groove and this protective layer adjacent non-coated metal layer；Remove this protective layer and be positioned at the metal level on this protective layer, forming one and be positioned at the reflector in this groove；And in the reflector that a fixed light-emitting diode chip for backlight unit is in this groove.Chip is located in the metallic reflection cup of groove-like by the present invention, and from chip two electrode unit with metallization process packaging body surface formed bare electrode, without using routing processing procedure, except reducing the fraction defective caused because of broken string, promote encapsulation reliability, also can improve the heat dispersion of chip, and make the assembly program of downstream application end easier.
Description
The application is filing date February 19, Application No. 200910037346.8, innovation and creation in 2009
The divisional application of the application of entitled " light-emitting diode chip for backlight unit, preparation method and method for packing ".
Technical field
The invention relates to a kind of light-emitting diode chip for backlight unit, its preparation method and method for packing, particularly relate to one
Kind of encapsulation volume is little and the fireballing light-emitting diode chip for backlight unit of processing procedure, its preparation method and method for packing.
Background technology
As it is shown in figure 1, known light-emitting diode chip for backlight unit 91 is generally by outside on routing mode and support plate 92
Portion's electrode 93 electrically connects.Owing to routing processing procedure needs to take the space that support plate 92 is bigger, and bonding process
Being to connect one by one with machine, process efficiency is extremely low, is unfavorable for that system encapsulates (system in package)
Or wafer-level packaging (wafer level package).
In order to improve the shortcoming of routing processing procedure, the most common mode is to utilize the side of flip (flip-chip)
Formula makees electrical connection, to save routing processing procedure.But flip chip manufacturing process need to plant a large amount of gold goal on single chips,
Process is time-consuming, also affects packaging efficiency.In addition to flip mode, some are separately had to be not required to the encapsulation side of routing
Formula, such as turning-over of chip will be located in the electrode of chip surface electrode directly and on support plate and stick together and do not use gold
Ball, such mode then needs the electrode making chip surface contour, and has splendid flatness, makes precision and wants
Ask higher, relatively make processing procedure difficulty higher.Another way is to adjust chip structure, makes chip electrode by core
Sheet surface extends to die bottom surface, such as the chip system disclosed in Japanese Patent Publication case JP2008-130875
Make method, as shown in Figures 2 and 3, be perforate 941 on chip 94, plate conductive layer 95, make to lead
The electrode 96 on chip 94 surface is connected with the electrode 97 of chip 94 bottom surface by electric layer 95 by perforate 941,
And make chip 94 electrode 97 can be located at its bottom surface.But in JP2008-130875 case, it defines perforate
The wall of 941 is vertical wall, when being coated with conductive layer, has the shortcoming that step coverage is bad, holds
It is easily caused conductive layer uneven and affect electric conductivity.
Summary of the invention
In order to solve aforesaid problem, the present invention utilizes and forms sloped sidewall in light-emitting diode chip for backlight unit both sides,
The inclined-plane produced by sloped sidewall, can make conductive layer easily uniform deposition on inclined-plane, to avoid ladder to cover
The shortcoming that lid is bad, and by the conductive layer on inclined-plane, the electrode on light-emitting diode chip for backlight unit surface is extended
To substrate both sides or the bottom surface of substrate of chip, follow-up encapsulation procedure, what is more, it is not required to make
Use routing, the volume of encapsulating structure can be reduced.
Further, the present invention also provides preparation method and the light-emitting diodes of the reflector utilizing manufacture of semiconductor technology
The method for packing of pipe, can be applicable to system encapsulation or wafer-level packaging.The preparation method of reflector of the present invention only needs profit
The groove structure that can complete to have reflecting layer with optical cover process, needs twice light compared to conventional process
Cover processing procedure, it is possible to reduce processing time and cost of manufacture.And the method for packing that the present invention provides need not routing
Processing procedure can be formed with the wire of encapsulating carrier plate and electrically connect, and can not only save processing time, promote and produce effect
Rate, moreover it is possible to reduce the volume of encapsulating structure.
Further, the present invention also provide for a kind of the electrode of light-emitting diode chip for backlight unit can be extended to encapsulation
The method for packing of the bottom surface of support plate, and it is not required to perforate in reflector, to avoid damage to the effect of encapsulating chip,
It is the easiest so that electrode to extend to caused chip bottom encapsulating carrier plate by reflector bottom opening to solve
Make moist and the problem of fragile structure of encapsulating structure, and its made encapsulating structure can be directly arranged at one
The circuit board of application product, is not required to use routing processing procedure, except reducing the fraction defective caused because of broken string, promotes
Encapsulation reliability, the assembly program that also can make downstream application end is easier.
Light-emitting diode chip for backlight unit provided by the present invention, makes the conductive layer of connection electrode extend by inclined-plane unit
To substrate inclined wall or bottom surface, light-emitting diode chip for backlight unit can be fixedly arranged in encapsulating carrier plate directly formation and be electrically connected
Connect, or utilize metallization process to make extension conductive layer formation electrical connection, owing to need not routing processing procedure, have
Help wafer-level packaging or system encapsulation, and the packaging time of routing one by one can be saved, and save routing institute
The space taken, to reduce volume, has a miniaturization advantage for integrating other photoelectric subassembly, and and other
LED technology is integrated, the such as integration of nano-crystals processing procedure, the most elastic.Additionally, the present invention is carried
The preparation method of the light-emitting diode chip for backlight unit of confession, by forming sloped sidewall and substrate inclined wall, with on its inclined-plane
Utilize metallization process to deposit conductive layer, be easily controlled compared to depositing conductive layer on the vertical plane, therefore can carry
Rise process rate, reduce manufacturing cost.
The preparation method of the reflector for LED package provided by the present invention, convexedly stretches in recessed by part
The shielding of the protective layer in groove, makes the layer gold layer being coated on groove without departing from slot opening, and can save together
Optical cover process, to reduce processing time and cost.
The method for packing of the light emitting diode of present invention offer, can complete the most several on same encapsulating carrier plate
The encapsulation of luminous diode chip, also can need not routing processing procedure, therefore more can be suitably used for wafer-level packaging or system
Encapsulation, may select applicable method step according to different LED chip constructions, will connect chip electricity
The conductive layer of pole extends outside reflector, further, moreover it is possible to by extending to encapsulating carrier plate bottom surface outside reflector,
With maintain chip seal integrity, make the method for packing of the present invention can not only save the encapsulation procedure time and
Reduce the volume of encapsulating structure, moreover it is possible to facilitate the assembly program of downstream application end.
Accompanying drawing explanation
Referring next to accompanying drawing and related embodiment, the present invention is described in detail and describes:
Fig. 1 is a schematic diagram, and a known light-emitting diode chip for backlight unit is described；
Fig. 2 is a top view, and the luminescence two disclosed in Japanese Patent Publication case JP2008-130875 is described
Pole die；
Fig. 3 is the sectional view of Fig. 2；
Fig. 4 (a)～Fig. 4 (f) is the enforcement step of the embodiment 1 of the preparation method that light-emitting diode chip for backlight unit of the present invention is described
Flow chart；
Fig. 5 is the top view of Fig. 4 (f), and the position of two electrode units of embodiment 1 is described；
Fig. 6 is a schematic diagram, and the embodiment 1 of light-emitting diode chip for backlight unit of the present invention is described；
Fig. 7 (a)～Fig. 7 (g) is the enforcement step stream of the embodiment 1 that LED encapsulation method of the present invention is described
Cheng Tu；
Fig. 8 is the flow chart of hookup 4 (a)～Fig. 4 (f), illustrate light-emitting diode chip for backlight unit of the present invention preparation method it
The enforcement step of embodiment 2；
Fig. 9 is a schematic diagram, and the embodiment 2 of light-emitting diode chip for backlight unit of the present invention is described；
Figure 10 (a)～Figure 10 (c) is the flow chart of hookup 7 (a)～Fig. 7 (d), and light emitting diode of the present invention is described
The enforcement step of the embodiment 2 of method for packing；
Figure 11 (a)～Figure 11 (f) is the enforcement step of the embodiment 3 that LED encapsulation method of the present invention is described
Flow chart；
Figure 12 (a)～Figure 12 (b) is the flow chart of Figure 11 (a)～Figure 11 (d) of continuing, and light-emitting diodes of the present invention is described
The enforcement step of the embodiment 4 of pipe method for packing；
Figure 13 (a)～Figure 13 (h) is the enforcement step of the embodiment 5 that LED encapsulation method of the present invention is described
Rapid flow chart；
Figure 14 is the top view of Figure 13 (h), and the position of the upper conductive layer of embodiment 5 is described；And
Figure 15 is a schematic diagram, and another encapsulation aspect of the light-emitting diode chip for backlight unit of embodiment 5 is described.
Detailed description of the invention
About addressing other technology contents, feature and effect before the present invention, following cooperation with reference to graphic it
In the detailed description of five preferred embodiments, can clearly present.
Before the present invention is described in detail, it is noted that, in the following description content, similar group
Part is to be identically numbered to represent.
Embodiment 1
The making of light-emitting diode chip for backlight unit
Refering to Fig. 4 (a)～Fig. 4 (f), the enforcement of the embodiment 1 of the preparation method of light-emitting diode chip for backlight unit of the present invention is described
Flow chart of steps.Implementation step comprises:
As shown in Fig. 4 (a), take a master slice 10 having completed epitaxial structure, master slice 10 include a substrate 11 and
One is formed at the epitaxial layer unit 12 on substrate 11.Epitaxial layer unit 12 includes that one is formed on substrate 11
The luminescent layer 122 that is formed in the first type semiconductor layer 121 of the first type semiconductor layer 121, one and a shape
Become the Second-Type semiconductor layer 123 on luminescent layer 122.In the present embodiment, substrate 11 is sapphire
(sapphire) material, thickness about 350 μm；First type semiconductor layer 121 is N-shaped gallium nitride (n-GaN),
Second-Type semiconductor layer 123 is p-type gallium nitride (p-GaN).
The patterning process utilizing manufacture of semiconductor technology defines a plurality of predetermined formation one on master slice 10
The position of chip and the position (not shown) of the predetermined groove formed between two chips.Following steps to be said
The bright sidewall and the electrode unit that how to utilize etching and metallization process to form each chip, rise for convenience of description
See, graphic in the implementation process between two adjacent chips is only shown.As shown in Fig. 4 (b), in predetermined formation
The position of groove 21 utilizes etch process to be etched to part the first type quasiconductor by Second-Type semiconductor layer 123
Layer 121, makes the first type semiconductor layer 121 exposed, and forms the groove 21 that an opening is expanded outward, the most just
It is to say to be formed in the side of each chip 1 down to be extended to part the first type half by Second-Type semiconductor layer 123 side
One first inclined-plane 131 of conductor layer 121 side.As shown in Fig. 4 (c), then between two recessed in the middle of chips 1
Bottom groove 21, the partial denudation surface of the i.e. first type semiconductor layer 121, the position of definition one second groove 22
Put, then etch that the first type semiconductor layer 121 to substrate 11 surface forms that an opening is expanded outward second
Groove 22, and make the part surface of substrate 11 exposed, thereby formed in the side of each chip 1 and be positioned at first
One second inclined-plane 132 and of type semiconductor layer 121 side adjacent substrate 11 is connected to the first inclined-plane 131
With the platform 133 on the second inclined-plane 132, and the 131, second inclined-plane 132, the first inclined-plane and platform 133 i.e. shape
Become one of epitaxial layer unit 12 down and the sloped sidewall 13 of past outer incline.The epitaxial layer unit of each chip 1
The opposite side of 12 is also formed one down also toward the inclination of outer incline from another group groove 21 and the second groove 22
Sidewall 13.Aforementioned etch process may utilize dry-etching or Wet-type etching, can be according to epitaxial layer unit 12
The etching mode that material selection is suitable, this is the known technology in field of the present invention, repeats no more in this.It is worth
It is noted that the enforcement step being previously formed groove 21 and the second groove 22 is only the one of embodiment,
Its also available different photoresistance thickness or halftoning site (halftone) processing procedure define simultaneously groove 21 with
The position of the second groove 22, and an available etching step or twice etching step formed groove 21 with
Second groove 22, is not limited with the present embodiment.
As shown in Fig. 4 (d), bottom the second groove 22, the most exposed substrate 11 surface, etch formation one
The substrate recess 23 that opening is expanded outward, thereby the chip 1 in substrate recess 23 both sides formed respectively one with
The substrate inclined wall 14 that its adjacent sloped sidewall 13 tilts in the same direction.Similarly, the substrate 11 of each chip 1
Opposite side concurrently form another substrate recess 23, and form another sloped sidewall 13 being adjacent in the same direction
The substrate inclined wall 14 tilted.Etch process may utilize dry-etching or Wet-type etching equally herein, at this
In embodiment, it is to utilize Wet-type etching mode, is mixed and heated using phosphoric acid and water and etches substrate as etching solution
11, make the inclination angle of substrate inclined wall 14 about between 40～60 degree.
As shown in Fig. 4 (e), utilize metallization process, on each chip 1, form two electrode units, be respectively
One forms, with the first type semiconductor layer 121, the first electrode unit 151 electrically connected, and one partly leads with Second-Type
Body layer 123 forms the second electrode unit 152 of electrical connection.First electrode unit 151 includes that one is located therein
The electrode 1511 on platform 133 surface of one sloped sidewall 13, and one by electrode 1511 along adjacent second
Inclined-plane 132 extends to the conductive layer 1512 on substrate inclined wall 14.Second electrode unit 152 includes that one sets
In the electrode 1521 on Second-Type semiconductor layer 123 surface, and one by electrode 1521 along another sloped sidewall 13
Extend to the conductive layer 1522 on substrate inclined wall 14.And the conductive layer 1522 of the second electrode unit 152
And it is initially formed an insulating barrier 153 between corresponding sloped sidewall 13, to avoid the first electrode unit 151
With the second electrode unit 152 short circuit.First electrode unit 151 and the second electrode unit 152 are at chip 1
On distribution can coordinate the top view refering to Fig. 5.Before forming electrode 1521, also partly can lead at Second-Type
Body layer 123 surface is coated to transparency electrode, if tin indium oxide (ITO) film (not shown) is to increase conduction all
Even property.
As shown in Fig. 4 (f), grind the bottom surface 111 of the substrate 11 being positioned at epitaxial layer unit 12 opposition side, will be each
Substrate recess 23 is worn out, makes the conductive layer 1512,1522 on each substrate inclined wall 14 expose bottom surface 111.
In this embodiment, substrate 11 thickness after grinding is about 50～100 μm.Afterwards, cutting master slice 10 is with shape
Become the most several independent chip 1.
Light-emitting diode chip for backlight unit
As shown in Figure 6, the embodiment 1 that chip 1 is light-emitting diode chip for backlight unit of the present invention that abovementioned steps prepares,
Comprise: substrate 11, epitaxial layer unit 12, two inclined-plane unit 16 and two electrode units 151,152.
Substrate 11 has surface 112 and a bottom surface 111.Epitaxial layer unit 12 is positioned at the surface 112 of substrate 11,
And include one first type semiconductor layer 121, luminescent layer 122 and a Second-Type semiconductor layer 123, first
Type semiconductor layer 121 is positioned at substrate 11 surface 112, and luminescent layer 122 is positioned at the first type semiconductor layer 121
And between Second-Type semiconductor layer 123.Two inclined-plane unit 16 lay respectively at two opposite sides, each inclined-plane unit
16 be the direction, bottom surface 111 from epitaxial layer unit 12 towards substrate 11 down and toward outer incline, respectively include position
In one of epitaxial layer unit 12 sloped sidewall 13, and it is positioned at one of substrate 11 substrate inclined wall 14.Respectively incline
Tiltedly sidewall 13 also includes that one is down extended to part the first type semiconductor layer by Second-Type semiconductor layer 123 side
First inclined-plane 131 of 121 sides and the second inclined-plane 132 of an adjacent substrate 11, and the first inclined-plane 131 and
It is connected by a platform 133 between two inclined-planes 132.Two electrode units 151,152 are respectively one and first
First electrode unit 151 of type semiconductor layer 121 electric connection, and one with Second-Type semiconductor layer 123
Second electrode unit 152 of electric connection.First electrode unit 151 includes that one is located therein a sloped sidewall
The electrode 1511 on platform 133 surface of 13 and and one being prolonged along the second adjacent inclined-plane 132 by electrode 1511
Extend the conductive layer 1512 on substrate inclined wall 14.Second electrode unit 152 includes being located at Second-Type half
The electrode 1521 on conductor layer 123 surface, and one extended to base by electrode 1521 along another sloped sidewall 13
Conductive layer 1522 on plate inclined wall 14.And the conductive layer 1522 of the second electrode unit 152 is with corresponding
Sloped sidewall 13 between be additionally provided with an insulating barrier 153.Additionally, substrate 11 also can be the base of tool electric conductivity
Plate, if substrate has electric conductivity, need to set insulating barrier on substrate inclined wall.In the present embodiment, substrate
The inclination angle of inclined wall 14, about between 40-60 degree, is conducive to being coated with extension on encapsulating carrier plate again during encapsulation and leads
Electric layer is connected with conductive layer 1512,1522, about the packaged type of light-emitting diode chip for backlight unit 1, and will be in
It is illustrated below.
The encapsulation of light emitting diode
Fig. 7 (a)～(g) illustrate the implementing procedure of the embodiment 1 of the method for packing of light emitting diode of the present invention, its
Middle Fig. 7 (a)～Fig. 7 (d) also illustrate the preparation method of the reflector of the present invention.As shown in Fig. 7 (a), carry in an encapsulation
Form a protective layer 31 on plate 3, then pattern protective layer 31, to form a perforation running through protective layer 31
311.In the present embodiment, encapsulating carrier plate 3 material is silicon, and protective layer 31 material is SiNx.Encapsulation carries
Plate 3 also can be other non-conductive material, the such as ceramic material such as aluminium nitride or aluminium oxide.Protective layer 31 material
Matter is alternatively SiOx、SiNx/SiOx, or metal (such as Ni, Au) etc., the formation side of protective layer 31
Method can use vapour deposition process (CVD) or high humidity high temperature furnace according to its material selection, such as non-metallic material
Processing procedure, metal material can be by modes such as plating, sputter or evaporations.
As shown in Fig. 7 (b), utilize etching solution by perforation 311 etching encapsulating carrier plate 3, form an opening 321
More than the groove 32 of perforation 311, the partial protection layer 31 of adjacent perforated 311 is made to convexedly stretch in groove 32.
In the present embodiment, etching solution is KOH solution, and the KOH solution of concentration 30vol% is in 80 DEG C or dense
The KOH solution of degree 45vol% is under the conditions of 85 DEG C, and etch-rate is about 1 μm/min.The choosing of etching solution
With adjusting according to actual demand, it is not limited with the present embodiment.
As shown in Fig. 7 (c), on protective layer 31 and groove 32, form a metal level 33,34, and by portion
Divide the shielding of the protective layer 31 convexedly stretched in groove 32, make at the adjacent protective layer of groove 32 31 (adjacent to opening
At mouth 321) non-coated metal layer 34.Metal level 33,34 can deposit by sputter or evaporation mode, material
Matter can be Ti/Al, Ti/Ni/Ag or other the most common reflecting layer material that may be used to reflect light.
As shown in Fig. 7 (d), remove protective layer 31 and the metal level 33 being positioned on protective layer 31, be left at groove
Metal level 34 in 32, i.e. forms a reflector 34 being positioned in groove 32.Formed by abovementioned steps
Reflector 34 only pattern protective layer 31 time need to use one optical cover process to define perforation 311
Position, the shielding of recycling protective layer 31 so that do not deposit metal level at adjacent recess 32 opening 321
34, so reflector 34 is without departing from groove 32 opening 321, and definition reflector 34 opening can be saved
Region is to avoid the optical cover process beyond groove 32 opening 321.
As shown in Fig. 7 (e), take an aforementioned prepared light-emitting diode chip for backlight unit 1 and be fixedly arranged in reflector 34.More
Further, light-emitting diode chip for backlight unit 1 is to utilize a crystal-bonding adhesive 38 to be fixed in reflector 34, at this
In embodiment, crystal-bonding adhesive 38 is isolation material so that the conductive layer 1512 of the first electrode unit 151 and
The conductive layer 1522 of two electrode units 152 is electrically isolated with reflector 34.
For another example shown in Fig. 7 (f), forming two extension conductive layers 35 with metallization process, each extension conductive layer 35 is respectively
The conductive layer 1512 of the first electrode unit 151 of connecting luminous diode chip 1 and the second electrode unit 152
Conductive layer 1522, and by substrate inclined wall 14 connect, the most also can be connected by sloped sidewall 13,
The first electrode unit 151 and the second electrode unit 152 is made to extend reflector by each extension conductive layer 35
On encapsulating carrier plate 3 outside 34, in the present embodiment, it is conduction due to reflector 34 and encapsulating carrier plate 3
Body, so before forming extension conductive layer 35, needing first preboarding on reflector 34 and encapsulating carrier plate 3
The position becoming to extend conductive layer 35 forms an insulating barrier 36, to avoid extending conductive layer 35 and reflector 34
And encapsulating carrier plate 3 contacts.As shown in Fig. 7 (g), in reflector 34, fill printing opacity glue material 37, to seal
Light-emitting diode chip for backlight unit 1.Printing opacity glue material 37 can be containing fluorescent material or without fluorescent material, depending on use demand
Fixed.
Although during in the present embodiment, light-emitting diode chip for backlight unit 1 is provided in reflector 34, but being previously formed
The enforcement step extending conductive layer 35 is equally applicable to general support plate, or general reflector.
Embodiment 2
The making of light-emitting diode chip for backlight unit
The enforcement step of the embodiment 2 of the preparation method of light-emitting diode chip for backlight unit of the present invention and embodiment 1 substantially phase
With, can coordinate refering to Fig. 4 (a)～Fig. 4 (f), be in place of its difference, as shown in Figure 8, at grinding base plate
After the bottom surface 111 ' of 11 ' is to expose the conductive layer 1512 ', 1522 ' of each substrate inclined wall 14 ', embodiment 2 profit
With metallization process formed in bottom surface 111 ' two respectively with the conductive layer 1512 ' of each substrate inclined wall 14 ',
The conductive layer 1513 ', 1523 ' that 1522 ' connect, makes the conduction of first, second electrode unit 151 ', 152 '
Layer 1512 ', 1513 ', 1522 ', 1523 ' extends to substrate 11 ' bottom surface 111 '.Additionally, in this metallization
Before fabrication steps, also can comprise further and bottom surface 111 ' is polished to provide a flatter and smooth surface
Step.Afterwards, each chip 1 ' on cutting master slice 10 ' is to form the most several independent chips 1 '.
Light-emitting diode chip for backlight unit
As it is shown in figure 9, the embodiment 2 that chip 1 ' is light-emitting diode chip for backlight unit of the present invention that abovementioned steps prepares,
Roughly the same with embodiment 1, it is in place of its difference, the first electrode unit 151 ' of embodiment 2 contains
Including a conductive layer 1513 ' extending substrate 11 ' bottom surface 111 ', and the second electrode unit 152 ' is containing including
One conductive layer 1523 ' extending substrate 11 ' bottom surface 111 '.
The encapsulation of light emitting diode
Figure 10 (a)～(c) illustrate the implementing procedure of the embodiment 2 of the method for packing of light emitting diode of the present invention, use
To encapsulate aforementioned light-emitting diode chip for backlight unit 1 '.
As shown in Figure 10 (a), prior to predetermined set light-emitting diode chip for backlight unit 1 ' bottom surface defined in reflector 34 '
The position (scheming non-label) of two conductive layers 1513 ', 1523 ' of 111 ', and utilize metallization process to form two
Extend conductive layer 35 ', make each extension conductive layer 35 ' respectively by the pre-determined bit of each conductive layer 1513 ', 1523 '
Put and extend on reflector 34 ' encapsulating carrier plate 3 ' outward.In the present embodiment, the reality of reflector 34 ' is formed
Execute step same as in Example 1, see Fig. 7 (a)～Fig. 7 (d).Due to reflector 34 ' and encapsulating carrier plate 3 '
It is electric conductor, so before forming extension conductive layer 35 ', needing first at reflector 34 ' and encapsulating carrier plate 3 '
The upper predetermined position forming extension conductive layer 35 ' forms an insulating barrier 36 ', to avoid extending conductive layer 35 '
Contact with reflector 34 ' and encapsulating carrier plate 3 '.
As shown in Figure 10 (b), a light-emitting diode chip for backlight unit 1 ' is fixedly arranged in reflector 34 ', and makes two to lead
Electric layer 1513 ', 1523 ' electrically connects with corresponding each conductive layer 35 ' that extends respectively.
As shown in Figure 10 (c), in reflector 34 ', fill printing opacity glue material 37 ', to seal light-emitting diode chip for backlight unit 1 '.
Printing opacity glue material 37 ' can be containing fluorescent material or without fluorescent material, depending on use demand.
Although in the present embodiment, light-emitting diode chip for backlight unit 1 ' is provided in reflector 34 ', but is previously formed extension
The enforcement step that conductive layer 35 ' connects with light-emitting diode chip for backlight unit 1 ' again is equally applicable to general support plate, or
General reflector.
Embodiment 3
Figure 11 (a)～Figure 11 (f) illustrates the embodiment 3 of LED encapsulation method of the present invention.
As shown in Figure 11 (a), it is coated to a guarantor in the front 411 of an encapsulating carrier plate 41 and the back side 412 the most respectively
Sheath 42, then pattern protective layer 42 and form plurality of through holes 421,422, arranges reflector defining reservation
Groove location 421, and lay respectively at groove location 421 both sides predetermined set and wear groove 44 (refering to Figure 11 (b))
Wear groove location 422.Be positioned at front 411 and the back side 412 to wear groove location about 422 corresponding.Such as figure
Shown in 11 (b), recycling etching solution etching encapsulating carrier plate 41, by the perforation 421 of protective layer 42 in encapsulation
Support plate 41 front 411 forms the groove 43 of a predetermined set reflector 471 (refering to Figure 11 (c)), makes recessed
The opening 431 of groove 43 is more than perforation 421, and by each perforation 422 by the front 411 of encapsulating carrier plate 41
And the back side 412 relatively etch and formed two be respectively adjacent to groove 43 wear groove 44.Groove 44 is worn by each
Form the sidewall 45 of its adjacent two encapsulating structures 4, and each sidewall 45 has one by encapsulating carrier plate 41 front
411 toward the top incline 451 and of middle flare from encapsulating carrier plate 41 back side 412 toward centre flare under
Inclined plane 452.In the present embodiment, the material of encapsulating carrier plate 41 is silicon, the material of protective layer 42 and erosion
Quarter, mode can refer to embodiment 1, no longer repeats in this.
As shown in Figure 11 (c), then deposited a metal level 47 by encapsulating carrier plate 41 front 411, make groove 43
And respectively wear the top incline 451 coated metal layer 47 of groove 44, its further groove 43 and protective layer 42 adjacent
Non-coated metal layer 47, and in groove 43, form a reflector 471.
As shown in Figure 11 (d), remove the protective layer 42 in encapsulating carrier plate 41 front 411 and the back side 412, due to
The encapsulating carrier plate 41 of the present embodiment has electric conductivity, after removing protective layer 42, by encapsulating carrier plate 41 just
Face 411 and the back side 412 depositing insulating layer 46.
As shown in Figure 11 (e), formation has predetermined at the back side 412 of encapsulating carrier plate 41 to utilize metallization process
The conductive layer 48 of pattern, is extended to each bottom incline 452 by encapsulating carrier plate 41 back side 412 respectively including two
Lower conductiving layer 481, and a conducting region 482 being positioned at encapsulating carrier plate 41 back side 412, conducting region 482
It is available for connecting with external radiating device (not shown).Or, conductive layer 48 also can be by lift-off processing procedure
Make.
As shown in Figure 11 (f), take light-emitting diode chip for backlight unit 1 as described in Example 1 and be fixedly arranged on reflector 471
In, coordinating refering to the step described in Fig. 7 (e)～Fig. 7 (g), the present embodiment 3 makes in embodiment 1 further
Extension conductive layer 35 extends to each top incline 451 and forms conductive layer 483 on two, each upper conductive layer 483
Be connected with corresponding each lower conductiving layer 481 respectively and respectively with the first electrode unit 151 and the second electrode
Unit 152 electrically connects, and makes first, second electrode unit 151,152 may extend to the back of the body of encapsulating carrier plate 41
Face 412.In reflector 471, fill a printing opacity glue material 49 sealed by light-emitting diode chip for backlight unit 1, with
Form an encapsulating structure 4.The visual demand of printing opacity glue material 49 contains fluorescent material or without fluorescent material.Aforementioned reality
Execute step and can complete the most several encapsulating structure 4 on same encapsulating carrier plate 41, many via preparing after cutting
Several independent encapsulating structures 4, each independent encapsulating structure 4 can be directly arranged at the circuit of an application product
Plate (not shown), is not required to use routing processing procedure, and facilitates the assembly program of downstream application end.
The packaged type of embodiment 3 utilizes is wearing groove 44 reflector 471 outside, make conductive layer 483 and under
Conductive layer 481 is connected, and can avoid damage to the sealing of light-emitting diode chip for backlight unit 1, and upper conductive layer
483 are respectively formed at top incline 451 and bottom incline 452 with lower conductiving layer 481, can make by inclined-plane
Metal level easily deposits, and can promote process rate.
Embodiment 4
Embodiment 4 is another embodiment of encapsulating light emitting diode chip for backlight unit 1 ' (refering to Fig. 9), and it is implemented
Step part is identical with the enforcement step of embodiment 3, refering to Figure 11 (a)～Figure 11 (d).Referring next to Figure 12 (a),
Metallization process is utilized to form the conductive layer 48 with predetermined pattern, bag at the back side 412 of encapsulating carrier plate 41
Include two lower conductiving layers 481 being extended to each bottom incline 452 respectively by encapsulating carrier plate 41 back side 412, and
One conducting region 482 being positioned at encapsulating carrier plate 41 back side 412, conducting region 482 is available for and external radiating device
(not shown) connects.And in the predetermined set light-emitting diode chip for backlight unit 1 ' end defined in reflector 471
The position of the conductive layer 1513 ', 1523 ' of first, second electrode unit 151 ', 152 ' in face, recycling gold
Genusization processing procedure forms conductive layer 483 ' on two, makes each upper conductive layer 483 ' respectively by first, second electrode list
The precalculated position (scheming non-label) of unit 151 ', 152 ' extends to each top incline 451, and with each lower conduction
Layer 481 is connected.Similarly, conductive layer 48 and the conductive layer 483 ' that powers on also may utilize lift-off processing procedure system
Make.
Refering to Figure 12 (b), fixed light-emitting diode chip for backlight unit 1 ' in reflector 471, and make two conductive layers 1513 ',
1523 ' electrically connect with corresponding each upper conductive layer 483 ' respectively, that is, make each upper conductive layer 483 ' respectively
With first, second corresponding electrode unit 151 ', 152 ' electrical connection.Fill thoroughly in reflector 471
Optical cement material 49, to seal light-emitting diode chip for backlight unit 1 '.Printing opacity glue material 49 can be containing fluorescent material or without fluorescence
Powder, depending on use demand.
Embodiment 5
Figure 13 (a)～Figure 13 (h) illustrates the enforcement step of the embodiment 5 of LED encapsulation method of the present invention.
The enforcement step of embodiment 5 can be used for encapsulating general electrode and is positioned at the light-emitting diode chip for backlight unit 5 in front.
Refering to Figure 13 (a) and Figure 13 (b), implementation step is roughly the same with Figure 11 (b) with Figure 11 (a) of embodiment 3,
Encapsulating carrier plate 41 is formed a groove 43 and two and wears groove 44, only, protective layer 42 and base plate for packaging 41
Between also have an insulating barrier 46.
Refering to Figure 13 (c), by groove 43 and wear the exposed surface oxidation of groove 44 and form oxide layer using as insulation
Layer 46 '.
Refering to Figure 13 (d), then deposited a metal level 47 by encapsulating carrier plate 41 front 411, make groove 43 and
Respectively wearing the top incline 451 coated metal layer 47 of groove 44, its further groove 43 is with protective layer 42 adjacent not
Coated metal layer 47, and in groove 43, form a reflector 471.
Refering to Figure 13 (e), remove the protective layer 42 in encapsulating carrier plate 41 front 411 and the back side 412, and utilize gold
Genusization processing procedure forms the conductive layer 48 with predetermined pattern at the back side 412 of encapsulating carrier plate 41, including two points
Do not extended to the lower conductiving layer 481 of each bottom incline 452 by encapsulating carrier plate 41 back side 412, and one is positioned at
The conducting region 482 at encapsulating carrier plate 41 back side 412, conducting region 482 is available for (scheming not with external radiating device
Illustrate) connect.
Refering to Figure 13 (f), a light-emitting diode chip for backlight unit 5 is installed in reflector 471, two conducting blocks are set
51 (scheme non-label), wherein at light-emitting diode chip for backlight unit 5 on two electrodes of this light-emitting diode chip for backlight unit 5
Each electrode on be respectively provided with a conducting block 51, make such conducting block 51 protrude outside reflector 471.At this
In embodiment, each conducting block 51 is the gold goal of the most about 50～100 μm.Although the present embodiment is the most fixed
Light-emitting diode chip for backlight unit 5 arranges conducting block 51 again, but after can also conducting block 51 be first set, then will send out
Luminous diode chip 5 is fixedly arranged in reflector 471, but combines this light emitting diode of this two conducting block 51
The whole height of chip 5 need to exceed this reflector 471 degree of depth.
As shown in Figure 13 (g), in reflector 471, fill printing opacity glue material 49 to seal light-emitting diode chip for backlight unit
5.The visual demand of printing opacity glue material 49 contains fluorescent material or without fluorescent material.
As shown in Figure 13 (h), after printing opacity glue material 49 solidifies, grind its surface, and make such conducting block 51
Partial denudation is in printing opacity glue material 49 surface.It is to say, the position of the exposed surface of such conducting block 51 is high
Position in reflector 471 opening.Coordinate refering to Figure 14, then it is each to form connection respectively with metallization process
Conducting block 51 also extends to conductive layer 483 on the two of top incline 451 ", make each upper conductive layer 483 " respectively
Electrically connect with each electrode, and each upper conductive layer 483 " connect with corresponding lower conductiving layer 481 respectively.It
Rear step is same as in Example 3, via the cutting the most several independent encapsulating structure 4 ' of feasible one-tenth.
The most applicable general reflector of step shown in aforementioned Figure 13 (f)～Figure 13 (h).As shown in figure 15, when instead
Penetrate cup 61 when being located at general encapsulating carrier plate 6, conductive layer 483 on aforementioned two " it is and extends reflector 61
The extension conductive layer 62 on encapsulating carrier plate 6 surface outside opening, extends conductive layer 62 and is available for and outer electrode (figure
Not shown) electrical connection.
Concluding above-mentioned, the preparation method of light-emitting diode chip for backlight unit 1,1 ' provided by the present invention, it is by formation
Sloped sidewall 13 and substrate inclined wall 14, with utilize on its inclined-plane metallization process deposition conductive layer 1512,
1512 ', it is easily controlled compared to depositing conductive layer on the vertical plane, therefore process rate can be promoted, reduce system
Cause this.
Additionally, light-emitting diode chip for backlight unit 1,1 ' provided by the present invention, by inclined-plane unit 16, the 16 ' company of making
The conductive layer 1512,1522,1512 ', 1522 ' of receiving electrode 1511,1521,1511 ', 1521 ' extends to
Substrate inclined wall 14, the conductive layer 1512,1522,1512 ', 1522 ' that furthers is connected with offer exposed electrical
Extension conductive layer 35,35 ' spacing, reduce broken string possibility.
Further, the light-emitting diode chip for backlight unit 1 of the present invention, make connection electrode by inclined-plane unit 16
1511, the conductive layer 1512,1522 of 1521 extends to substrate inclined wall 14, and light-emitting diode chip for backlight unit 1 '
Conductive layer 1513 ', 1523 ' extend to substrate 11 ' bottom surface 111 ', recycling metallization process makes and extends
Conductive layer 35,35 ' is formed with light-emitting diode chip for backlight unit 1,1 ' and electrically connects, then need not routing processing procedure, suitable
Encapsulate for wafer-level packaging or system, and the packaging time of routing one by one can be saved, and save routing institute
The space taken, to reduce volume, has a miniaturization advantage for integrating other photoelectric subassembly, and and other
LED technology is integrated, the such as integration of nano-crystals processing procedure, the most elastic.
From the enforcement step described in embodiment 1～embodiment 5, the envelope of the light emitting diode of present invention offer
Dress method need not routing processing procedure, can be suitably used for wafer-level packaging or system encapsulation, according to different luminescences two
Pole die 1,1 ', 5 structure may select applicable method step.Further, such as embodiment 3～enforcement
Described in example 5, moreover it is possible to form the encapsulating structure 4,4 ' of the circuit board that can be directly arranged at an application product, no
Routing processing procedure need to be used, the encapsulation procedure time can not only be saved and reduce the volume of encapsulating structure 4,4 ',
The assembly program of downstream application end can also be facilitated.
Additionally, such as Fig. 7 (a)-7 (d), 10 (a), 11 (a)-11 (e), 12 (a) and the encapsulation side shown in 13 (a)-13 (e)
Method, encapsulating carrier plate framework and reflector framework, do not limit the light-emitting diodes being only applicable to disclosed herein
Die 1,1 ', is equally applicable for generally a light emitting diode chip.
Only as described above, only the preferred embodiments of the invention, real when the present invention can not be limited with this
The scope executed, becomes according to the simple equivalence that scope of the present invention patent and invention description content are made the most generally
Change and modify, being all still covered by the present invention within the scope of the patent.
Claims (8)
1. a method for packing for light-emitting diode chip for backlight unit, utilizes manufacture of semiconductor to make, and step comprises:
Form a protective layer on an encapsulating carrier plate；
Pattern this protective layer, to form a perforation running through this protective layer；
Etch this encapsulating carrier plate, form the opening groove more than this perforation, make the portion of this perforation adjacent
This protective layer is divided to convexedly stretch in this groove；
Form a metal level on this protective layer and this groove, wherein this groove and this protective layer adjacent
Non-coated metal layer；
Removing this protective layer and be positioned at the metal level on this protective layer, it is anti-that formation one is positioned in this groove
Penetrate cup；
Utilize the fixed light-emitting diode chip for backlight unit of isolation material crystal-bonding adhesive reflector in this groove
On so that the conductive layer of the first electrode unit of light-emitting diode chip for backlight unit and the conductive layer of the second electrode unit with
Reflector is electrically isolated；
Formed two extension conductive layers, this two extend conductive layer be electrically connected this light-emitting diode chip for backlight unit it
The conductive layer of the first electrode unit and the conductive layer of the second electrode unit, make this first electrode unit and the second electricity
Pole unit extends on the package carrier outside this reflector by respectively this extension conductive layer；And
On this reflector and encapsulating carrier plate, the predetermined position forming extension conductive layer forms an insulating barrier,
This insulating barrier to should two extend conductive layers position.
2. according to the method for packing of light-emitting diode chip for backlight unit described in claim 1, it is characterised in that fixed this
After step on luminous diode chip reflector in this groove, also comprise:
Filling printing opacity glue material is in this reflector, to seal this light-emitting diode chip for backlight unit.
3. according to the method for packing of the light-emitting diode chip for backlight unit described in claim 1, it is characterised in that this is first years old
The conductive layer of the conductive layer of electrode unit and this second electrode unit extends to the base of light-emitting diode chip for backlight unit
The bottom surface of plate, and electrically connect with corresponding respectively this extension conductive layer respectively.
4. according to the method for packing of the light-emitting diode chip for backlight unit described in claim 1, it is characterised in that
After etching the step of this encapsulating carrier plate, also comprise
Being formed and be respectively adjacent to the two of this groove and wear groove in this encapsulating carrier plate, wherein, respectively this wears the sidewall of groove
Have one from this encapsulating carrier plate front toward the top incline of middle flare and one from this encapsulating carrier plate back side toward in
Between the bottom incline of flare；
After this light-emitting diode chip for backlight unit fixed step on this reflector, also comprise
Form two lower conductiving layers being extended to respectively this bottom incline respectively by this encapsulating carrier plate back side；
Formation extends to respectively this top incline, and conductive layer on be connected with respectively this lower conductiving layer two；
It is electrically connected with the first electrode unit and second electricity of respectively conductive layer and this light-emitting diode chip for backlight unit on this
Pole unit；And
Fill printing opacity glue material to be sealed by this light-emitting diode chip for backlight unit in this reflector.
5. according to the method for packing of the light-emitting diode chip for backlight unit described in claim 4, it is characterised in that this is first years old
The conductive layer of the conductive layer of electrode unit and this second electrode unit extends to the bottom surface of substrate, and difference
With corresponding respectively this conductive layer electrical connection on two.
6. according to the method for packing of the light-emitting diode chip for backlight unit described in claim 4 or 5, it is characterised in that being formed should
Reflector with this two step wearing groove is:
Form a protective layer at the front of this encapsulating carrier plate and the back side；
Form a plurality of perforation running through respectively this protective layer, to define this groove and this two position wearing groove；
Etching this encapsulating carrier plate and form this groove and this two wears groove, wherein the opening of this groove is right more than it
The perforation answered, makes this protective layer of part convexedly stretch in this groove；
Deposit a metal level in this encapsulating carrier plate front, wherein this groove and this protective layer adjacent not by
Metal-clad；And
Remove this protective layer in front and the back side, and form this reflector being positioned in this groove.
7. according to the method for packing of the light-emitting diode chip for backlight unit described in claim 4, it is characterised in that form this reflection
Form the step of insulating barrier after Bei, make this two lower conductiving layer at this encapsulating carrier plate back side and this lead on two
Electric layer is correspondingly formed on this insulating barrier.
8., for an encapsulating structure for light emitting diode chip, comprise:
One encapsulating carrier plate, its upper surface has a groove；
One metal level, is positioned at groove except the residue part of adjacent recess opening part so that formation anti-
Penetrate cup without departing from slot opening；
One light-emitting diode chip for backlight unit, has two electrode units, and utilizes an isolation material crystal-bonding adhesive fixed
On this reflector so that the conductive layer of the first electrode unit of light-emitting diode chip for backlight unit and the second electrode unit
Conductive layer electrically isolated with reflector；
Two extend conductive layer, are electrically connected conductive layer and second electrode unit of this first electrode unit
Conductive layer, make this first electrode unit and the second electrode unit extend this by respectively this extension conductive layer anti-
Penetrate on the package carrier of cup；
One insulating barrier, the predetermined position forming extension conductive layer on this reflector and encapsulating carrier plate, should
Insulating barrier to should two extend conductive layers position；And
One printing opacity glue material, is filled in this reflector, to seal this light-emitting diode chip for backlight unit.
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| CN201210312384.1A CN102820411B (en) | 2009-02-19 | 2009-02-19 | Light-emitting diode chip for backlight unit, preparation method and method for packing |
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| CN200910037346.8A CN101515621B (en) | 2009-02-19 | 2009-02-19 | Light-emitting diode chip, manufacturing method and packaging method |
| CN201210312384.1A CN102820411B (en) | 2009-02-19 | 2009-02-19 | Light-emitting diode chip for backlight unit, preparation method and method for packing |
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| CN1973355A (en) * | 2004-04-15 | 2007-05-30 | 泽斯吸气剂公司 | Integrated getter for vacuum or inert gas packaged LEDs |
| CN101038949A (en) * | 2006-03-14 | 2007-09-19 | 三星电机株式会社 | Light emitting diode package |
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| CN100490195C (en) * | 2006-03-16 | 2009-05-20 | 先进开发光电股份有限公司 | Packaging structure of solid-state light-emitting element and manufacturing method thereof |
| US20070228386A1 (en) * | 2006-03-30 | 2007-10-04 | Jin-Shown Shie | Wire-bonding free packaging structure of light emitted diode |
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| CN1973355A (en) * | 2004-04-15 | 2007-05-30 | 泽斯吸气剂公司 | Integrated getter for vacuum or inert gas packaged LEDs |
| CN101038949A (en) * | 2006-03-14 | 2007-09-19 | 三星电机株式会社 | Light emitting diode package |
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