CN102820055A - Data readout circuit for phase change memorizer - Google Patents

Abstract

A data readout circuit of a phase-change memory with switchable read voltage/read current, comprising: a foil bit voltage generating circuit; a precharge circuit; a foil bit circuit, having a first working mode for generating foil bit current and generating a pre-amplified voltage The second working mode; the read mode switching circuit, under the control of the read mode selection signal, selects the read current mode or the read voltage mode; the current voltage conversion circuit, in the read current mode, performs operations on the foil bit current and the reference current, and converts them into complementary Two voltages; the comparison amplifier circuit compares the selected two voltages and outputs the readout result; in the current reading mode, the two voltages are the two voltages formed by the current-voltage conversion circuit; in the voltage reading mode, the two voltages The voltage is the pre-amplification voltage and the reference voltage in read voltage mode. Compared with the prior art, the data readout circuit of the present invention realizes the switching of read voltage/read current, and can select a matching read mode for different load conditions.

Description

Data readout circuit of phase change memory

technical field

The invention relates to a phase-change memory, in particular to a data readout circuit of a phase-change memory with switchable read voltage/read current.

Background technique

Phase change memory (PC-RAM) is a new type of resistive nonvolatile semiconductor memory. Compared with various semiconductor storage technologies currently available, it has low power consumption, non-volatile, high density, and radiation resistance. Lighting, non-volatile, high-speed reading, long cycle life (>10 ¹³ times), device size shrinkability (nanoscale), high and low temperature resistance (-55°C to 125°C), anti-vibration, anti-electronic interference and The manufacturing process is simple (can be matched with the existing integrated circuit process) and other advantages, and it is the most powerful competitor in the next-generation memory widely favored by the industry at present, and has a broad market prospect.

Phase-change memory uses chalcogenide material as the storage medium, and uses the Joule heat generated by electric pulse or light pulse to make the phase-change memory material between the amorphous state (the material is in a high resistance state) and the crystalline state (the material is in a low resistance state). Reversible phase change occurs to realize data writing and erasing, and data reading is realized by measuring the state of resistance.

The data stored in the phase change memory (that is, the crystalline state or amorphous state of the phase change unit) is read through the data readout circuit. Considering that its intuitive characteristics are low resistance state or high resistance state, therefore, the phase change The memory is controlled by the read enable signal and the data readout circuit, inputting a small amount of current or voltage to the phase change memory unit of the phase change memory, and then measuring the voltage value or current value on the phase change memory unit. Achieved.

Generally, the data readout circuit sends a tiny current value (voltage value) to the phase-change memory cell, and at this time reads the voltage (current) of the bit line. If the voltage of the bit line is higher (lower current), it indicates a phase change. The cell is in a high resistance state, that is, "1"; if the bit line voltage is low (the current is large), it means that the phase change cell is in a low resistance state, that is, "0". However, in the process of reading, when a current flows through the phase-change memory cell, the phase-change memory cell will generate Joule heat. If the power of Joule heat is greater than the heat dissipation efficiency of the phase-change memory cell, this thermal effect will affect the phase-change memory cell. At the same time, when the voltage difference between the two ends of the phase-change memory cell exceeds a certain threshold, the internal carriers of the phase-change material will undergo a breakdown effect, and the carriers will increase suddenly, showing low-resistance characteristics, but this The material itself does not undergo a phase transition. The above two phenomena are the so-called read corruption phenomenon.

In order to avoid the above-mentioned reading destruction phenomenon, the data readout circuit needs to meet the following requirements: the readout current (voltage) must be very small so that the power of Joule heat does not exceed the heat dissipation efficiency of the phase change memory unit; When the reading current (voltage) is appropriately large, the reading speed must be very fast so that the Joule heat generated does not have time to change the basic state of the cell, and the maximum value of the reading current (voltage) must be less than the phase change The internal carrier breakdown threshold of the unit is used to prevent the internal carrier breakdown effect of the phase change material.

For an ideal phase-change memory, the above requirements are achievable. However, in an actual phase-change memory, due to the existence of the parasitic capacitance on the bit line, it will take a long time to read the current (voltage) while satisfying the above requirements. Because the data readout circuit needs to wait for the readout current (voltage) to charge the bit line capacitor before it can correctly read the state of the phase change memory cell, which greatly restricts the speed characteristics of the phase change memory.

Generally speaking, the phase-change memory readout circuit can be divided into a read current mode and a read voltage mode, wherein the phase-change memory readout circuit in the read current mode has a faster reading speed than the phase-change memory readout circuit in the read voltage mode. output rate, and the phase change memory readout circuit in the read voltage mode has lower power consumption than the phase change memory readout circuit in the read current mode. At the same time, the read rate and power consumption are limited by the size of the load parasitic capacitance and the high and low resistance range of the phase-change memory unit, and the load parasitic capacitance of the readout circuit and the high-low resistance resistance of the phase-change memory unit are related to the These uncertain parameters pose a serious challenge to how to design a high-speed, low-power, high-performance readout circuit.

Therefore, how to improve the above problems such as the parasitic load capacitance and the high and low resistance state resistance range of the storage unit taking too long to read data, low high and low resistance state resolution, and large power consumption has become an urgent problem to be solved by those skilled in the art. technical issues.

Contents of the invention

The object of the present invention is to provide a data readout circuit of a phase-change memory with switchable read voltage/read current, which is used to solve the problem of incompatibility between data readout rate and power consumption in the prior art.

In order to solve the above and other problems, the present invention provides a data readout circuit of a phase-change memory with switchable read voltage/read current. The phase-change memory includes one or more phase-change memory cells, and each phase-change memory cell Connected to the control circuit through a bit line and a word line; the data reading data includes: a bit voltage generating circuit for generating a bit voltage; a pre-charging circuit for storing the memory cell under the control of the bit voltage The bit line is charged quickly; the bit line is controlled by the bit voltage, and has the first operation mode of bit line generation in the read current mode to generate a bit current and pre-sets the bit line signal in the read voltage mode. Amplify to generate the second working mode of the pre-amplified voltage; the read mode switching circuit selects the read current mode or the read voltage mode under the control of the read mode selection signal, and controls the foil bit circuit to execute the first work mode corresponding to the read current mode or the corresponding read voltage The second working mode of the mode, and select the two voltages that need to be compared; the current-voltage conversion circuit, in the case that the reading mode switching circuit selects the reading current mode, will generate the foil bit current and the reference current in the reading current mode Carry out calculations and convert them into two complementary voltages; compare the amplifier circuit, compare the two voltages selected by the read mode switching circuit, and output the readout result: in the current reading mode, the two voltages selected by the read mode switching circuit The voltage includes two complementary voltages formed by the current-voltage conversion circuit; in the voltage reading mode, the two voltages selected by the read mode switching circuit include the pre-amplified voltage and the pre-amplified voltage for pre-amplifying the bit line signal by the bit circuit Reference voltage in read voltage mode.

Optionally, the data readout circuit further includes a bit line transmission gate connected in series on the bit line, so that the precharge circuit and the foil bit current generating circuit communicate with the bit line transmission gate through the bit line transmission gate. bit line connection.

Optionally, the data readout circuit further includes a discharge circuit, configured to discharge residual charges on the bit line and the load terminal of the data readout circuit after the comparison amplifier circuit completes the comparison amplification operation.

Optionally, the discharge circuit includes a controlled first nMOS transistor connected between the precharge circuit and a ground line, and a controlled second nMOS transistor connected between the bit line and the ground line.

Optionally, the data readout circuit further includes a bit line bias current circuit for providing a bias current to the bit line.

Optionally, the bit line bias current circuit includes a current mirror structure formed by two pMOS transistors, wherein the drain of the first pMOS transistor is connected to the bias current source, and the drain of the second pMOS transistor is connected to the Foil bit circuit connections.

Optionally, when the bit line bias current circuit is in the voltage reading mode and the current reading mode, the bias current sources have different currents.

Optionally, the foil bit voltage generation circuit includes a current source, a first nMOS transistor connected in a diode form, and a second nMOS transistor connected in series with the first nMOS transistor, the drain of the first nMOS transistor is connected to the current source The current output terminal of the first nMOS transistor is connected, the gate of the first nMOS transistor is connected to the gate of the second nMOS transistor, the source of the first nMOS transistor is connected to the drain of the second nMOS transistor, and the source of the second nMOS transistor is grounded.

Optionally, the pre-charging circuit includes a pre-charging switch tube and a pre-charging nMOS tube connected in series with the pre-charging switch tube.

Optionally, the foil bit circuit includes a foil bit nMOS transistor.

Optionally, the read mode switching circuit includes: a current-voltage conversion circuit control switch; a comparison amplifier circuit input signal selection switch, including a switch for respectively connecting the first voltage generated by the current-voltage conversion circuit and the positive voltage of the comparison amplifier in the current-reading mode. Input terminal, the pre-amplified voltage and the positive input terminal of the comparison amplifier in the voltage reading mode, the second voltage generated by the current-voltage conversion circuit and the negative input terminal of the comparison amplifier in the current reading mode, the reference voltage and the negative input terminal of the comparison amplifier in the voltage reading mode four transmission gates; and an inverter for inverting the read mode selection signal to obtain an inverse signal of the read mode selection signal.

Optionally, the read mode selection signal and the inverse signal of the read mode selection signal passed through the inverter are respectively loaded on the control terminals of the four transmission gates and the control terminal of the current-voltage conversion circuit control switch; when the selection signal is "1", The current-voltage conversion circuit controls the switch to be closed, and the transmission gate connected to the pre-amplification voltage and the positive input terminal of the comparative amplifier and the transmission gate connected to the reference voltage of the reading voltage mode and the negative input terminal of the comparative amplifier are turned on; otherwise, when the selection signal is "0", The current-voltage conversion circuit controls the switch to open, and connects the first voltage generated by the current-voltage conversion circuit in the current-reading mode to the transmission gate of the positive input of the comparison amplifier, and connects the second voltage generated by the current-voltage conversion circuit to the comparison amplifier in the current-reading mode The transmission gate on the negative input turns on.

Optionally, the comparison amplifier circuit includes a voltage comparator.

The data readout circuit of the read voltage/read current switchable phase-change memory provided by the present invention can select between the read current mode and the read voltage mode under the control of the read mode selection signal, so that it can be selected for different load conditions. The matching read mode achieves the best effect of read rate, high and low resistance state resolution, and power consumption.

In addition, the data readout circuit of the phase change memory provided by the present invention also includes a discharge circuit, which can effectively discharge residual charges, reduce or even eliminate data crosstalk, and improve data readout speed and reliability of data readout.

Description of drawings

Fig. 1 is a schematic diagram of the load array structure of the data readout circuit of the phase change memory;

2 is a schematic circuit structure diagram of the data readout circuit of the read voltage/read current switchable phase change memory of the present invention;

FIG. 3 is a schematic diagram of a circuit structure of a data readout circuit of a phase change memory with switchable read voltage/read current in a specific embodiment of the present invention.

Detailed ways

The inventors of the present invention have found that the data readout circuit of the traditional phase change memory adopts a single read mode (either read current mode or read voltage mode), which has weak adaptability and cannot be selected to match it according to the load condition. In the read mode, data readout speed and power consumption cannot be achieved at the same time, and it is difficult to obtain the best performance effect.

Therefore, in order to prevent the occurrence of the above-mentioned defects, the inventors of the present invention have improved the prior art and proposed a data readout circuit with switchable read voltage/read current, which has both the read current mode and the read voltage mode, and The matching read current mode or read voltage mode can be selected according to different load conditions, so as to achieve the best effect of read rate, high and low resistance state resolution, and power consumption.

The data readout circuit of the phase change memory of the invention will be described in detail below through specific embodiments.

The invention is described more fully below with reference to the drawings, which provide preferred embodiments, but should not be considered limited to the embodiments set forth herein. The referenced figures are schematic views of the present invention, and the representations in the figures are only schematic in nature and should not be considered as limiting the scope of the present invention.

FIG. 1 is a schematic structural diagram of a load array of a data readout circuit of a phase change memory. As shown in Figure 1, the load end of a data readout circuit will be respectively connected to multiple (for example, p) bit lines through multiple bit line transmission gates, and at the same time, multiple (for example, p) bit lines are connected in parallel on each bit line q) phase-change memory cells. In addition, a parasitic capacitance Cp_ is connected to the load end of the data readout circuit, and a parasitic capacitance Cp is connected to the load end of each bit line transmission gate.

FIG. 2 is a schematic circuit structure diagram of a data readout circuit of a phase-change memory with switchable read voltage/read current according to the present invention. As shown in Figure 2, a memory cell in a phase-change memory has a bit line and a word line, and the read voltage/current mode switchable data readout circuit includes: a bit line transmission gate, a foil bit voltage generation circuit, a precharge circuit, Foil bit circuit, bit line bias current circuit, read mode switch circuit, current voltage conversion circuit, comparison amplifier circuit, and discharge circuit.

The data readout circuit is connected to the bit line BL of the memory cell through the bit line transmission gate;

The foil bit voltage generating circuit is used for generating the foil bit voltage. In the present invention, the foil bit voltage generation circuit includes: a bias current source I _bias , an nMOS transistor M11 connected in a diode form, and an nMOS transistor M12 connected in series with the nMOS transistor M11 .

The precharge circuit is used for fast charging the bit line of the storage unit. In the present invention, the pre-charging circuit includes a pre-charging switching tube M3 and a pre-charging nMOS tube M2b connected in series with the pre-charging switching tube M3.

The foil bit circuit has a first working mode in which the bit line is clamped to generate a blank bit current in the read current mode and a second working mode in which the bit line signal is pre-amplified to generate a pre-amplified voltage in the read voltage mode. In the present invention, the foil bit circuit includes a foil bit nMOS transistor M2a.

The bit line bias current circuit is used for providing bias current to the bit line. In the present invention, the bit line bias current circuit includes a current mirror structure formed by two pMOS transistors M4, M5a.

The read mode switching circuit selects the read current mode or the read voltage mode under the control of the read mode selection signal, controls the foil bit circuit to execute the first working mode corresponding to the reading current mode or the second working mode corresponding to the reading voltage mode, and selects the Two voltages. In the present invention, the read mode switching circuit is composed of nMOS transistor M7 and a comparative amplifier input selector (CMP input selector), and is controlled by the read mode select signal.

The current-voltage conversion circuit converts the bit current generated in the current reading mode into a voltage when the reading mode switching circuit selects the current reading mode.

The comparison amplifier circuit compares the voltage converted from the current voltage in the current reading mode or compares the pre-amplified voltage with the reference voltage in the voltage reading mode, thereby outputting the read result. In the present invention, the comparison amplifier circuit is a voltage comparator.

The data readout circuit of the present invention further includes a discharge circuit for discharging the remaining charge on the bit line and the load terminal of the data readout circuit after the comparison amplifier circuit completes the comparison amplification operation. In the present invention, the discharge circuit includes a controlled nMOS transistor M1a connected between the precharge circuit and the ground line and a controlled nMOS transistor M1b connected between the bit line and the ground line.

FIG. 3 is a schematic diagram of a circuit structure of a data readout circuit of a phase change memory with switchable read voltage/read current in a specific embodiment of the present invention. As shown in Figure 3, the data readout circuit includes: a bit line transmission gate, a foil bit voltage generating circuit, a precharge circuit, a foil bit circuit, a bit line bias current circuit, a read mode switching circuit, a current voltage conversion circuit, Compare amplifier circuits and discharge circuits.

The data readout circuit is connected to the bit line BL of the memory cell through the bit line transmission gate;

The foil bit voltage generating circuit is used for generating the foil bit voltage. In this embodiment, the foil bit voltage generating circuit includes: a bias current source I _bias , an nMOS transistor M11 connected in the form of a diode, and an nMOS transistor M12 connected in series with the nMOS transistor M11, the drain of the nMOS transistor M11 is connected to the bias The current output terminal of the current source I _bias is connected, the gate of nMOS transistor M11 is connected to the drain of nMOS transistor M11, the gate of nMOS transistor M12 is connected, the source of nMOS transistor M11 is connected to the drain of nMOS transistor M12, and the nMOS transistor M11 is connected to the drain of nMOS transistor M12. The source of M12 is grounded.

A pre-charging circuit is configured to rapidly charge the bit line of the storage unit under the control of the foil bit voltage. In this embodiment, the pre-charging circuit includes a pre-charging switching tube M3 and a pre-charging nMOS transistor M2b connected in series with the pre-charging switching tube M3. The pre-charge switch tube M3 is actually a pMOS tube, the gate of the pMOS tube M3 is connected to the pre-charge enable signal, the source of the pMOS tube M3 is connected to the voltage source Vdd, and the drain of the pMOS tube M3 is connected to the pre-charge foil bit of the nMOS tube M2b. The drain is connected, the gate of the pre-charged foil-position nMOS transistor M2b is connected to the gate of the nMOS transistor M11 and the gate of the nMOS transistor M12 (receiving the foil-bit voltage), the source of the pre-charged foil-position nMOS transistor M2b is connected to the bit line Transmission gate connection.

The foil bit circuit, controlled by the foil voltage, has the first working mode of foiling the bit line in the read current mode to generate the foil bit current and the pre-amplification of the bit line signal in the read voltage mode to generate the pre-amplified voltage Second working mode. In this embodiment, the foil bit circuit includes a foil bit nMOS transistor M2a, wherein the gate of the foil bit nMOS transistor M2a is connected to the gate of the nMOS transistor M11 and the gate of the nMOS transistor M12 (receiving the foil bit voltage) , the source of the low-bit nMOS transistor M2a is connected to the source of the pre-charged low-bit nMOS transistor M2b and the bit line transmission gate, and the drain of the low-bit nMOS transistor M2a outputs a low-bit current I _Cell .

The bit line bias current circuit is used for providing bias current to the bit line. In this embodiment, the bit line bias current circuit includes a current mirror structure formed by two pMOS transistors M4 and M5a, wherein the gate of the pMOS transistor M4 is connected to the gate of the pMOS transistor M5a, and the pMOS transistor M4 The gate of the pMOS transistor M4 is connected to the drain, the source of the pMOS transistor M4 is connected to the power supply voltage Vdd, the drain of the pMOS transistor M4 is connected to the bias current source, the source of the pMOS transistor M5a is connected to the power supply voltage Vdd, and the pMOS transistor M5a The drain is connected to the drain of the foil bit nMOS transistor M2a in the foil bit circuit.

The read mode switching circuit selects the read current mode or the read voltage mode under the control of the read mode selection signal, controls the foil bit circuit to execute the first working mode corresponding to the reading current mode or the second working mode corresponding to the reading voltage mode, and selects the Two voltages. In this embodiment, the read mode switching circuit includes: a current-voltage conversion circuit control switch, a comparison amplifier circuit input signal selection switch including four transmission gates TG0, TG1, TG2, TG3, and an inverter INV0.

Specifically, the current-voltage conversion circuit control switch is composed of read mode selection switch tubes (pMOS transistors M9a, M9b), wherein the gate of pMOS transistor M9a is connected to the gate of pMOS transistor M9b, and the source of pMOS transistor M9a It is connected to the drain of the pMOS transistor M5b (the gate of the pMOS transistor M5b is connected to the drain of the pMOS transistor M5b, and the source of the pMOS transistor M5b is connected to the power supply voltage Vdd), and the drain of the pMOS transistor M9a is connected to the foil in the foil bit circuit. The drain of the nMOS transistor M2a is connected, the source of the pMOS transistor M9b is connected to the drain of the pMOS transistor M8 (the gate of the pMOS transistor M8 is connected to the drain of the pMOS transistor M8, and the source of the pMOS transistor M8 is connected to the power supply voltage Vdd) , the drain of the pMOS transistor M9b is connected to the reference current source I _ref . The control switch of the current-voltage conversion circuit is controlled by the read mode selection signal RMod. Here, the gate of the pMOS transistor M9a and the gate of the pMOS transistor M9b are used to receive the read mode selection signal RMod.

The transmission gate TG0 is used to connect the first voltage C1 generated by the current-voltage conversion circuit in the current reading mode and the positive input terminal of the comparative amplifier, and the transmission gate TG1 is used to connect the pre-amplified voltage V1 and the positive input terminal of the comparative amplifier in the voltage reading mode. The gate TG1 is used to connect the second voltage C2 generated by the current-voltage conversion circuit and the negative input terminal of the comparative amplifier in the current reading mode, and the transmission gate TG1 is used to connect the reference voltage V2 (that is, V _ref ) and the negative input of the comparative amplifier in the voltage reading mode end. In this embodiment, the comparative amplifier is a voltage comparator (CMP).

The inverter INV0 is used to invert the read mode selection signal. Specifically, the input terminal of the inverter INV0 is used to receive the read mode selection signal RMod, and is connected to the control terminals of each transmission gate TG0, TG1, TG2, TG3, and the output terminal of the inverter INV0 outputs the inverse signal of the read mode selection signal and each The control terminals of the transmission gates TG0, TG1, TG2 and TG3 are connected. The opening and closing of each transmission gate TG0, TG1, TG2, TG3 can be controlled by using the read mode selection signal and the read mode selection signal after passing through the inverter INV0.

The current-voltage conversion circuit converts the bit current generated in the current reading mode into a voltage when the reading mode switching circuit selects the current reading mode. In this embodiment, the current-voltage conversion circuit is composed of pMOS transistors M6a, M6b, M6c, M6d and nMOS transistors M7a, M7b, M7c, M7d, wherein the gate of pMOS transistor M6a and the gate of pMOS transistor M5b pole, the drain of pMOS transistor M5b is connected, the source of pMOS transistor M6a is connected to the power supply voltage Vdd, the drain of pMOS transistor M6a is connected to the drain of nMOS transistor M7a, and the gate of nMOS transistor M7a is connected to the drain of nMOS transistor M7a , the source of the nMOS transistor M7a is grounded; the gate of the pMOS transistor M6b is connected to the gate of the pMOS transistor M6a, the source of the pMOS transistor M6b is connected to the power supply voltage Vdd, the drain of the pMOS transistor M6b is connected to the drain of the nMOS transistor M7b, The gate of the nMOS transistor M7b is connected to the gate of the nMOS transistor M7d, and the source of the nMOS transistor M7b is grounded; the gate of the pMOS transistor M6c is connected to the gate of the pMOS transistor M6d, and the source of the pMOS transistor M6c is connected to the power supply voltage Vdd. The drain of the transistor M6c is connected to the drain of the nMOS transistor M7c, the gate of the nMOS transistor M7c is connected to the gate of the nMOS transistor M7a, and the source of the nMOS transistor M7c is grounded; the gate of the pMOS transistor M6d is connected to the gate of the pMOS transistor M8 connection, the source of the pMOS transistor M6d is connected to the power supply voltage Vdd, the drain of the pMOS transistor M6d is connected to the drain of the nMOS transistor M7d, the gate of the nMOS transistor M7d is connected to the drain of the nMOS transistor M7d, and the source of the nMOS transistor M7d is grounded .

The discharge circuit is used for discharging the remaining charge on the bit line and the load end of the data readout circuit after the comparison and amplification circuit completes the comparison and amplification operation. In this embodiment, the discharge circuit includes a controlled nMOS transistor M1a connected between the precharge circuit and the ground line, and a controlled nMOS transistor M1b connected between the bit line and the ground line. The gate of the controlled nMOS transistor M1a is connected to the discharge voltage, the source of the controlled nMOS transistor M1a is grounded, and the drain of the controlled nMOS transistor M1a is connected to the source and transmission gate of the precharged nMOS transistor M2b in the precharging circuit. The gate of the controlled nMOS transistor M1b is connected to the discharge voltage, the source of the controlled nMOS transistor M1b is grounded, and the drain of the controlled nMOS transistor M1b is connected to the bit line and the other end of the transmission gate. Preferably, the control signal of the nMOS transistor M1a in the discharge circuit is valid when the chip select read signal is invalid, and is valid when each read operation is completed; the control signal of the nMOS transistor M1b in the discharge circuit is valid when each read operation is completed. By using the discharge circuit, the residual charge on the bit line and the load end of the data readout circuit can be discharged, thereby reducing or even eliminating data crosstalk, and improving the data readout speed and the reliability of data readout.

When applying the data readout circuit of the phase-change memory with switchable read voltage/read current shown in Figure 3,

When the read mode selection signal RMod is high level "1", the data readout circuit works in the read voltage mode, the pMOS transistors M9a and M9b as the read mode selection switch tubes are disconnected, and the transmission gates TG1 and TG3 are turned on (transmission gate TG0 and TG2 are turned off), the adjusted bias current I _bias is poured into the bit line BL through the pMOS transistors M4 and M5a, and the foil bit nMOS transistor M2a in the foil bit circuit acts as a pre-amplifier to obtain a pre-amplification voltage V1, thus, The pre-amplified voltage V1 and the reference voltage Vref are transmitted to the input terminal of the voltage comparator CMP through the transmission gates TG1 and TG3 respectively, and the voltage comparator CMP compares the pre-amplified voltage V1 with the reference voltage Vref and outputs the readout result; the read mode selection signal When RMod is low level "0", the data readout circuit works in the read current mode, the pMOS transistors M9a and M9b as the read mode selection switch tubes are closed, and the transmission gates TG0 and TG2 are turned on (the transmission gates TG1 and TG3 are turned off ), the foil bit nMOS transistor M2a in the foil bit circuit acts as a clamp to generate a clamping current I _Cell , due to the existence of the pMOS tube M5b, the difference between the foil bit current I _Cell and the adjusted bias current I _C ( I _C =I _Cell -mgI _bias ) will flow through the pMOS transistor M5b, and then input the reference current I _ref into the current-voltage conversion circuit, which will calculate the difference between I _C and the reference current I _ref and then convert it into two complementary voltages C1, C2, the two voltages C1, C2 are respectively transmitted to the input terminal of the voltage comparator CMP through the transmission gates TG0, TG2, and the voltage comparator CMP compares the voltages C1, C2 and outputs a readout result.

In summary, the data readout circuit of the phase-change memory with switchable read voltage/current mode of the present invention can effectively compare the working performance of the read current and read voltage modes under different load conditions through mode switching, and for different Select the matching read mode according to the load condition to achieve the best effect of read rate, high and low resistance state resolution, and power consumption.

The above-mentioned embodiments only illustrate the principles and functions of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can make modifications to the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be listed in the claims.

Claims (13)

1. data reading circuit of reading the switchable phase transition storage of voltage/read current, said phase transition storage comprises one or more phase-change memory cells, each phase-change memory cell links to each other with control circuit with word line through bit line; It is characterized in that said data are read packet and drawn together:

Paper tinsel position voltage generation circuit is used to produce paper tinsel position voltage;

Pre-charge circuit, the bit line to said storage unit under the control of said paper tinsel position voltage carries out rapid charge;

Paper tinsel position circuit by the control of paper tinsel position voltage, has and carries out the paper tinsel position in pairs of bit line under the read current pattern and produce first mode of operation of paper tinsel digit current and reading that pairs of bit line signal under the voltage mode amplifies in advance and second mode of operation that produces preparatory amplifying voltage;

The reading mode commutation circuit; Select to select the read current pattern under the signal controlling or read voltage mode at reading mode; Control paper tinsel position circuit is carried out first mode of operation or corresponding second mode of operation of reading voltage mode of corresponding read current pattern, and selection needs two-way voltage relatively;

Current-to-voltage converting circuit is selected in said reading mode commutation circuit under the situation of read current pattern paper tinsel digit current that produces and the reference current under the read current pattern to be carried out computing, and then is converted complementary two-way voltage into;

Compare amplifying circuit, the two-way voltage that said reading mode commutation circuit is selected compares, and the result is read in output; Under the read current pattern, the two-way voltage that said reading mode commutation circuit is selected comprises that said current-to-voltage converting circuit conversion back forms complementary two-way voltage; Reading under the voltage mode, the two-way voltage that said reading mode commutation circuit is selected comprises the preparatory amplifying voltage that paper tinsel position circuit pairs of bit line signal amplifies in advance and reads the reference voltage under the voltage mode.

2. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Also be included in the bit line transmission gate that is connected in series on the said bit line, make said pre-charge circuit and said paper tinsel digit current produce circuit and be connected with said bit line via said bit line transmission gate.

3. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Also comprise discharge circuit, be used for comparing on the said bit line of releasing after amplifieroperation is compared in the amplifying circuit completion and the remaining electric charge of said data reading circuit load end said.

4. the data reading circuit of phase transition storage as claimed in claim 3; It is characterized in that said discharge circuit comprises that controlled nMOS pipe that is connected between said pre-charge circuit and the ground wire and controlled the 2nd nMOS that is connected between said bit line and the ground wire manage.

5. like the data reading circuit of claim 1 or 3 described phase transition storages, it is characterized in that, also comprise the bit line bias current circuit, be used for bias current being provided to bit line.

6. the data reading circuit of phase transition storage as claimed in claim 5; It is characterized in that; Said bit line bias current circuit comprises the current-mirror structure that is formed by two pMOS pipes; Wherein, the drain electrode of pMOS pipe is connected with bias current sources, and the drain electrode of the 2nd pMOS pipe is connected with said paper tinsel position circuit.

7. the data reading circuit of phase transition storage as claimed in claim 6 is characterized in that, said bit line bias current circuit is in respectively that its bias current sources has different electric currents when reading voltage mode with the read current pattern.

8. the data reading circuit of phase transition storage as claimed in claim 1; It is characterized in that; Said paper tinsel position voltage generation circuit comprises current source, connects into the nMOS pipe of diode and the 2nd nMOS pipe that is connected in series with nMOS pipe, and the drain electrode of nMOS pipe is connected with the current output terminal of said current source, and the grid of nMOS pipe is connected with the grid of the 2nd nMOS pipe; The source electrode of the one nMOS pipe is connected with the drain electrode of the 2nd nMOS pipe, the source ground of the 2nd nMOS pipe.

9. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, the precharge paper tinsel position nMOS pipe that said pre-charge circuit comprises the precharge switch pipe and connects with said precharge switch pipe.

10. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, said paper tinsel position circuit comprises paper tinsel position nMOS pipe.

11. the data reading circuit of phase transition storage as claimed in claim 1 is characterized in that, said reading mode commutation circuit comprises: the current-to-voltage converting circuit CS; Amplifying circuit input signal SS relatively comprises being used for connecting respectively first voltage and the comparison amplifier positive input terminal that are produced by current-to-voltage converting circuit under the read current pattern, reading under preparatory amplifying voltage and comparison amplifier positive input terminal under the voltage mode, the read current pattern by second voltage and the comparison amplifier negative input end of current-to-voltage converting circuit generation, reading four transmission gates of reference voltage and comparison amplifier negative input end under the voltage mode; And be used for reading mode selection signal is carried out anti-phase and obtains the phase inverter that reading mode is selected the signal designature.

12. the data reading circuit of phase transition storage as claimed in claim 11; It is characterized in that; Reading mode is selected signal and is selected the signal designature to be carried in the control end and the current-to-voltage converting circuit CS control end of four transmission gates respectively through the reading mode of phase inverter: when selecting signal for " 1 "; The current-to-voltage converting circuit CS cuts out, and is connected the transmission gate of preparatory amplifying voltage and comparison amplifier positive input terminal and is connected the transmission gate conducting of reading voltage mode reference voltage and comparison amplifier negative input end; Otherwise; When selecting signal to be " 0 "; The current-to-voltage converting circuit CS is opened, and is connected under the read current pattern transmission gate of first voltage that produced by current-to-voltage converting circuit and comparison amplifier positive input terminal and is connected under the read current pattern by second voltage of current-to-voltage converting circuit generation and the transmission gate conducting of comparison amplifier negative input end.

13. the data reading circuit like claim 1,11 or 12 described phase transition storages is characterized in that, said relatively amplifying circuit comprises voltage comparator.

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