CN102810332A - Non-volatile memory device and method controlling dummy word line voltage according to location of selected word line - Google Patents

Abstract

The nonvolatile memory device includes an access circuit that selects a word line during operation, the access circuit selects a word line during operation, applies a selected word line voltage to a selected word line, applies a non-selected word line voltage to a word line unselected word lines and apply the dummy word line voltage to the dummy word lines. When the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage; when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the same as the first dummy word line voltage A second dummy word line voltage with a different voltage.

Description

Nonvolatile memory and method of controlling dummy word line voltage according to selected word line

This application claims priority from Korean Patent Application No. 10-2011-0054190 filed with the Korean Intellectual Property Office on Jun. 3, 2011, the subject matter of which is hereby incorporated by reference.

technical field

The inventive concept relates to a nonvolatile memory device, a nonvolatile memory cell array, a system including the nonvolatile memory device, and a method of operating the same. More specifically, the inventive concepts relate to nonvolatile memories and nonvolatile memory cell arrays including one or more dummy word lines, methods of operating nonvolatile memory cell arrays, and nonvolatile memory cell arrays including such A system of volatile memory devices.

Background technique

Non-volatile memory has become a mainstay component in digital systems and consumer electronics. The term "non-volatile memory" includes a broad sense of data storage devices capable of retaining stored data without power being applied. There are different kinds of non-volatile memory. One type is Electrically Erasable Programmable Read Only Memory (EEPROM). So-called "flash memory" is a special type of EEPROM and has become a particularly important form of non-volatile memory. Flash memories of the same period include NOR flash memory and NAND flash memory distinguished by the corresponding arrangement of access logic.

NAND flash memory can be configured to provide an array of non-volatile memory cells with very high integration density. Among other features related to NAND flash memory, this high integration density can be achieved by arranging NAND flash memory cells in a "string structure". A NAND string is essentially a number of NAND flash memory cells connected in series. Typically, a NAND flash memory cell string is disposed between a string selection transistor connected to a string selection line and a ground selection transistor connected to a ground selection line.

NAND flash memory shares many of the performance and implementation advantages of various nonvolatile and volatile memories. However, NAND flash memory is not without its own design considerations. For example, during certain program-inhibit functions, due to the difference between the high voltage on the boosted channel and the low voltage on the ground select line or the gate of the string select line, the Gate-Induced Drain Leakage (GIDL) is prone to occur in memory cells. GIDL current generally increases as the voltage difference between the channel of the memory cell and the gate of the ground select line or the string select line increases. GIDL currents increase the likelihood of hot carrier injection (HCI) disturbances in memory cells adjacent to string and ground select lines. Such disturbances result in reduced read margins and can degrade the overall operating characteristics of the nonvolatile memory device.

Contents of the invention

Certain embodiments of the inventive concept provide nonvolatile memory devices including flash memory devices, 2D and 3D memory cell arrays including 2D and 3D flash memory cell arrays, methods for controlling nonvolatile memory devices and memory cell arrays Related methods of operation and systems including non-volatile memory devices. Embodiments flexibly adjust control voltages applied to 2D and 3D memory cell arrays including one or more dummy word lines. A specific arrangement relationship (for example, an arrangement relationship of dummy word lines within a plurality of word lines, or an arrangement relationship between a dummy word line and a selected word line within a plurality of word lines) may be used to determine a specific control voltage (for example, Read voltages, program voltages, erase voltages, dummy word line voltages, main word line voltages, bit line voltages) are applied to characteristics (eg, levels, waveforms, timing) of the memory cell array. As a result, disturbances induced in the constructed memory cells can be significantly reduced. As a result, disturbances introduced in the constructed memory cells can be significantly reduced. Therefore, a decrease in read margin due to disturbance can be suppressed, and furthermore, operating characteristics of the nonvolatile memory device can be improved.

One embodiment relates to a non-volatile memory device comprising: an array of non-volatile memory cells arranged in association with word lines including dummy word lines; Select the word line in the line, apply the voltage of the selected word line to the selected word line, apply the voltage of the unselected word line to the unselected word line among the word lines, and apply the voltage of the dummy word line to the dummy word line , wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage A second dummy word line voltage different from the dummy word line voltage.

Another embodiment relates to a nonvolatile memory device comprising: a vertical memory cell array including a plurality of nonvolatile memory cells and word lines, the plurality of nonvolatile memory cells arranged along a first direction In the stacked plurality of memory cell array layers, the word lines extend in a second direction intersecting the plurality of memory cell array layers and include dummy word lines; selecting a word line, applying a selected word line voltage to a selected word line, applying a non-selected word line voltage to an unselected word line among the word lines, and applying a dummy word line voltage to a dummy word line, Wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the second dummy word line voltage. line voltage.

Another embodiment relates to a nonvolatile memory device comprising: a vertical memory cell array including a plurality of nonvolatile memory cells and word lines, the plurality of nonvolatile memory cells arranged along a first direction In the stacked plurality of memory cell array layers, the word lines extend along a second direction intersecting with the plurality of memory cell array layers and include a plurality of dummy word lines; the access circuit, during operation, responds to a received address at Selecting a word line among the word lines, applying the voltage of the selected word line to the selected word line, applying the voltage of the unselected word line to the unselected word lines among the word lines, and respectively applying the voltage of the multiple dummy word lines A dummy word line voltage is applied to each dummy word line in the plurality of dummy word lines, wherein the plurality of dummy word line voltages include: when the selected word line is not adjacent to the corresponding dummy word line , applying the first dummy word line voltage to the corresponding dummy word line, and applying the second dummy word line voltage to the corresponding dummy word line when the selected word line is adjacent to the corresponding dummy word line.

Another embodiment relates to a nonvolatile memory device including: a vertical memory cell array including a plurality of nonvolatile memory cells and a plurality of word lines, the plurality of nonvolatile memory cells arranged along a first In a plurality of memory cell array layers stacked in one direction, the plurality of word lines extend along a second direction intersecting the plurality of memory cell array layers and include a plurality of dummy word lines; an access circuit, during operation, responding to The received address selects a word line among the plurality of word lines, applies a voltage of the selected word line to the selected word line, and applies a voltage of an unselected word line to an unselected word among the plurality of word lines. line, and respectively apply one dummy word line voltage among the multiple dummy word line voltages to each of the multiple dummy word line voltages, wherein the multiple dummy word line voltages include: a first dummy word line voltage word line voltage, when the selected word line is not adjacent to the corresponding dummy word line, the first dummy word line voltage is applied to the corresponding dummy word line; the second dummy word line voltage, when the selected word line is adjacent to the corresponding dummy word line When the dummy word lines are adjacent, the second dummy word line voltage is applied to the corresponding dummy word lines. At least one of the waveform of the voltage of the first dummy word line is different from that of the voltage of the second dummy word line, the level of the voltage of the first dummy word line is different from the level of the voltage of the second dummy word line, and the plurality of dummy words The lines include at least one end dummy word line and at least one middle dummy word line. Each of the plurality of nonvolatile memory cells is a NAND flash memory cell, and the plurality of nonvolatile memory cells are also arranged in a plurality of NAND memory cell strings, the plurality of NAND flash memory cells The high-speed memory cell strings respectively extend along a first direction through the stacked plurality of memory cell layers, each of the plurality of NAND memory cell strings includes: a string selection transistor coupled to a string selection line; a ground selection transistor, Bonded to the ground select line; the first group of NAND flash memory cells, connected in series between the string select transistor and the dummy word line in the middle and respectively bonded to the first group of word lines; the second group of NAND flash memory cells, in the middle The dummy word lines are connected in series with the ground selection lines and respectively combined with the second group of word lines.

Another embodiment relates to a system that includes a memory controller configured to control operation of a non-volatile memory device, wherein the non-volatile memory device includes an array of non-volatile memory cells, and a The word lines of the dummy word lines are arranged in association; the access circuit, during operation, selects a word line among a plurality of word lines in response to an address received, applies a selected word line voltage to a selected word line, and unselects a word line A line voltage is applied to an unselected word line among the plurality of word lines, and a dummy word line voltage is applied to the dummy word line, wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is A first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is a second dummy word line voltage different from the first dummy word line voltage.

Another embodiment relates to a memory card system comprising: an interface operatively connecting the memory card system with a host to receive input data from the host and transmit output data to the host; a memory controller controlled by configured to receive input data from the interface, store the input data in a non-volatile memory device, receive output data from the non-volatile memory device, and transmit the output data to a host, wherein the non-volatile memory device includes : An array of nonvolatile memory cells arranged in association with word lines including dummy word lines and an access circuit, the access circuit responding to a received address during a plurality of word lines during operation Select the word line in the line, apply the voltage of the selected word line to the selected word line, apply the voltage of the unselected word line to the unselected word line among the plurality of word lines, and apply the voltage of the dummy word line to the dummy word line word line, wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage The second dummy word line voltage is different from the first dummy word line voltage.

Another embodiment relates to a solid-state drive (SSD) comprising: a memory controller configured to control operations of a plurality of non-volatile memory devices via a plurality of channels, wherein the plurality of non-volatile memory devices Each of the volatile memory devices includes: an array of nonvolatile memory cells arranged in association with a plurality of word lines including dummy word lines; access circuitry responsive to a received address during operation on the plurality of word lines Selecting the word line, applying the voltage of the selected word line to the selected word line, applying the voltage of the unselected word line to the unselected word line among the plurality of word lines, and applying the voltage of the dummy word line to the dummy word line line, wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the same as The second dummy word line voltage is different from the first dummy word line voltage.

Another embodiment relates to a Redundant Array of Independent Disks (RAID) system including a RAID controller connected to a plurality of memory systems via respective channels, wherein each of the plurality of memory systems includes A memory controller configured to control operation of a plurality of nonvolatile memory devices, wherein each of the plurality of nonvolatile memory devices includes: an array of nonvolatile memory cells, and a A plurality of word lines are arranged in association; an access circuit selects a word line among the plurality of word lines in response to an address received during operation, applies a voltage of the selected word line to a selected word line, and applies a voltage of an unselected word line applied to an unselected word line among the plurality of word lines, and a dummy word line voltage is applied to the dummy word line, wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is a second dummy word line voltage different from the first dummy word line voltage.

Another embodiment relates to a method of operating a non-volatile memory device, the method comprising: receiving an address associated with an operation to be performed by the non-volatile memory device, responsive to the address, in the non-volatile memory device Selecting a word line among a plurality of word lines of the memory device, applying a voltage of the selected word line to the selected word line, applying a voltage of an unselected word line to an unselected word line among the plurality of word lines, and applying a dummy The word line voltage is applied to a dummy word line among the plurality of word lines, wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line When the dummy word lines are adjacent, the dummy word line voltage is a second dummy word line voltage different from the first dummy word line voltage.

Another embodiment relates to a method of operating a memory system including a memory controller and a nonvolatile memory device including word lines and dummy word lines, the method comprising: The address and command of the memory controller are transmitted to the nonvolatile memory device, wherein, according to the address, a word line among the plurality of word lines is selected, whether the selected word line is adjacent to a dummy word line is determined, and the selected word line is determined When the line is adjacent to the dummy word line, a first dummy word line voltage is applied to the dummy word line, otherwise a second dummy word line voltage different from the first dummy word line voltage is applied to the dummy word line.

Another embodiment is directed to a nonvolatile memory device comprising: an array of nonvolatile memory cells arranged in association with a plurality of wordlines including dummy wordlines; access circuitry during operation in response to received The address selects a word line among the plurality of word lines, applies a voltage of the selected word line to the selected word line, and applies a voltage of an unselected word line to an unselected word line among the plurality of word lines, wherein the access circuit includes dummy word line control logic for applying a dummy word line voltage to the dummy word line during operation, wherein the dummy word line voltage is the first dummy word line when the selected word line is not adjacent to the dummy word line line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is a second dummy word line voltage different from the first dummy word line voltage.

Description of drawings

The above and other features and advantages of the inventive concept will become more apparent when considering certain exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

1 is a block diagram of a nonvolatile memory according to an embodiment of the inventive concept;

FIG. 2A further illustrates one possible horizontal array of memory cells for the non-volatile memory of FIG. 1;

FIG. 2B further illustrates one possible vertical array of memory cells for the non-volatile memory of FIG. 1;

3A is a block diagram of a dummy word line control logic and a dummy word line voltage generator according to an embodiment of the inventive concept;

3B is a block diagram of a dummy word line control logic and a dummy word line voltage generator according to another embodiment of the inventive concept;

3C is a block diagram of a dummy word line control logic and a dummy word line voltage generator according to yet another embodiment of the inventive concept;

4 is a flowchart outlining one possible method of operating the non-volatile memory of FIG. 1;

FIG. 5 is a diagram illustrating provision and definition of dummy word lines according to a typical programming operation;

6 and 7 are diagrams explaining the regulation and definition of dummy word line voltages according to certain embodiments of the inventive concept;

8 (including FIG. 8A to FIG. 8D ) and FIG. 9 (including FIG. 9A to FIG. 9D ) are diagrams for further explaining the regulation and definition of dummy word line voltages according to typical read operations;

FIG. 10 (comprising FIG. 10A to FIG. 10D ) is a diagram further explaining regulation and definition of a dummy word line voltage according to an embodiment of the inventive concept;

FIG. 11 is a graph showing the overshoot that occurs in association with typical bias conditions for dummy word lines;

12 is a graph illustrating that a waveform of a voltage of a dummy word line changes according to a selected word line, according to an embodiment of the inventive concept;

13A and 13B are diagrams explaining a method of changing a waveform and a level of a voltage of a dummy word line according to a selected word line according to some embodiments of the inventive concepts;

14 to 17 are diagrams of an example of controlling a voltage of a dummy word line according to a position of a selected word line in a three-dimensional NAND memory device, according to an embodiment of the inventive concept;

18A and 18B are diagrams illustrating different examples of controlling a voltage of a dummy word line according to a position of a selected word line, according to an embodiment of the inventive concept;

19 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1, according to an embodiment of the inventive concept;

20 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1 according to another embodiment of the inventive concepts;

21 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1 according to still another embodiment of the inventive concepts;

22 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1 according to still another embodiment of the inventive concepts;

23 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1 according to still another embodiment of the inventive concept;

24 is a block diagram of a memory system including the nonvolatile memory device of FIG. 1 according to still another embodiment of the inventive concept;

FIG. 25 is a block diagram of a data processor including the memory system of FIG. 24 .

Detailed ways

Embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings. However, the inventive concept may be embodied in many different forms and should not be construed as limited to only the set forth embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the written description and drawings, the same serial numbers and reference numerals are used to designate the same or similar elements throughout.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements or layers may be present. In contrast, when an element is described as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and may be abbreviated as "/".

It will be understood that, although the terms first, second etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the present disclosure.

The terms used herein are intended to describe particular embodiments only and are not intended to limit the inventive concept. As used herein, singular forms are intended to include plural forms unless the context clearly dictates otherwise. It will also be understood that when the terms "comprising" and/or "comprising" are used in this specification, it indicates that the features, regions, integers, steps, operations, elements and/or components exist, but does not exclude the existence or additional One or more other features, regions, integers, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be construed to have the same meaning as they have in the context of the relevant art and/or application, rather than ideally or Explain their meaning too formally.

Recognizing that the increasing impact of the performance of a nonvolatile memory device on the performance of a host device that includes the nonvolatile memory device requires that the nonvolatile memory device retain or increase its performance under increasingly challenging operating conditions Read margin. Such operating conditions may often be characterized by one or more requirements including reduced power consumption, higher operating frequency, expanded data bandwidth, and greater error detection and correction capabilities. In addition, emerging memory systems require increased data storage densities and capacities that conventional two-dimensional (2D) or horizontal memory arrays are insufficient to provide. Accordingly, many emerging memory systems include three-dimensional (3D) or vertical memory arrays. A vertical memory array is any configuration in which at least one semiconductor layer including a plurality of memory cells is stacked vertically on top of another semiconductor layer including a plurality of memory cells. In the embodiments described below, specific horizontal (2D) and vertical (3D) memory array structures will be described. Those skilled in the art will recognize that features described herein as memory arrays configured horizontally can be extended to similarly arranged vertical memory arrays.

FIG. 1 is a block diagram of relevant portions of a nonvolatile memory device 10 according to certain embodiments of the inventive concept. FIG. 2A further shows non-volatile memory cell array 20 in a relevant portion as a horizontal memory cell array, while FIG. 2B further shows memory cell array 20' as a vertical memory cell array. Either the nonvolatile memory cell array 20 or the nonvolatile memory cell array 20' may be included in the nonvolatile memory device 10 of FIG. 1 .

It should be noted that the illustrated embodiments assume the use of NAND flash memory cells in the constructed memory cell array. However, those skilled in the art will appreciate that the scope of the inventive concept is not limited to a memory cell array including only NAND type flash memory cells.

Referring to FIGS. 1 and 2A , a nonvolatile memory device 10 includes a memory cell array 20 and an access circuit 22 . Assuming that the shown embodiment d NAND flash memory operates, the program operation and the read operation in the nonvolatile memory 10 are performed on a page-by-page basis (that is, in page units), while block-by-block The erase operation is performed within the nonvolatile memory device 10 on a block basis (ie, in units of blocks), where each block includes a plurality of pages.

As shown in FIG. 2A, the memory cell array 20 includes a plurality of NAND memory cell strings 20-1, 20-2, . . . , 20-m, where "m" is a natural number. Each of the NAND memory cell strings 20-1 to 20-m includes a plurality of nonvolatile memory cells 21 and dummy cells 25 connected in series. The NAND memory cell strings 20-1 to 20-m are mainly arranged in a single "horizontal" plane defined by two dimensions (X and Y).

The NAND memory cell string 20-1 includes string selection transistors ST1 (or first selection transistors) connected in series to the bit line BL1 and ground selection transistors ST2 (or second selection transistors) connected to the common source line CSL. A plurality of nonvolatile memory cells 21 and dummy cells 25 . A gate of the first selection transistor ST1 is connected to a string selection line SSL. The gates of the plurality of nonvolatile memory cells 21 are connected to the plurality of word lines WL0 to WL63, respectively. The second selection transistor ST2 is connected to the ground selection line GSL. Gates of the respective dummy cells 25 are connected to dummy word lines DWL0 to DWL1, respectively.

In the embodiment shown in FIG. 2A, the NAND memory cell strings 20-1 to 20-m have substantially the same structure, although 64 bit word lines WL0 to WL63 and Two dummy word lines DWL0 and DWL1 , but other embodiments of the inventive concept are not limited to this specific number and arrangement of word lines and dummy word lines. For example, the dummy word lines DWL0 and DWL1 shown in FIGS. 1, 2A, and 2B are disposed at opposite ends of a group of word lines WL0 to WL63 (ie, directly adjacent to the ground selection line GSL and the string selection line SSL, respectively). ). However, other embodiments of the inventive concept may include dummy word lines and multiple sets of word lines that are not disposed in association with a selection line.

Each nonvolatile memory cell 21 included in each of the NAND memory cell strings 20-1 to 20-m may utilize a multi-level flash memory cell (MLC) and/or a single-level flash memory cell. memory cell (SLC).

As shown in FIG. 2B, NAND memory cell strings 20'-1, 20'-2, ..., 20'-k (where "k" is a natural number) can be arranged in three (X, Y and Z) dimensions defined in different multiple planes. That is, a vertical memory array may be constructed by arranging multiple "horizontal" memory arrays (eg, NAND memory cell strings 20'-1 through 20'-k) in a "vertical" stack. In this context, those skilled in the art will recognize that the terms "vertical" and "horizontal" define relative and arbitrary geometric relationships. Vertical memory arrays can be realized using many different fabrication and assembly techniques. For example, the plurality of material layers 21-1 to 21-k respectively implementing the horizontal NAND memory cell strings 20'-1 to 20'-k may be implemented as a wafer stack, a chip stack, or a cell stack. Material layers 21-1 to 21-k may utilize one or more elements (and associated manufacturing techniques) such as through-silicon vias (TSVs), conductive bumps, wire bonds, distribution wiring, etc. "Stack connected" to another layer.

The NAND memory cell strings 20'-1 to 20'-k of FIG. 2B may be configured to share and operate in response to an access circuit similar to the access circuit 22 of FIG. 1A. This type of access circuit is capable of selectively accessing memory cells in a vertical memory array using various operations such as program, read and erase operations.

Similar to the horizontal memory cell array of FIG. 2A, the first NAND memory cell string 20'-1 of the first layer 21-1 of FIG. 2B includes a plurality of serially connected between the first selection transistor ST11 and the second selection transistor ST21 Nonvolatile memory cells (eg, NAND memory cells) 21 and dummy cells 25 . The second NAND memory cell string 20'-2 of the second layer 21-2 includes a plurality of nonvolatile memory cells 21 and dummy cells 25 connected in series between the first selection transistor ST12 and the second selection transistor ST22. The kth NAND memory cell string 20'-k of the kth layer 21-k includes a plurality of nonvolatile memory cells 21 and dummy cells 25 connected in series between the first selection transistor ST1k and the second selection transistor ST2K.

As shown in FIG. 2B, NAND memory cell strings 20'-1 to 20'-k may share (ie, be commonly connected to) a plurality of word lines WL0 to WL63 (or a subset thereof), a plurality of bit lines BL1 to BLm At least one of them and one or more control signal lines (for example, common source line CSL). In other words, the NAND memory cell strings at corresponding positions in the respective material layers 21-1 to 21-k may be connected to a plurality of page buffers included in the page buffer and sense amplifier (S/A) block 70 One of 71-1 to 71-m corresponds to one page buffer.

Referring to FIG. 1 , the access circuit 22 is configured to selectively access one or more memory cells arranged in the memory cell array 20 using these conventionally understood operations (program operation, read operation, and erase operation). Such operations may be performed in response to a command (or set of commands) and associated addresses provided externally from a source, such as a memory controller (not shown). As conventionally understood, program operations performed by access circuitry 22 may include program verify operations, and erase operations may include erase verify operations.

Referring now to FIGS. 1 and 2A , assume that the access circuit 22 receives an externally provided programming command, an associated address (i.e., a set of addresses or address ranges) and “write data” to be programmed into the memory cell array 20 (e.g., write data on one page). In response to a program command, access circuit 22 generates the control signals required to program (or store) given write data into the memory cell array. Assuming a simple example where write data for a particular page is defined to be associated with a particular word line (e.g., WL31), a corresponding address is applied to read from multiple strings of NAND memory cells (e.g., 20−1). The particular word line is "selected" among the word lines WL0 to WL63. Thus, in response to the program command and associated address, the one particular word line becomes the "selected word line" at least during the constituted program operation, while the other word lines remain "unselected word lines". Thus, a selected word line is a word line associated with one or more memory cells that received write data during a programming operation, and an unselected word line is a word line that is not associated with the memory cells that received write data.

Similar distinctions can be made between word lines during read operations. Thus, in response to a read operation and associated address, the one particular word line becomes the "selected word line" at least during the constituted read operation, while the other word lines remain "unselected word lines" . Thus, the selected word line is the word line associated with the memory cell or cells from which "read data" was obtained during the read operation, and the unselected word line is the word line associated with the "read data" from which the "read data" was obtained. The memory cells are not associated with the word line.

In addition to defining and generating other control signals (eg, voltage and/or current ), the access circuit 22 defines and generates specific control signals applied to the dummy word lines. More specifically, during the current operation, at least in part by the position of the selected word line of the plurality of word lines relative to the position of one or more dummy word lines of the plurality of word lines controlled by the inventive concept Embodiments design or operate the definition, generation and application of dummy word line signals (eg, voltages) made by access circuits.

In one example consistent with an embodiment of the inventive concept, when the selected word line during operation is "adjacent" to (ie, placed directly next to) a dummy word line among the arranged plurality of word lines line, with no other word lines in between), then the first dummy word line voltage applied to the dummy word line during the operation will be similar to when the selected word line is not adjacent to the dummy word line. The second dummy word line voltage applied to the dummy word line during operation is different. For example, during a read operation, a read voltage applied to a dummy word line will vary depending on whether a word line selected by the read operation is adjacent to a dummy word line in a memory block. Similarly, during a program operation, the voltage applied to the dummy word line will vary depending on whether the word line selected by the program operation is adjacent to the dummy word line in the memory block.

A method of controlling execution of operations on data stored (or to be stored) in an array of memory cells will be described in some additional detail with reference to the embodiments shown in FIGS. 1 and 2A. In FIG. 1, exemplary access circuitry 22 includes voltage supply circuitry 30, row drivers 40, control logic 50, common select line (CSL) drivers 60, page buffers and S/A circuitry 70, input/output (I/O ) circuit 80.

The voltage supply circuit 30 generates and supplies specific control voltages required for various operations to be performed through the row driver 40 . These control voltages include specific voltages that are applied row by row through the row driver 40 and vary in level and/or activation/deactivation timing according to operations. For example, the voltage supply circuit 30 may generate a program voltage during a program operation, an erase voltage during an erase operation, and a read voltage during a read operation. It should be noted that some embodiments of the inventive concept include a program operation of applying a program voltage generated according to an incremental step pulse program (ISPP) scheme. Other embodiments of the inventive concept may include erase voltages generated according to an incremental step pulse erase (ISPE) scheme.

The voltage supply circuit 30 shown in FIG. 1 includes a first dummy word line voltage generator 31 - 1 , a second dummy word line voltage generator 31 - 2 , a selection voltage generator 33 and a main word line voltage generator 35 . The first dummy word line voltage generator 31-1 and the second dummy word line voltage generator 31-2 respectively generate the first dummy word line voltage VDUM0 and the second dummy word line voltage VDUM1 and supply them to the first dummy word line respectively. line DWL0 and the second dummy word line DWL1. The selection voltage generator 33 generates voltages applied to the string selection line SSL and the ground selection line GSL. The main wordline voltage generator 35 generates respective wordline voltages VWL applied to the plurality of wordlines WL0 to WL63. In the foregoing, it should be noted that the various generators within the voltage supply circuit 30 may be implemented with one or more voltage generator circuits. Accordingly, the signal-specific descriptions of the generators given above are provided to illustrate functional or operational differences, rather than differences that must be associated with individual circuits. Indeed, many embodiments of the inventive concept will seek to provide the required control voltages with minimal hardware resources to reduce the resulting size of the constructed non-volatile memory device.

Control logic 50 controls the overall operation of access circuit 22 . In the embodiment shown in FIG. 1, control logic 50 may be used to control the operation of dummy word line voltage generators 31-1 and 31-2. For example, specific logic hardware (and/or associated software routines) may be used to control dummy word line voltage generators 31-1 and 31-2. However, this hardware, firmware, and/or software implemented specifically within control logic 50 will be described as dummy word line control logic 51 . Some examples of possible structures and functional operations of dummy word line control logic 51 are described below.

As shown in FIG. 2B, the page buffer and S/A circuit 70 may include a plurality of page buffers 71-1 to 71-m. The page buffers 71-1 to 71-m may be connected to a plurality of bit lines BL1 to BLm, respectively. Under the control of the control logic 50, each of the page buffers 71-1 to 71-m serves as a driver during a programming operation for programming write data into the memory cell array 20'; Under the control of 50, it functions as a sense amplifier (S/A) during a verify operation or a read operation for sensing and amplifying the bit line voltage level.

The I/O circuit 80 can be selectively configured to transfer externally supplied write data to the page buffer and S/A circuit 70, or to transfer the write data from the page buffer and S/A circuit 70 through a plurality of I/O pins or a data bus. The read data provided by the A circuit 70 is transmitted to an external circuit. I/O pins associated with I/O circuitry 80 may be used to receive address information (e.g., program address, read address, or erase address), command information (e.g., program command, read command, or erase command) and /or write data associated with a programming command. Various addresses may include column addresses and/or row addresses.

3A-3C are block diagrams further illustrating some possible implementation examples of dummy wordline control logic 50 and dummy wordline voltage generator 31 (VDUM generator) of FIG. 1 . FIG. 3A is a block diagram of dummy word line control logic 51 and dummy word line voltage generator 31 according to one embodiment of the inventive concept. Referring to FIG. 3A , the dummy word line control logic 51 includes a reference address storage unit 53 , a comparator 54 , a first code storage unit 55 - 1 and a second code storage unit 55 - 2 , and a selector 56 .

The reference address storage unit 53 stores a reference address RWL_ADDR. The first code storage unit 55-1 and the second code storage unit 55-2 store the previously received first code CODE1 and second code CODE2, respectively. The reference address RWL_ADDR and at least one of the first code CODE1 and the second code CODE2 may be implemented as a register. The register may be implemented using a static random access memory (SRAM) or an electronic fuse register, but embodiments of the inventive concept are not limited thereto.

The reference address RWL_ADDR and at least one of the first code CODE1 and the second code CODE2 may be stored as a hard-wired value (hard-wired value). For example, when the reference address RWL_ADDR is stored as a hardwired value of "101", the value of "1" can be achieved by connecting to the supply voltage, and the value of "0" can be achieved by connecting to ground. However, the reference address storage unit 53 and the first code storage unit 55-1 and the second code storage unit 55-2 may be implemented in other ways.

The reference address RWL_ADDR is an address that can be used to determine whether a selected word line is adjacent to a dummy word line. Therefore, multiple reference addresses can be used to respectively indicate corresponding dummy word lines.

The comparator 54 compares the selected address WL_ADDR with the reference address RWL_ADDR and outputs a comparison signal CS. The selected address WL_ADDR is an address corresponding to a word line selected during an operation (eg, a program or read operation), and may be provided from the outside or generated in response to an input address.

When the selected address WL_ADDR is less than or equal to the reference address RWL_ADDR, the comparator 54 may output the comparison signal CS at a first logic level (for example, "0"), and when the selected address WL_ADDR is greater than the reference address RWL_ADDR, the comparator 54 may output The comparison signal CS is output at a second logic level (for example, "1"). As an alternative, when the selected address WL_ADDR is greater than or equal to the reference address RWL_ADDR, the comparator 54 may output a comparison signal CS at a first logic level (for example, "0"), and when the selected address WL_ADDR is less than the reference address RWL_ADDR , the comparator 54 may output the comparison signal CS at a second logic level (for example, "1"). Alternatively, when the selected address WL_ADDR falls within a predetermined range from the reference address RWL_ADDR, the comparator 54 may output the comparison signal CS at a first logic level (for example, “0”), otherwise, the comparator 54 outputs the comparison signal CS with The second logic level (for example, "1") outputs the comparison signal CS.

In response to the comparison signal CS, the selector 56 selects and outputs one of the first code CODE1 and the second code CODE2 as the selection code S_CODE.

In the embodiment shown in FIG. 3A, the dummy word line voltage generator 31 generates the dummy word line voltage VDUM at a level corresponding to the selection code S_CODE. The dummy word line voltage generator 31 may be a voltage generator that generates voltages at different levels according to code values. Accordingly, the dummy word line voltage generator 31 may generate word line voltages at different levels according to the selection code S_CODE, but the inventive concept is not limited to the current embodiment. Alternatively, the dummy word line voltage generator 31 may generate word line voltages having different waveforms according to the selection code S_CODE.

3B is a block diagram of dummy word line control logic 51' and dummy word line voltage generator 31' according to another embodiment of the inventive concept. The dummy word line control logic 51 ′ includes a reference address storage unit 53 and a comparator 54 . The reference address storage unit 53 and the comparator 54 of FIG. 3B may perform the same functions as those described above in relation to the embodiment shown in FIG. 3A .

The dummy word line voltage generator 31' includes a first voltage level generator 31a, a second voltage level generator 31b, and a selector 31c. The first voltage level generator 31a and the second voltage level generator 31b generate a first voltage level VDL1 and a second voltage level VDL2, respectively. The selector 31c selects and outputs one of the first voltage level VDL1 and the second voltage level VDL2 as the dummy word line voltage VDUM in response to the comparison signal CS.

FIG. 3C is a block diagram of a dummy word line control logic 51′ and a dummy word line voltage generator 31″ according to another embodiment of the inventive concept. In order to avoid inappropriate redundant description, only the embodiment and the dummy word line of FIG. 3B will be described. The difference between the embodiments of Figure 3C.

The dummy word line voltage generator 31" includes a first waveform generator 32a and a second waveform generator 32b instead of the first voltage level generator 31a and the second voltage level generator 31b shown in FIG. 3B. In other words In other words, although the dummy word line voltage generator 31' shown in FIG. 3B selects and outputs one of different voltage levels as the dummy word line voltage VDUM in response to the comparison signal CS, the dummy word line voltage VDUM shown in FIG. The dummy word line voltage generator 31" selects and outputs one of different waveforms as the dummy word line voltage VDUM in response to the comparison signal CS.

FIG. 4 is an overview of one possible method for controlling the operation of the non-volatile memory device 10 shown in FIG. 1 . Referring to FIGS. 1 to 4 in its entirety, the nonvolatile memory device 10 receives a command CMD and a corresponding input address ADD provided from the outside as needed ( S10 ). Command CMD and address ADD may be received from a number of different kinds of sources including, but not limited to, a memory controller or host connected to non-volatile memory device 10 via one or more channels. The one or more channels may be hardwired or wirelessly implemented. Although not specifically identified in FIG. 4 , other data (eg, write data) may also be received as part of the command CMD provided to the non-volatile memory device 10 .

A word line address WL_ADDR may be selected (or derived) from an input address ADD, and then compared with the one or more reference addresses RWL_ADDR (S11). For example, as described above, the reference address RWL_ADDR may be stored in a hardwired (hardwired) register or data storage unit.

When the selected word line address WL_ADDR is less than or equal to the reference address RWL_ADDR, a first dummy word line voltage is generated ( S13 ), otherwise a second dummy word line voltage is generated ( S15 ). When the selected word line address WL_ADDR is less than or equal to the reference address RWL_ADDR, the selected word line (ie, the word line selected by the address WL_ADDR) is adjacent to the dummy word line.

Alternatively, when the selected word line address WL_ADDR is greater than or equal to the reference address RWL_ADDR, a first dummy word line voltage is generated ( S13 ), otherwise a second dummy word line voltage is generated ( S15 ). That is, when the selected word line address WL_ADDR is less than or equal to the first reference address RWL_ADDR or greater than or equal to the second reference address, the first dummy word line voltage can be generated ( S13 ), otherwise the second dummy word line voltage can be generated ( S15 ). Therefore, as described above, various methods of determining whether the selected word line address WL_ADDR indicates that the selected word line is adjacent to the dummy word line may be used to define and generate an appropriate dummy word line voltage.

The first dummy word line voltage and the second dummy word line voltage will be "different" from each other. The difference may be reflected in at least one of level, waveform, application timing and the like. In order to selectively generate different dummy word line voltages, different first codes and second codes may be stored, wherein one of the first code and the second code may be selected in response to a selection signal to generate a corresponding dummy word line Voltage. As described above, the selection signal may be generated by comparing the selected word line address WL_ADDR with the reference address RWL_ADDR.

Once the dummy word line voltage is properly defined, the dummy word line voltage is applied to the dummy word line during the operation indicated by the command CMD (S17).

Therefore, according to an embodiment of the inventive concept, at least one characteristic of the dummy word line voltage applied to the dummy word line during operation will be determined according to the relative arrangement of the dummy word line and the selected word line among the plurality of word lines (eg, level, waveform, timing, etc.). As a result, for memory cells adjacent to dummy word lines, the frequency (or likelihood) of memory cell disturbances that might otherwise arise is reduced, and the corresponding reduction in read margin due to such disturbances can be significantly suppressed. .

Using specific, hypothetical examples, a comparison of the examples shown in FIGS. 5 , 6 and 7 will further clarify aspects of the inventive concept. Figure 5 shows a portion of memory cell strings (i.e. memory cells connected to word line 61 (WL61), word line 62 (WL62), word line 63 (WL63) respectively) and a dummy memory cell connected to a dummy word line (DWL1) cells, the dummy memory cells may be dummy NAND flash memory cells. It is assumed that the memory cells in FIG. 5 are under the control of conventionally generated control signals during normal programming operations. During a program operation, it is further assumed that word line 63 (WL63) is a selected word line receiving a program voltage (Vpgm) and is adjacent to a dummy word line (DWL1). Consistent with conventional practice, the programming voltage (Vpgm) applied to selected word lines is a high voltage, while unselected word lines are program inhibited.

In the example of FIG. 5, it is assumed that the program inhibit voltage applied to the unselected word lines (WL61 and WL62, including the dummy word line (DWL1)) is 8.0V. However, due to the difference between the relatively high channel voltage appearing on the dummy word line (DWL1) and the relatively low gate voltage of the string selection line SSL, gate induced drain leakage (GIDL) is easily related to the program inhibit bit line The association appears. Those skilled in the art will understand that the previous example where the 64th word line (WL63) is adjacent to the second dummy word line (DWL1) (wherein the second dummy word line (DWL1) is connected to the string selection line (SSL) Adjacent) can be extended to a similar example (where the first word line (WL0) is adjacent to the first dummy word line (DWL0) which is adjacent to the ground select line (GSL) ) and all lines are similarly biased), see, for example, Figure 2A. In either example, the GIDL current generated during the program operation causes hot carrier injection (HCI), resulting in disturbance between the second dummy word line (DWL1) and the 64th word line (WL63), or between Interference occurs between the first dummy word line (DWL0) and the first word line (WL0).

In contrast to the example shown in FIG. 5 , the examples shown in FIGS. 6 and 7 consistent with embodiments of the inventive concept suppress GIDL current and maintain read margin. To achieve these results, among other desirable results, different dummy word line voltages are used in determining whether a selected word line is adjacent to a dummy word line during a programming operation. In the example shown in FIG. 6, the word line selected by the programming operation is again adjacent to the dummy word line, while in the example shown in FIG. 7, the selected word line is not adjacent to the dummy word line.

Referring to FIG. 6, when the selected word line (WL63) is adjacent to the second dummy word line (DWL1), the dummy word line voltage applied to the second dummy word line (DWL1) is controlled to be lower than that applied to the unselected word line. Word line voltage for word lines WL0 to WL62. More specifically, when the selected word line (WL63) is adjacent to the second dummy word line (DWL1) during the program operation, less than the pass voltage Vpass applied to the unselected word lines WL0 to WL62 A voltage (eg, 3.0V) of (eg, 8.0V) is applied to the second dummy word line ( DWL1 ) to reduce or eliminate the GIDL current, thereby reducing HCI.

Referring to FIG. 7, when the selected word line (here, WL61 instead of WL63) is not adjacent to the second dummy word line (DWL1), the dummy word line voltage applied to the second dummy word line (DWL1) may be the same as The word line voltages applied to the unselected word lines WL0 to WL60 , WL62 and WL62 are the same (eg, the same level). In other words, as the distance between the selected word line and the dummy word line increases, the detrimental effect of GIDL and the resulting HCI decreases. Accordingly, the voltage applied to the dummy word line can be increased to contribute to high channel boosting efficiency.

Accordingly, the lower voltage (for example, 3.0V in FIG. 6 ) applied to the second dummy word line (DWL1) when the selected word line is adjacent to the second dummy word line (DWL1) is smaller A normal program inhibit voltage (for example, 8V in FIG. 7 ) applied to the second dummy word line ( DWL1 ) when the selected word line is not adjacent to the second dummy word line ( DWL1 ). The preceding comparative example shows how a particular control voltage applied to a dummy word line can be defined and controlled based at least in part on the placement relationship between the selected word line and the dummy word line, thereby reducing or eliminating the GIDL current and the resulting HCI, and increase boost efficiency.

In this regard, it should be noted that embodiments of the inventive concept are not limited to only an arrangement relationship in which a selected word line is adjacent to a dummy word line. The "close" placement relationship between other selected word lines and the dummy word line can be used to change the characteristics of the control voltage applied to the dummy word line during operation. For example, a non-adjacent but close placement relationship (eg, less than two or less than one intermediate word lines between the selected word line and the dummy word line) can be used to control the definition of the dummy word line voltage.

8A-8D (all of FIG. 8 ) and FIGS. 9A-9D (all of FIG. 9 ) are diagrams further illustrating the specification and definition of dummy word line voltages during a typical read operation. Next, hypothetical arrangements of a portion of word lines under various bias conditions are shown in FIGS. 8 and 9 . FIG. 8 shows the case where conventional bias conditions are used for a read operation and the voltage applied to the dummy word line ( DWL1 ) does not vary in association with the relative arrangement of the selected word lines. (Compare FIG. 8A in which WL63 adjacent to dummy word line ( DWL1 ) is selected during a read operation to FIG. 8B in which WL61 not adjacent to dummy word line ( DWL1 ) is selected during read operation).

As shown in FIG. 8A , when the voltage applied to the dummy word line ( DWL1 ) is similar to the voltage applied to the unselected word lines (for example, about 7.0 V), the device having the erased state is connected to the dummy word line DWL1 . The threshold voltage distribution of the dummy memory cells of is shifted from the initial distribution (G1_D1) to the changed distribution (G2_D1) (as shown in FIG. 8C). This undesirable shift in the threshold voltage distribution is due to the fact that the dummy word line DWL1 has been disturbed as a result of applying a relatively high voltage (approximately 7.0V) during the read operation. That is, the threshold voltage distribution shift of the memory cells connected to the dummy word line ( DWL1 ) causes a coupling effect between the 64th word line ( WL63 ) and the adjacent dummy word line ( DWL1 ). As a result, the threshold voltage distribution of memory cells connected to the 64th word line (WL63) changes, thereby reducing the read margin of such cells, as shown in FIG. 8D.

According to FIG. 9, in order to improve the read margin of the memory cells connected to the 64th word line (WL63) adjacent to the dummy word line (DWL1), the dummy word line voltage applied to the dummy word line (DWL1) can be made is reduced to be less than the voltage applied to the unselected word lines but greater than the voltage applied to the selected word line regardless of the arrangement relationship between the selected word line ( WL63 or WL61 ) and the dummy word line ( DWL1 ). (Comparing FIG. 9A with FIG. 8A, it can be noticed that compared with FIG. 8C, the threshold voltage distribution G3_D1 to threshold voltage distribution G4_D1 of the dummy memory cells connected to the dummy word line DWL1 shown in FIG. 9C has a reduced interference; Comparing FIG. 9B with FIG. 8B, it can be noted that the threshold voltage distribution G3_63 to threshold voltage distribution G4_63 of the memory cells connected to word line WL63 shown in FIG. 9D have reduced interference compared to FIG. 8D).

These results are mainly due to the fact that the dummy word line voltage applied to the dummy word line ( DWL1 ) is smaller than the voltage applied to the unselected word lines. That is, when the voltage applied to the dummy word line ( DWL1 ) is smaller than the voltage applied to the unselected word lines during the read operation, the possibility of disturbance in the dummy word line is reduced, so that when connected to the dummy word line The shift in the threshold voltage distribution of the memory cells of the word line is reduced, as shown in Figure 9C.

However, due to the parasitic capacitance existing between the control gate of the dummy word line and the floating gate of the adjacent word line, when the level of the read voltage applied to the dummy word line decreases, the potential of the floating gate decrease. As a result, in order to turn on the transistors of the memory cells connected to the plurality of word lines WL0 and WL63 , it is necessary to increase the voltage applied to the plurality of word lines WL0 and WL63 . In other words, when reading the selected word line WL63 (FIG. 9A) adjacent to the second dummy word line DWL1, the voltage applied to the selected word line WL63 should be greater than the read voltage applied to the second dummy word line DWL1. Voltage. Therefore, when the read voltage applied to the dummy word line decreases, the threshold voltage distribution of memory cells having an erased state and connected to a word line adjacent to the dummy word line increases such that the erased state is different from the adjacent programmed state The read margin between is reduced.

FIGS. 10A through 10D (all of FIG. 10 ) are diagrams further illustrating certain aspects of the inventive concepts in the context of a read operation and in relation to the arrangement relationship between selected word lines and dummy word lines. Referring to FIG. 10A, when the word line WL63 is selected during a read operation and the selected word line WL63 is adjacent to the second dummy word line (DWL1), the read voltage of the second dummy word line (DWL1) increases, thereby substantially The increased disturbance effect on the threshold voltage distribution of memory cells having an erased state and connected to word line WL63 is eliminated, as shown in FIG. 10D. Referring to FIG. 10C, when the selected word line WL61 is not adjacent to the second dummy word line (DWL1), the read voltage of the second dummy word line (DWL1) can be reduced to be lower than that applied to the unselected word line. read voltage but greater than the read voltage applied to the selected word line. In this way, the possibility of read disturb is significantly reduced or eliminated, as shown in Figure 10D.

Therefore, in the conventional operation method, a high read voltage is always applied to the dummy word line during the read operation shown in FIG. 8 . Alternatively, in other conventional operating methods, a reduced read voltage may be applied to the dummy word lines regardless of the arrangement relationship of the selected word lines, as shown in FIG. 9 . However, embodiments of the inventive concept consider an arrangement relationship of selected word lines and dummy word lines in a nonvolatile memory cell array, as shown in FIG. 10 . Accordingly, in the example of FIG. 10, a high read voltage (for example, 7.0 V) needs to be applied to a specific nonvolatile memory cell as many times as in the case shown in FIG. 8. The number of times is about 1/64 (assuming the case based on 64 strings), so that the possibility of read disturb and the wear of the memory cells are significantly reduced in the embodiments of the inventive concept compared with the conventional method.

FIG. 11 is a graph showing voltage waveforms where supershooting occurs in a typical dummy word line. Referring to FIG. 11, the dummy word line DWL1 has a larger overshoot than the main word lines WL0 to WL62, possibly because of the load difference between the dummy word line DWL1 and the main word lines WL0 to WL62, or because of the performance of different drivers. driver differences. Therefore, when the selected word line WL63 is adjacent to the dummy word line DWL1 and the voltage level of the dummy word line DWL1 is high, overshooting may cause disturbance.

12 is a voltage waveform diagram further illustrating a method of effectively changing a waveform of a voltage appearing on a dummy word line in consideration of an arrangement relationship of selected word lines according to certain embodiments of the inventive concept. For example, when the word line WL63 adjacent to the dummy word line DWL1 is selected, the voltage applied to the dummy word line DWL1 may have a staircase waveform as shown in FIG. 12 . That is, the voltage applied to the dummy word line DWL1 may have a low level initially, and then after a predetermined time point, the voltage applied to the dummy word line DWL1 may have a higher level. Although not shown, when a word line not adjacent to the dummy word line DWL1 is selected, a voltage similar to that applied to an unselected word line may be applied to the dummy word line instead of a voltage having a staircase waveform. DWL1, the voltage applied to the dummy word line DWL1 is smaller than the voltage applied to the unselected word lines.

As described above, when the waveform of the voltage applied to the dummy word line DWL1 is changed according to the arrangement relationship of the selected word lines, it is possible to prevent overshooting that occurs when a high voltage is applied to the dummy word line DWL1.

13A and 13B are correlation diagrams illustrating a method of changing the level and/or waveform of a word line voltage applied to a dummy word line during a read operation according to an arrangement relationship of a selected word line according to a specific embodiment of the inventive concept. collection of waveform diagrams.

Referring to FIG. 13A, the voltage level applied to the dummy word line DWL when the selected word line is adjacent to the dummy word line is greater than the voltage level applied to the dummy word line DWL when the selected word line is not adjacent to the dummy word line. . In other words, only the voltage level applied to the dummy word line changes depending on whether the selected word line is adjacent to the dummy word line.

Referring to FIG. 13B, when the selected word line is adjacent to the dummy word line, the voltage applied to the dummy word line has a ladder waveform, and the level of the voltage applied to the dummy word line is greater than that of the selected word line and the dummy word line. adjacent to the level of the voltage applied to the selected word line. In other words, both the level and the waveform of the voltage applied to the dummy word line are changed according to whether the selected word line is adjacent to the dummy word line.

14 to 17 further illustrate a method of controlling a voltage applied to a dummy word line in consideration of an arrangement relationship of a selected word line in a NAND flash memory device having a vertical memory cell array according to an embodiment of the inventive concept. related diagrams. Figure 14 is a partial cross-sectional view of a vertical memory array and illustrates two (2) subsets (hereinafter, "vertical sub-stacks") of vertically stacked material layers, each subset comprising NAND flash memory cells array of . In the embodiment shown in FIG. 14, the first vertical sub-stack 20'-ss1 includes first to eighth word lines ( WL0-WL7), the second vertical sub-stack 20'-ss2 includes 9th to 16th wordlines located between the second dummy wordline (DWL1) and the third dummy wordline (DWL2). The combination of the first sub-stack and the second sub-stack is a vertical array of memory cells located between the lower ground select line (GSLK) and the upper ground select line (SSLK).

In the foregoing configuration, since the second dummy word line is disposed between adjacent word lines of the plurality of main word lines (MWL) in the vertical memory cell array, the second dummy word line can be referred to as a "middle dummy word line". word line", . On the contrary, since each of the first dummy word line and the third dummy word line is disposed at one end of the plurality of word lines, each of the first dummy word line and the third dummy word line may be The line is referred to as an "end dummy word line". It should be noted that the embodiment shown in FIG. 14 includes only a single middle word line ( DWL1 ) separating the first and second sub-stacks. However, a plurality of intermediate dummy word lines may be used to separate the first sub-stack from the second sub-stack, or may be incorporated into the vertical memory cell array for other purposes. Similarly, more than one end dummy word line can also be used at the upper or lower end of the vertical memory cell array.

Correspondingly, each string of NAND flash memory cells in the vertical NAND memory cell array of FIG. 14 includes three dummy word lines DWL0 , DWL1 and DWL2 .

15 , 16 and 17 illustrate certain exemplary bias conditions that may exist according to certain embodiments of the inventive concept in relation to the vertical memory cell array of FIG. 14 . Referring to FIG. 15, and assuming a program operation, when the selected word line WL7 is adjacent to the middle dummy word line DWL1, a second dummy word line voltage VDUM2 greater than the voltage (Vpass) applied to the unselected word lines is applied to The middle dummy word line DWL1. A first dummy word line voltage VDUM1 equal to Vpass may be applied to end dummy word lines DWL0 and DWL2 .

Referring to FIG. 16 and again assuming a program operation, when the selected word line WL12 is not adjacent to the middle dummy word line DWL1 (or any of the end dummy word lines DWL0 and DWL2), the first dummy word line voltage VDUM1 may be applied to all dummy word lines.

Referring to FIG. 17 and again assuming a programming operation, when the selected word line WL15 is adjacent to the end dummy word line DWL2, a second dummy word line voltage VDUM2 less than Vpass is applied to the end dummy word line DWL2, and the first dummy word line voltage VDUM2 is applied to the end dummy word line DWL2. VDUM1 may be applied to the other end dummy word line DWL0 and the middle dummy word line DWL1.

18A and 18B illustrate exemplary bias conditions that may exist according to certain embodiments of the inventive concept in relation to a vertical memory cell array different from that of FIG. 14 . 18A and 18B assume that the vertical memory cell array includes dual-ended dummy word lines (DWL0/DWL1 and DWL2/DWL3) that surround multiple main word lines without intervening dummy word lines (DWL0/DWL1). word line. Furthermore, it is assumed that there is an independent dummy wordline voltage generator for each dummy wordline.

Referring to FIG. 18A and assuming that a read operation is performed on a word line not adjacent to a dummy word line, the NAND flash memory device is capable of generating four (4) dummy word line voltages (VDUM0', VDUM1', VDUM2', VDUM3' ). It is worth noting that the first dummy word line voltage VDUM0' and the second dummy word line voltage VDUM1' may be graded relative to each other. That is, the first (or outer) dummy word line voltage VDUM0' may be slightly smaller than the second (or inner) dummy word line voltage VDUM1'. The third and fourth dummy word line voltages can be similarly defined.

In addition, the level of the read voltage (VREAD vs. VREAD') can be changed to be slightly raised with respect to the arrangement relationship of the selected word line and the word lines adjacent to the selected word line, regardless of the two groups of end points. What is the arrangement relationship of the dummy word lines?

The foregoing embodiments are selected examples of the inventive concept to flexibly adjust control voltages applied to (2D and 3D) memory cell arrays including one or more dummy word lines. A specific arrangement relationship (for example, the arrangement relationship of the dummy word line in multiple word lines, or the arrangement relationship between the dummy word line and the selected word line in the multiple word lines) can be used to determine a specific control voltage (for example, read Take the characteristics (eg, level, waveform, timing) of the voltage, program voltage, erase voltage, dummy word line voltage, main word line voltage, bit line voltage) applied to the memory cell. As a result, disturbances induced in the constructed memory cells can be significantly reduced. Therefore, reduction in read margin due to the disturbance can be suppressed. In addition, the operating characteristics of the nonvolatile memory device can be improved.

So far, the illustrated embodiments have described a nonvolatile memory device including a flash memory device, a nonvolatile memory unit including a horizontal memory cell array and a vertical memory cell array, and operations for the nonvolatile memory device. unit method. However, the scope of the inventive concept is not limited to nonvolatile memory cell arrays, memory devices, and related operating methods. Other embodiments of the inventive concept relate to systems including such nonvolatile memory devices including horizontal and vertical memory cell arrays and methods of operating the same.

For example, FIG. 19 is a block diagram of a memory system 100 including the nonvolatile memory device 10 of FIG. 1 , according to an embodiment of the inventive concept. Referring to FIGS. 1 to 19, the memory system 100 may be implemented as a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), or a radio communication system.

The memory system 100 includes a nonvolatile memory device 10 and a memory controller 150 that controls the operation of the nonvolatile memory device 10 . The memory controller 150 may control data access operations (eg, program operations, erase operations, and read operations) of the nonvolatile memory device 10 according to the control of the processor 110 .

Page data programmed in the nonvolatile memory device 10 may be displayed through the display 120 according to the control of the processor 110 and/or the memory controller 150 .

The radio transceiver 130 transmits or receives radio signals through the antenna ANT. The radio transceiver 130 may convert radio signals received through the antenna ANT into signals that may be processed by the processor 110 . Accordingly, the processor 110 may process a signal output from the radio transceiver 130 and transmit the processed signal to the memory controller 150 or the display 120 . The memory controller 150 may program the signals processed by the processor 110 to the nonvolatile memory device 10 . The radio transceiver 130 may also convert a signal output from the processor 110 into a radio signal and output the radio signal to an external device through the antenna ANT.

The input device 140 inputs a control signal for controlling the operation of the processor 110 or causes data to be processed by the processor 110 to be input to the memory system 100 . The input device 140 may be implemented through, for example, a touch pad or computer mouse, a keypad or a keyboard.

The processor 110 may control the operation of the display 120 to display data output from the memory controller 150 , data output from the radio transceiver 130 , or data output from the input device 140 . The memory controller 150 controlling the operation of the nonvolatile memory device 10 may be implemented as part of the processor 110 or may be implemented as a separate chip.

FIG. 20 is a block diagram of a memory system 200 including the nonvolatile memory device 10 of FIG. 1 according to another embodiment of the inventive concepts. The memory system 200 may be implemented as a PC, tablet PC, netbook, e-reader, PDA, Portable Multimedia Player (PMP), MP3 player, or MP4 player.

The memory system 200 includes a nonvolatile memory device 10 and a memory controller 240 that controls data processing operations of the nonvolatile memory device 10 . The processor 210 may display data stored in the nonvolatile memory device 10 through the display 230 according to data input through the input device 220 . The input device 220 may be implemented by a pointing device such as a touch pad or computer mouse, a keypad or a keyboard.

The processor 210 may control the overall operation of the memory system 200 and the operation of the memory controller 240 . The memory controller 240 that can control the nonvolatile memory device 10 may be implemented as part of the processor 210 or may be implemented as a separate chip.

FIG. 21 is a block diagram of a memory system 300 including the nonvolatile memory device 10 of FIG. 1 according to still another embodiment of the inventive concepts. Memory system 300 may be implemented as a memory card or a smart card. The memory system 300 includes the nonvolatile memory device 10 , a memory controller 310 and a card interface 320 .

The memory controller 310 may control data exchange between the nonvolatile memory device 10 and the card interface 320 . The card interface 320 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but the inventive concept is not limited to the current embodiment.

The card interface 320 may interface the host 330 with the memory controller 310 for data exchange according to the protocol of the host 330 . The card interface 320 may support Universal Serial Bus (USB) protocol and Inter-Chip (IC) USB protocol. Here, the card interface 320 may refer to hardware supporting a protocol used by the host 330, software installed in hardware, or a signal transmission mode.

When the memory system 300 is connected to a host 330 such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box, the host interface 350 of the host 330 can Control to perform data communication with the nonvolatile memory device 10 through the card interface 320 and the memory controller 310 .

FIG. 22 is a block diagram of a memory system 400 including the nonvolatile memory device 10 of FIG. 1 according to yet another embodiment of the inventive concepts. The memory system 400 may be implemented as an image processor such as a digital camera, a digital camera-equipped cellular phone, a digital camera-equipped smart phone, or a digital camera-equipped tablet PC.

The memory system 400 includes a nonvolatile memory device 10 and a memory controller 440 that controls data processing operations of the nonvolatile memory device 10 (eg, program operations, erase operations, and read operations). The image sensor 420 included in the memory system 400 converts an optical image into a digital signal and outputs the digital signal to the processor 410 or the memory controller 440 . The digital signal may be controlled by the processor 410 to be displayed by the display 430 or stored in the non-volatile memory device 10 by the memory controller 440 .

Data stored in the nonvolatile memory device 10 may be displayed through the display 430 according to the control of the processor 410 or the memory controller 440 . The memory controller 440, which may control the operation of the nonvolatile memory device 10, may be implemented as part of the processor 410 or as a separate chip.

FIG. 23 is a block diagram of a memory system 500 including the nonvolatile memory device of FIG. 1 according to still another embodiment of the inventive concepts. The memory system 500 includes a nonvolatile memory device 10 and a central processing unit (CPU) 510 that controls the operation of the nonvolatile memory device 10 .

Memory system 500 also includes a memory device 550 that may be used as operating memory for CPU 510. Memory device 550 may be implemented by non-volatile memory, such as read only memory (ROM), or volatile memory, such as static random access memory (SRAM). A host connected to the memory system 500 may perform data communication with the nonvolatile memory device 10 through the memory interface 520 and the host interface 540 .

The CPU 510 controls an error correction code (ECC) block 530 to detect error bits included in data output from the nonvolatile memory device 10 through the memory interface 520, correct the error bits, and pass the error-corrected data through the host interface 540. sent to the host. The CPU 510 can control data communication between the memory interface 520, the ECC block 530, the host interface 540, and the memory device 550 through the bus 501. Memory system 500 may be implemented as a flash memory drive, a USB memory drive, an IC-USB memory drive, or a memory stick.

FIG. 24 is a block diagram of a memory system 600 including the nonvolatile memory device 10 of FIG. 1 according to yet another embodiment of the inventive concepts. Memory system 600 may be implemented as a data storage system such as a solid state drive (SSD).

The memory system 600 includes: a plurality of nonvolatile memory devices 10; a memory controller 610, which controls the data processing operations of the nonvolatile memory devices 10; a nonvolatile memory device 630 such as a dynamic random access memory (DRAM). the buffer manager 620, which controls the data transferred between the memory controller 610 and the host 640 to be stored in the non-volatile memory device 630;

FIG. 25 is a block diagram of a data processor 700 including the memory system 600 of FIG. 24 . Referring to FIGS. 24 and 25, the data processor 700 may be implemented as a Redundant Array of Independent Disks (RAID) system. The data processor 700 includes a RAID controller 710 and a plurality of memory systems 600-1 to 600-n, where "n" is a natural number.

Each of the memory systems 600-1 to 600-n may be the memory system 600 shown in FIG. 11 . The memory systems 600-1 through 600-n may form a RAID array. Data processor 700 may be a PC or SSD.

During a program operation, in response to a program command received from the host, the RAID controller 710 may transmit program data output from the host to at least one of the memory systems 600-1 to 600-n according to a RAID level. During a read operation, in response to a read command received from the host, the RAID controller 710 may transmit data read from at least one of the memory systems 600-1 to 600-n to the host.

While the inventive concept has been particularly shown and described with reference to certain exemplary embodiments thereof, it will be appreciated by those skilled in the art that other modifications may be made therein without departing from the scope of the inventive concept as defined in the claims. Various modifications in form and detail.

Claims (20)

1. A non-volatile memory device comprising: an array of non-volatile memory cells arranged in association with a plurality of word lines including dummy word lines; access circuitry for selecting a word line among the plurality of word lines in response to a received address during operation, applying a selected word line voltage to the selected word line, applying a non-selected word line voltage to the plurality of word lines unselected word lines in the line, and apply the dummy word line voltage to the dummy word line, Wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage. A second dummy word line voltage different from the dummy word line voltage. 2. The nonvolatile memory device according to claim 1, wherein the operation is a program operation, and a level of the first dummy word line voltage is greater than a level of the second dummy word line voltage. 3. The nonvolatile memory device according to claim 2, wherein the selected word line voltage is a programming voltage, the unselected word line voltage is a pass voltage whose level is lower than the programming voltage, and the first dummy word Line voltage is the pass voltage. 4. The nonvolatile memory device of claim 1, wherein the operation is a read operation, and a level of the first dummy word line voltage is lower than a level of the second dummy word line voltage. 5. The nonvolatile memory device according to claim 4, wherein the selected word line voltage is a first read voltage, and the unselected word line voltage is a first read voltage having a level higher than the first read voltage. The second read voltage and the second dummy word line voltage are the second read voltage and the level of the first dummy word line voltage is higher than the first read voltage and lower than the second read voltage. 6. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory cells are NAND flash memory cells further arranged in strings of NAND memory cells, the nonvolatile memory Units include: a string select transistor coupled to a string select line; ground select transistor, coupled to the ground select line; a plurality of main NAND flash memory cells connected in series between the string selection transistor and the ground selection transistor and respectively coupled to one of the plurality of word lines; Dummy NAND flash memory cells, coupled to dummy word lines. 7. The nonvolatile memory device of claim 5 , wherein the dummy NAND flash memory cell is adjacent to the string selection transistor in the NAND memory string, or the dummy NAND flash memory cell is connected to ground in the NAND memory string. Select transistors are adjacent. 8. The non-volatile memory device of claim 1, wherein the access circuit comprises: a control logic that receives an address and generates a first control signal and a second control signal in response to the received address; a voltage supply circuit configured to generate at least one of a selected word line voltage, an unselected word line voltage, a first dummy word line voltage, and a second dummy word line voltage in response to a first control signal; a row decoder configured to apply the selected word line voltage to the selected word line, the unselected word line voltage to the unselected word line and the dummy word line voltage to the dummy word line in response to the second control signal word line. 9. The non-volatile memory device of claim 8, wherein the control logic comprises: a comparator for comparing a reference address associated with the dummy word line with at least a portion of the received address to provide a comparison signal; The selector provides a first control signal in response to the comparison signal. 10. The non-volatile memory device of claim 9, wherein the selector comprises: a code selector receiving a first code associated with a first dummy word line voltage and a second code associated with a second dummy word line voltage, selectively providing one of the first code and the second code as a first control Signal. 11. The nonvolatile memory device according to claim 8, wherein the voltage supply circuit comprises: a first voltage level generator providing a first dummy word line voltage; an independent second voltage level generator providing second dummy word line voltage. 12. A non-volatile memory device comprising: A vertical memory cell array, including a plurality of nonvolatile memory cells and a plurality of word lines, the plurality of nonvolatile memory cells are arranged in a plurality of memory cell array layers stacked along a first direction, the plurality of The word lines extend along a second direction crossing the first direction and include dummy word lines; access circuitry for selecting a word line among the plurality of word lines in response to a received address during operation, applying a selected word line voltage to the selected word line, applying a non-selected word line voltage to the plurality of word lines unselected word lines in the line, and apply the dummy word line voltage to the dummy word line, Wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the second dummy word line voltage. word line voltage. 13. The nonvolatile memory device according to claim 12, wherein the dummy word line voltage satisfies at least one of the following conditions: The waveform of the first dummy word line voltage is different from the waveform of the second dummy word line voltage, The level of the first dummy word line voltage is different from that of the second dummy word line voltage. 14. The nonvolatile memory device according to claim 13 , wherein each of the plurality of nonvolatile memory cells is a NAND flash memory cell, and the plurality of nonvolatile memory cells are further arranged in strings of NAND memory cells, each of the plurality of NAND flash memory strings extending from the lowest level of the vertical memory cell array to the highest level of the vertical memory cell array, the plurality of NAND flash memory Each of the flash memory strings includes: a string select transistor coupled to a string select line; ground select transistor, coupled to the ground select line; a plurality of main NAND flash memory cells connected in series between the string selection transistor and the ground selection transistor and respectively coupled to one of the plurality of word lines; Dummy NAND flash memory cells, coupled to dummy word lines. 15. The nonvolatile memory device of claim 14, wherein, in the NAND memory string, the dummy NAND flash memory cells are adjacent to the string selection transistor. 16. The nonvolatile memory device of claim 14, wherein the dummy NAND flash memory cells are adjacent to the ground selection transistors in the NAND memory string. 17. A non-volatile memory device comprising: A vertical memory cell array, including a plurality of nonvolatile memory cells and a plurality of word lines, the plurality of nonvolatile memory cells are arranged in a plurality of memory cell array layers stacked along a first direction, the plurality of The word lines extend along a second direction crossing the first direction and include a plurality of dummy word lines; access circuitry for selecting a word line among the plurality of word lines in response to a received address during operation, applying a selected word line voltage to the selected word line, applying a non-selected word line voltage to the plurality of word lines lines, and respectively apply one of the dummy word line voltages among the plurality of dummy word line voltages to each of the plurality of dummy word lines, wherein the plurality of dummy word lines The dummy word line voltages include: a first dummy word line voltage, when the selected word line is not adjacent to the corresponding dummy word line, the first dummy word line voltage is applied to the corresponding dummy word line, The second dummy word line voltage is applied to the corresponding dummy word line when the selected word line is adjacent to the corresponding dummy word line. 18. The nonvolatile memory device according to claim 17, wherein the dummy word line voltage satisfies at least one of the following conditions: The waveform of the first dummy word line voltage is different from the waveform of the second dummy word line voltage, The level of the first dummy word line voltage is different from that of the second dummy word line voltage. 19. A system comprising a memory controller configured to control operation of a non-volatile memory device, wherein the non-volatile memory device comprises: an array of non-volatile memory cells arranged in association with a plurality of word lines including dummy word lines; access circuitry for selecting a word line among the plurality of word lines in response to a received address during operation, applying a selected word line voltage to the selected word line, applying a non-selected word line voltage to the plurality of word lines unselected word lines in the line, and apply the dummy word line voltage to the dummy word line, Wherein, when the selected word line is not adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage, and when the selected word line is adjacent to the dummy word line, the dummy word line voltage is the first dummy word line voltage. A second dummy word line voltage different from the dummy word line voltage. 20. The system of claim 19, further comprising: a processor configured to control the operation of the memory controller; A display configured to display an image defined by the output data obtained from the non-volatile memory device through operation of the memory controller and the processor.

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