CN102819626A - Method for locating intermediate region of through-silicon via (TSV) in three-dimensional (3D) integrated circuit automatic layout - Google Patents

Abstract

The invention provides a method for locating the middle area of a TSV in the automatic layout of a 3D integrated circuit, which belongs to the field of circuit design. In the method of the present invention, the horizontal Cartesian coordinate system is first established with the upper and lower chip edges of the layout respectively, and then the range rectangle formed by the units that need to be interconnected between the two layers of chips in the horizontal direction is determined respectively, and finally the upper and lower layers of the cross-layer line network The range rectangle of the layer performs the AND operation of the horizontal and vertical coordinate intervals to calculate the middle area; the middle area is the determined layout range of the TSV. The TSV inserted in the middle area of the cross-layer net positioned in the present invention can optimize the net length of the cross-layer net, thereby increasing the speed of the circuit.

Description

A method for positioning the middle area of TSV in automatic layout of 3D integrated circuits

field of invention

The present invention generally relates to the design and manufacture of 3D integrated circuits, and more specifically, the present invention relates to a method for automatic layout in 3D integrated circuit design, which belongs to the field of circuit design.

Background technique

The design and manufacturing level of integrated circuits has been developing rapidly, and now hundreds of millions of transistors can be integrated on a single chip. More specifically, according to the description of Moore's Law, the advanced technology level has reached the nanometer level. Due to the increase in the number of transistors on a single chip, ordinary 2D integrated circuits will cause the problem of excessively long lines, which will reduce the operation speed of the circuit and increase power consumption. 3D integrated circuits can effectively reduce line length, improve computing speed, and reduce power consumption.

3D integrated circuits are an emerging technology that reduces the area of a chip by placing multiple IC chips in a vertical direction. At the same time, the units of multi-layer chips can be interconnected through TSV (silicon vias across chip layers). As long as the position of the TSV is placed reasonably, this TSV-based 3D integrated circuit technology can effectively reduce the length of the line network.

FIG. 1 is a schematic diagram of a 3D chip. A 3D integrated circuit is a three-dimensional circuit structure formed by stacking a top chip 1 and a bottom chip 2 . The standard unit 4 in the circuit is the basic structure of the circuit. A 3D circuit chip of a certain layer has properties similar to ordinary 2D chips. Standard cells 4 are interconnected through metal interconnection lines 6 . In a 2D circuit, the collection of all units connected together by metal interconnection lines is collectively called a line network. In a 3D integrated circuit, a net in which all units are on the same layer (similar to a net in a 2D circuit) is a single-layer net. Each unit is also interconnected by metal wires. In a 3D circuit, some units in different layers also need to be interconnected. A net composed of units in different layers is called a cross-layer net, and a net composed of standard units 4 is a cross-layer net. When units in different layers need to be interconnected, TSV5 (through silicon vias) can be used for interconnection.

The upper and lower 2D chip units of the 3D integrated circuit are interconnected through TSV, that is, the TSV is a bridge connecting the upper and lower units of the cross-layer wire network. The position of the TSV in the upper unit set and the lower unit set is the key to the interconnection effect, and an excellent TSV position can greatly optimize the interconnection. Therefore, finding the ideal location of TSV has become one of the keys to TSV positioning.

Unfortunately, there is currently no automatic design method for 3D integrated circuits regarding TSV positioning. Therefore, it is hoped that an automatic design method for 3D integrated circuits can be provided.

Contents of the invention

In order to solve the problem of determining the position of a cross-chip layer silicon via (TSV) in a 3D integrated circuit, the present invention proposes a method for locating the middle area of the TSV in the automatic layout of a 3D integrated circuit.

In the method of the present invention, the positioning range of TSV is determined by the positional relationship of the cross-layer line network, and the steps are as follows:

A. Establish a horizontal Cartesian coordinate system with the upper and lower chip edges of the layout respectively;

B. Determine the range rectangle formed by the units that need to be interconnected in the two layers of chips in the horizontal direction;

C. Perform an AND operation on the range rectangles of the upper and lower layers on the cross-layer network to calculate the middle area; the middle area is the determined layout range of the TSV.

The method for determining the range rectangle is as follows: locate all units in the horizontal rectangular coordinate system with coordinates, calculate the maximum and minimum values of all units in each line network in the direction of horizontal and vertical coordinates, and determine with these four edge values The extent rectangle of the net.

When the result of the AND calculation of the interval for the abscissa of the range rectangle is not an empty set, it is determined that the AND operation result of the above-mentioned abscissa is the abscissa interval of the above-mentioned middle area; when the abscissa of the range rectangle is When the AND calculation result of the interval is an empty set, the closed interval on the abscissa that just connects the two intervals is taken as the interval on the abscissa.

When the result of the AND operation calculation of the interval for the ordinate of the range rectangle is not an empty set, it is determined that the AND operation result of the above-mentioned ordinate is the abscissa interval of the above-mentioned middle area; when the ordinate of the range rectangle is When the AND calculation result of the interval is an empty set, the closed interval of the ordinate that just connects the two intervals is taken as the interval of the ordinate.

The rectangular area enclosed by the above abscissa interval and ordinate interval is the middle area where TSV is installed, and TSV can be installed at any point in the middle area.

The present invention can obtain following beneficial effect:

In any adjacent two-layer chip of a 3D integrated circuit, in the cross-layer wire network formed by the interconnection of cross-layer standard units in the present invention, the TSV inserted in the middle area can make the wire network length of the cross-layer wire network obtain optimized to increase the speed of the circuit.

Description of drawings

Figure 13D is a schematic cross-sectional view of an integrated circuit chip;

Two wire nets of the first positional relationship in Fig. 2;

Two wire nets of the second positional relationship of Fig. 3;

Two line nets of the third positional relationship in Fig. 4;

Two wire nets of the fourth positional relationship in Fig. 5;

Figure 6 is a schematic diagram of the cross-layer wire mesh in the wire mesh area of the upper and lower chips;

Figure 7 Schematic diagram of regional operations.

In the figure: 1. Top-layer chip, 2. Bottom-layer chip, 3. Substrate, 4. Standard cell of top-layer chip, 5. Standard cell of bottom-layer chip, 6. TSV, 7. Metal interconnection line, 8. Top-layer wire mesh area, 9. The range area of the bottom net, 10, the middle area, 11, the coordinates of the lower left corner of the top net, 12, the coordinates of the upper right corner of the top net, 13, the coordinates of the lower left corner of the bottom net, 14, the coordinates of the upper right corner of the bottom net, 15 , additional horizontal wire mesh length, 16, additional vertical wire mesh length, 17, the projection of the bottom new mesh on the Y axis, 18, the projection of the top layer mesh on the Y axis, 19, the projection of the bottom layer mesh on the X axis , 20, the projection of the top-level wire mesh on the X-axis, 21, the overlapping area, 22, the separation area.

Detailed ways

The method for locating the middle area of TSVs in the automatic layout of 3D integrated circuits in the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

A. In the present invention, two adjacent layers of 3D integrated circuit chips are referred to as the top chip and the bottom chip.

Establish a Cartesian coordinate system on the top and bottom chips, take the two edges of the chip as the coordinate axes, as shown in Figure 6, take the left edge as the vertical axis, the lower edge as the horizontal axis, and take the edge intersection point in the lower left corner as the coordinate origin. According to the determined planar Cartesian coordinate system, the coordinates of each standard unit on the top and bottom floors are determined in these two coordinate systems as the basis for describing the positions of all units. Determining the middle area of the TSV is based on the area surrounded by some units of the upper and lower layers of chips where the units that need cross-layer interconnection are respectively located.

B. The units that need cross-layer interconnection are located on the two-layer chips of the integrated circuit. In FIG. 6 , the top-level chip standard unit 4 shown by the solid triangle is the structure of the top-level chip standard unit 4 in FIG. 1 , and their coordinates are determined based on the top-level coordinate axes. In FIG. 6 , the bottom chip standard unit 5 shown by the solid square is the structure of the bottom chip standard unit 5 in FIG. 1 , and their coordinates are determined based on the coordinate axes of the bottom layer. The top chip standard unit 4 and the bottom chip standard unit 5 are the standard units of the upper and lower chip layers in the 3D circuit, and are the basic structure of the circuit.

When determining the range area of the top-level unit, based on the top-level unit, compare the abscissa and ordinate of the unit, compare the maximum and minimum values of the abscissa and ordinate among all units, and determine the rectangle determined by these four edge values That is, the extent area of the top-level and bottom-level nets. As shown in the figure, the top layer wire mesh range area 8, and the bottom layer wire mesh range area 9.

C. After calculating the range rectangle on the two-layer chip of the cross-layer line network, the coordinate axes of the upper and lower two-layer chips are coincident. Make the cross-layer wire mesh area on the two-layer chip be placed in the same coordinate system. As shown in FIG. 7 , the top wire mesh area 8 and the bottom wire mesh area 9 .

After the two layers of chips are placed in the same coordinate system, they are respectively projected (calculate the range intervals of the horizontal and vertical coordinates of the two range areas, and expressing them on the coordinate axes is the projection operation) onto the horizontal and vertical coordinate axes. The projection area is the projection 17 of the bottom line network on the Y axis, the projection 18 of the top line network on the Y axis, the projection 19 of the bottom line network on the X axis, and the projection 20 of the top line network on the X axis. An overlap region 21 and a separation region 22 are formed.

Perform an AND operation on the interval formed by the four projections on the horizontal and vertical axes, if the result is not an empty set, it will be determined as the coordinate range of the middle area in the coordinate direction, which is called the overlapping interval; if the result is empty Set, then the closed interval that can just connect two intervals (that is, the interval between these two non-intersecting intervals) is taken as the range interval of the intermediate area in the coordinate direction, which is called the separation interval. At the same time, the range of the middle area in the two coordinate directions is obtained, so as to determine the rectangular range of the middle area 11 . After the range of the middle area is determined, a point coordinate is randomly generated in the middle area, which is the coordinate of the TSV.

The resulting intermediate region is analyzed as follows:

The cross-layer line networks with different positional relationships have different projection intervals on the two coordinate axes, and their types are the arrangement and combination of overlapped intervals and separated intervals on the horizontal and vertical axes. Four positional relationships are illustrated in Figures 1-4, and the method of the present invention can be applied to cross-layer nets of all positional relationships.

The first position relationship:

Taking the rectangle formed by the two overlapping intervals as the middle area, the middle area is obtained as the area from (x3, y3) to (x2, y2). Figure 2.

The second positional relationship:

Taking the rectangle formed by the coincident interval on the vertical axis and the separation interval on the horizontal axis as the intermediate area, the intermediate area is obtained as the area from (x2, y3) to (x3, y2). Figure 3.

The third position relationship:

Taking the rectangle formed by the separated interval on the vertical axis and the overlapped interval on the horizontal axis as the intermediate area, the intermediate area is obtained as the area from (x3, y2) to (x2, y3). Figure 4.

The fourth position relationship:

Taking the rectangle formed by the separation interval on the vertical axis and the separation interval on the horizontal axis as the middle area, the middle area is the area from (x2, y2) to (x3, y3). Figure 5.

In the optimal area, a point is generated randomly as the coordinates of TSV.

Claims (2)

1. The middle area positioning method of TSV in the automatic layout of 3D integrated circuits is characterized in that: the adopted steps are as follows: A. Establish a horizontal Cartesian coordinate system with the upper and lower chip edges of the layout respectively; B. Determine the range rectangle formed by the units that need to be interconnected in the two layers of chips in the horizontal direction; C. Perform an AND operation on the range rectangles of the upper and lower layers on the cross-layer network to calculate the middle area; the middle area is the determined layout range of the TSV. 2. The method for locating the middle area of TSV in the automatic layout of 3D integrated circuits according to claim 1 is characterized in that: the method for determining the range rectangle is: positioning all units with coordinates in a horizontal Cartesian coordinate system, and calculating The maximum and minimum values of all units in each line network in the direction of horizontal and vertical coordinates, and these four edge values determine the range rectangle of the line network; When the result of the AND calculation of the interval for the abscissa of the range rectangle is not an empty set, it is determined that the AND operation result of the above-mentioned abscissa is the abscissa interval of the above-mentioned middle area; when the abscissa of the range rectangle is When the AND calculation result of the interval is an empty set, the abscissa closed interval that just connects the two intervals is taken as the abscissa interval; When the result of the AND operation calculation of the interval for the ordinate of the range rectangle is not an empty set, it is determined that the AND operation result of the above-mentioned ordinate is the abscissa interval of the above-mentioned middle area; when the ordinate of the range rectangle is When the result of the AND calculation of the interval is an empty set, the closed interval of the ordinate that just connects the two intervals is taken as the interval of the ordinate; The rectangular area enclosed by the above abscissa interval and the ordinate interval is the middle area where the TSV is installed.

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