CN102801488B - A kind ofly be applicable to the intertexture of WiMAX or the implementation method of deinterleaving and device - Google Patents

Abstract

The invention discloses an interleaving or deinterleaving implementation method suitable for WiMAX, the method comprising: obtaining the column factor of an interleaving matrix according to the packet length of original data to be interleaved or to be deinterleaved; according to the column factor of the interleaving matrix , and combine the interleaving address compression table to calculate the read-write control address to complete the interleaving or deinterleaving operation. The present invention also discloses a WiMAX interleaving or deinterleaving realization device, through the method and device, the storage space required for the read and write addresses of original data is reduced, and the interleaving or deinterleaving process is simplified.

Description

A method and device for implementing interleaving or deinterleaving suitable for WiMAX

technical field

The present invention relates to the data transmission technology in the long-term evolution system of the third generation partnership project, in particular to a method and device for implementing WiMAX interweaving or deinterleaving.

Background technique

Interleaving technology is widely used in the communication field to convert burst errors into random errors, so as to reduce the concentration and technical cost of error correction. In order to resist burst errors in the transmission process, sub-blocks in the Worldwide Interoperability for Microwave Access (WiMAX) system are internally interleaved after channel circular convolution coding. Similarly, the receiver needs to perform deinterleaving.

Since the calculation of the read-write address of the original data is relatively complicated during the interleaving or de-interleaving process, the address is calculated in advance in the prior art, and then stored and used further. Since the WiMAX system supports up to 17 packet lengths, and the maximum packet length is 2400, during the process of storing interleaving or deinterleaving, the read and write addresses of the original data need relatively large storage space, and different tables need to be searched according to the packet length. It is used to find out the corresponding address, and the implementation is relatively complicated.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a method and device for realizing interleaving or deinterleaving suitable for WiMAX, which reduces the storage space required for the read and write addresses of original data, and simplifies the process of interleaving or deinterleaving.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

The present invention provides a method for implementing interleaving or deinterleaving suitable for WiMAX, the method comprising:

Obtain the interleaving matrix column factor (m) according to the original data length (N) to be interleaved or to be deinterleaved;

According to the column factor (m) of the interleaving matrix and combined with the interleaving address compression table, the read-write control address is calculated to complete the interleaving or deinterleaving operation.

Wherein, the obtaining the column factors of the interleaving matrix specifically includes: obtaining the column factors of the interleaving matrix by querying the mapping table of the data packet length and the column factors of the interleaving matrix.

Wherein, the read-write control address includes: the read control address of the cache unit before processing, which stores the original data to be interleaved or deinterleaved, and the write control address of the cache unit after processing;

According to the column factors of the interleaving matrix, and combining the interleaving address compression table to calculate the read-write control address, the completion of the interleaving or deinterleaving operation specifically includes: initializing the original address base address, index factor and derivative factor, and combining the interleaving address compression table to obtain the interleaving address base address; calculate and generate a read-write control address according to the interleaved address base address and the original address base address; write the pre-processed cache unit data into the processed cache control unit according to the read-write control address.

Wherein, the calculation and generation of the read-write control address according to the base address of the interleaving address and the base address of the original address is specifically: adding 0, 1, 2, and 3 to the base address of the interleaving address respectively to obtain the read-write address of the four cache units before processing. control address;

Add 0, N/4, 2N/4 and 3N/4 to the base address of the original address respectively to obtain the write control addresses of the four processed cache units.

Wherein, after the cache unit after the write process, it also includes: the original address base address is accumulated by 1, and the derivation factor is accumulated by 1. If the interleaved address base address is accumulated by 2^m and is less than the packet length of the original data, then re-cache the interleaved address Base address, generate a read-write control address, and perform read-write operations; if it is not less than the packet length of the original data, add 2^(m-1) to the cached interleaved address base address, and then generate a read-write control address, and perform read and write operations. Write operation; when the base address of the cached interleaving address is used up, the index factor is accumulated by 1, and if the index factor is not less than N/4, the process ends, otherwise, return to initialize the derivation factor, and execute the subsequent process.

The present invention also provides an interleaving or deinterleaving implementation device suitable for WiMAX, the device includes: a pre-processing buffer unit, a read-write control unit and a post-processing buffer unit, wherein,

The read-write control unit is used to obtain the column factor of the interleaving matrix according to the length of the original data to be interleaved or to be deinterleaved, calculate the read-write control address according to the column factor of the interleave matrix and in combination with the interleaving address compression table, and calculate the read-write control address according to the read Write the control address, read the original data to be interleaved or de-interleaved from the pre-processing cache unit, write into the post-processing cache unit, and complete the interleaving or de-interleaving operation.

Wherein, the read-write control unit obtains the column factors of the interleaving matrix, specifically: by querying the mapping table of the data packet length and the column factors of the interleaving matrix, the column factors of the interleaving matrix are obtained.

Wherein, the read-write control address includes: the read control address of the cache unit before processing, which stores the original data to be interleaved or deinterleaved, and the write control address of the cache unit after processing;

According to the column factor of the interleaving matrix, combined with the interleaving address compression table, the read-write control address is calculated, and according to the read-write control address, the original data to be interleaved or to be deinterleaved is read from the pre-processing cache unit, and written into the processing The rear cache unit specifically includes: initializing the original address base address, index factor, and derivation factor, and combining the interleaving address compression table to obtain the interleaving address base address; calculating and generating the read-write control address according to the interleaving address base address and the original address base address; according to the The read-write control address writes the pre-processing cache unit data into the post-processing cache unit.

The implementation method and device for interleaving or deinterleaving suitable for WiMAX provided by the present invention caches the original data to be interleaved or deinterleaved into the buffer unit before processing; obtains the column factor of the interleaving matrix according to the packet length of the original data ; Combining the interleaving address compression table to calculate the read-write control address, according to the read-write control address, read the original data to be interleaved or to be deinterleaved from the pre-processing cache unit, write into the post-processing cache unit, and complete the interleaving or deinterleaving operation . By sorting out the interleaving addresses of 17 kinds of packet lengths supported by the WiMAX system, and planning the storage content according to the rules discovered therein, a compressed interleaving address storage table suitable for all packet length data is finally given, and cooperates with the storage table A calculation method for interleaving addresses is proposed, which reduces the consumption of storage resources, and reduces the difficulty of interleaving and deinterleaving through the corresponding read and write address generation mechanism. The use of the present invention has great significance for reducing the realization cost of the WiMAX system.

Description of drawings

Fig. 1 is a schematic flow chart of an implementation method of interleaving or deinterleaving suitable for WiMAX according to the present invention;

Fig. 2 is the structural representation of the mapping table of data packet length and interleaving matrix column factor;

Fig. 3 is a schematic structural diagram of an interleaving address compression table;

FIG. 4 is a schematic structural diagram of an implementation device for interleaving or deinterleaving suitable for WiMAX according to the present invention.

Detailed ways

The basic idea of the present invention is to cache the original data to be interleaved or to be deinterleaved into the buffer unit before processing; obtain the column factor of the interleaving matrix according to the data packet length of the original data; combine the interleaving address compression table to calculate the read and write control address, according to The read-write control address reads the original data to be interleaved or deinterleaved from the pre-processing cache unit, writes it into the post-process cache unit, and completes the interleaving or deinterleaving operation.

The technical solutions of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

Fig. 1 is a schematic flow chart of an implementation method of interleaving or deinterleaving suitable for WiMAX according to the present invention. As shown in Fig. 1, the method includes:

Step 101, buffering the original data to be interleaved or to be deinterleaved into the pre-processing buffer unit;

Step 102, obtaining an interleaving matrix column factor according to the length of the original data;

Specifically, obtaining the column factor of the interleaving matrix specifically includes: obtaining the column factor m of the interleaving matrix by querying the length of the original data, that is, the mapping table of the packet length N of the original data and the column factor m of the interleaving matrix. FIG. 2 is a schematic structural diagram of a mapping table between data packet length and interleaving matrix column factors.

Step 103: Calculate the read-write control address according to the column factors of the interleaving matrix and in combination with the interleaving address compression table, and complete the interleaving or deinterleaving operation.

Specifically, the read-write control address includes: the read control address (hereinafter referred to as the read address) for reading the original data from the cache unit before processing, and the write control address (hereinafter referred to as the write address) for writing into the cache unit after processing . According to the column factors of the interleaving matrix, and combining the interleaving address compression table to calculate the read-write control address, the completion of the interleaving or deinterleaving operation specifically includes: initializing the original address base address, index factor and derivative factor, and combining the interleaving address compression table to obtain the interleaving address base address; calculate and generate a read-write control address according to the interleaved address base address and the original address base address; write the pre-processed cache unit data into the processed cache control unit according to the read-write control address.

Further, step 103 specifically includes the following steps:

Step 103a, initialize the base address of the original address to 0, and initialize the index factor i to 0;

Further, in the subsequent step 103e, the base address of the original address will be used as a basis for generating the write address of the processed cache unit.

Step 103b, initialize the derivation factor j to be 0, query from the interleaving address compression table according to the index factor i and the interleaving matrix column factor m, and obtain the interleaving address base address;

Specifically, FIG. 3 is a schematic structural diagram of the interleaving address compression table. As shown in FIG. 3 , Index is an index factor, and ADDR is a read address of the interleaving address compression table corresponding to the index factor. The value of the table lookup is related to the column factor m of the interleaving matrix obtained in step 102, specifically: when m is 10, the value is obtained row by row from the interleaving address compression table according to the index factor; when m is 9, according to the index factor, the Take values from every two rows in the address compression table; when m is 8, take values from every four rows in the interleaved address compression table according to the index factor; and so on, until m is 3, according to the index factor, take values from the interleaved address compression table , take a value every 128 rows; the above rule can be summarized as, according to the index factor, take a value every 2^(10-m) rows from the interleaved address compression table.

Step 103c, cache the base address of the interleaving address;

Specifically, since in step 103b, an interleaving address base address is read every 2^(10-m) rows from the interleaving address compression table, the cached interleaving address base address is one or more.

Step 103d, generate 4 addresses according to the base address of the interleaved address, as the read address of the cache unit before processing;

Specifically, the method of generating the read address of the cache unit before processing is: adding 0, 1, 2 and 3 to the base address of the interleaving address respectively.

Step 103e, generate 4 addresses according to the base address of the original address, as the write address of the cache unit after processing;

Specifically, the write address of the cache unit after processing is generated in the following manner: add 0, N/4, 2N/4, and 3N/4 to the base address of the original address, where N is the packet length of the original data.

Step 103f, according to the read-write control address, read the original data to be interleaved or to be deinterleaved from the pre-processing cache unit, and write it into the post-processing cache unit;

Step 103g, add 1 to the base address of the original address, add 1 to the derivation factor j, add 2^m to the base address of the interleaved address, if the base address of the new interleaved address is not less than the packet length N of the original data, then execute step 103h, otherwise execute step 103c ;

Step 103h, add 2^(m-1) to the base address of the interleaving address cached in step 103c, and then perform steps 103d to 103f, if the base address of the interleaving address cached in step 103c is used up, or the base address of the cached interleaving address After accumulating 2^m, when the base address of the new interleaving address is greater than N, then execute step 103i;

In step 103i, the index factor i is incremented by 1, and if the index factor i is not less than N/4, the process ends, otherwise step 103b is executed.

It should be further noted that the deinterleaving method described in the present invention is basically the same as the interleaving method, the difference is that the "pre-processing buffer unit" stores the data to be deinterleaved, and the "post-processing buffer unit" stores the deinterleaved data. The final result, the intermediate calculation process is the same.

Further, the interleaving address compression table of the present invention organizes the interleaving addresses of 17 kinds of packet lengths supported by the WiMAX system, plans the storage content according to the rules therein, and then obtains the interleaving address compression table. Analysis of the data after interleaving or deinterleaving can be obtained. The interleaving within a sub-block of WiMAX can be summarized as follows: write by row, and then list after interleaving; the number of columns is 2^m, the number of rows is j; the last row Add dummy at the end and delete dummy when outputting; the order of column output is interleaved. Table 1 is the processed data after adding dummy elements with the packet length N=36 as an example:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four 25 26 27 28 29 30 31 32 33 34 35 x x x x x x x x x x x x

Table 1

Among them, x represents a dummy.

In order to speed up the de-interleaving speed, 4-way parallel processing is adopted, and the de-interleaving process is completed by means of interleaved reading and sequential storage. During parallel processing, the address after interleaving is shown in Table 2, specifically:

ADDR0 ADDR1 ADDR2 ADD3 0 1 2 3 16 17 18 19 32 33 34 35 8 9 10 11 twenty four 25 26 27 x x x x 4 5 6 7 20 twenty one twenty two twenty three x x x x 12 13 14 15

28 29 30 31 x x x x

Table 2

It can be seen from Table 2 that at the same time, the second, third, and fourth paths are the results of the first path reading addresses +1, +2, and +3 respectively. If the table is simplified according to this rule, 3/4 of the storage space can be saved by applying the simplified interleaving address compression table of the present invention. In addition, it is further found that in Table 2, every 3 rows is repeated, and each row is incremented by 16, until the accumulated 16 is greater than 36 (ie N), the dummy x is used instead. According to this, only the first row in every 3 rows can be stored, and the values of other rows can be calculated according to the above rules. After this operation, applying the simplified interleaving address compression table of the present invention can further save about 2/3 of the storage space. It can also be seen from Table 2 that in the first row of every 3 rows, adding 8 to the first row of the even group is the value of the first row of the odd group, and thus the table content can be compressed by half. According to the above rules, the table is simplified to obtain the interleaved address compression table and its usage method of the present invention. It can be seen that, adopting the method of the present invention can save a large amount of storage space for reading and writing addresses, and the implementation is also simpler.

The implementation method of interleaving or deinterleaving of the present invention will be set forth below in conjunction with a specific embodiment. In this embodiment, the code block length of the original data is equal to 36 as an example, and the method includes:

Step 401, buffering the original data to be interleaved into the pre-processing buffer unit;

Step 402, since N=36, m=4 can be obtained by querying Figure 2;

Step 403a, initialize the base address of the original address to 0, and initialize the index factor i to 0;

Step 403b, initialization derivation factor j is 0; Since m is 4, therefore from Fig. 3 according to every 2^(10-4)=64 row values, the interleaving address base address that reads is 0;

Step 403c, cache interleaving address base address 0;

Step 403d, generate 4 addresses according to the base address 0 of the interleaving address, which are respectively 0, 1, 2, and 3 as the read addresses of the cache unit before processing;

Step 403e, using the original address base address 0 to derive 4 addresses, respectively 0, N/4=9, 2N/4=18, 3N/4=27, as the write address of the cache unit after processing;

Step 403f, read data from addresses 0, 1, 2, and 3 of the cache unit before processing, and write data into addresses 0, 9, 18, and 27 of the cache unit after processing;

Step 403g, the base address of the original address is accumulated by 1, which is 1 after accumulation, the derivative factor j is accumulated by 1, and is 1 after accumulation, the base address of the interleaving address is accumulated by 2^m, and it is 16 after accumulation, because 16 is less than N=36, then re-cache Interleaving address base address 16 (equivalent to step 103g, return to execute step 103c);

Step 403h, generate 4 addresses according to the interleaving address base address 16, respectively 16, 17, 18, 19 as the read address of the pre-processing cache unit;

Step 403i, using the original address base address 1 to derive 4 addresses, respectively 1, 1+N/4=10, 1+2N/4=19, 1+3N/4=28, as the write address of the cache unit after processing;

Step 403j, read data from addresses 16, 17, 18, and 19 of the cache unit before processing, and write data into addresses 1, 10, 19, and 28 of the cache unit after processing;

Step 403k, the base address of the original address is accumulated by 1, and the accumulated value is 2, the derivation factor j is accumulated by 1, and the accumulated value is 2, the base address of the interleaved address is accumulated by 2^m, and the accumulated value is 32, because 32 is less than N=36, then re-cache Interleave address base address 32 (equivalent to in step 103g, return to execute step 103c);

Step 4031, generate 4 addresses according to the interleaving address base address 32, which are respectively 32, 33, 34, and 35 as the read addresses of the cache unit before processing;

Step 403m, using the original address base address 2 to derive 4 addresses, respectively 2, 2+N/4=11, 2+2N/4=20, 2+3N/4=29 as the write address of the cache unit after processing;

Step 403n, read data from addresses 32, 33, 34, and 35 of the cache unit before processing, and write data into addresses 2, 11, 20, and 29 of the cache unit after processing;

Step 403o, the base address of the original address is accumulated by 1, and the accumulated value is 3, the derivation factor j is accumulated by 1, and the accumulated value is 3, the base address of the interleaving address is accumulated by 2^m, and the accumulated value is 48, because 48 is greater than N=36, and then the cache is used The base address of the interleaving address, calculate the new base address of the interleaving address, repeat steps similar to step 103d to step 103f, and finally when the index factor is not less than N/4, the process ends.

Fig. 4 is a schematic structural diagram of an implementation device for interleaving or deinterleaving suitable for WiMAX according to the present invention. As shown in Fig. 4, the device includes: a pre-processing buffer unit 41, a read-write control unit 42 and a post-processing buffer unit 43 ,in,

The pre-processing buffer unit 41 is used for buffering the original data to be interleaved or to be deinterleaved;

Further, the deinterleaving method described in the present invention is basically the same as the interleaving method, the difference is: when performing interleaving processing, what the buffer unit 41 stores before processing is the data to be interleaved, and what the buffer unit 43 stores after processing is the interleaved data. The result after deinterleaving; when performing deinterleaving processing, the buffer unit 41 before processing stores the data to be deinterleaved, and the buffer unit 43 after processing stores the result after deinterleaving, and the intermediate calculation process is the same.

The read-write control unit 42 is used to obtain the column factor of the interleaving matrix according to the length of the original data to be interleaved or to be deinterleaved, and calculate the read-write control address according to the column factor of the interleaving matrix and in combination with the interleaving address compression table, according to the The read and write control address reads the original data to be interleaved or deinterleaved from the pre-processing cache unit 41, and writes the processed cache unit 43 to complete the interleaving or deinterleaving operation.

Specifically, the obtaining the column factors of the interleaving matrix specifically includes: obtaining the column factors of the interleaving matrix by querying the mapping table of the data packet length and the column factors of the interleaving matrix. The read-write control address includes: a read address for reading original data from the cache unit 41 before processing, and a write address for writing into the cache unit 43 after processing. According to the column factor of the interleaving matrix, combined with the interleaving address compression table, the read-write control address is calculated, and according to the read-write control address, the original data to be interleaved or to be deinterleaved is read from the pre-processing cache unit, and written into the processing The rear cache unit specifically includes: initializing the original address base address, index factor, and derivation factor, and combining the interleaving address compression table to obtain the interleaving address base address; calculating and generating the read-write control address according to the interleaving address base address and the original address base address; according to the The read/write control address writes the data of the pre-processing cache unit 41 into the post-processing cache unit 43 .

Wherein, said generating the read addresses of the 4 pre-processing cache units according to the interleaving address base address is specifically: adding 0, 1, 2 and 3 to the interleaving address base address respectively to obtain the read addresses of the 4 pre-processing cache units; The write addresses of the four processed cache units are generated according to the base address of the original address, specifically: add 0, N/4, 2N/4, and 3N/4 to the base address of the original address respectively to obtain the write addresses of the four processed cache units. address.

Further, the read-write control unit 42 is also used for adding 1 to the base address of the original address and adding 1 to the derivation factor after writing into the cache unit 43 after processing, if the base address of the interleaving address is accumulated 2^m and is less than the value of the original data data packet length, re-cache the interleaved address base address, generate read and write control addresses, and perform read and write operations; if it is not less than the original data packet length, add 2^(m-1) to the cached interleaved address base address, Then generate a read-write control address and perform read-write operations; when the base address of the cached interleaving address is used up, the index factor is accumulated by 1, and if the index factor is not less than N/4, the interleaving or deinterleaving operation is ended, otherwise, the initialization derivative factor is returned, and execute subsequent procedures.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (8)

1. be applicable to the intertexture of WiMAX or an implementation method for deinterleaving, it is characterized in that, described method comprises:

According to waiting to interweave or treat that the initial data length N of deinterleaving obtains interleaver matrix row factor m;

According to described interleaver matrix row factor m, and calculate Read-write Catrol address in conjunction with interleaving address compaction table, complete intertexture or deinterleaving operation;

Described Read-write Catrol address, comprising: before storing the process waiting the initial data interweaving or treat deinterleaving buffer unit read control address, and process after buffer unit write control address;

Described according to the described interleaver matrix row factor, and calculate Read-write Catrol address in conjunction with interleaving address compaction table, complete intertexture or deinterleaving operation specifically comprise: initialization original address base address, index Summing Factor derivative factor, obtain interleaving address base address in conjunction with interleaving address compaction table; Calculate according to described interleaving address base address and original address base address and generate Read-write Catrol address; Caching control unit after buffer unit data write process before processing according to described Read-write Catrol address.

2. method according to claim 1, is characterized in that, the described acquisition interleaver matrix row factor, is specially: by the mapping table of data query packet length and the interleaver matrix row factor, obtains the interleaver matrix row factor.

3. method according to claim 1, it is characterized in that, described calculating according to interleaving address base address and original address base address generates Read-write Catrol address, is specially: described interleaving address base address is added 0,1,2 and 3 respectively, and before obtaining 4 process, buffer unit reads control address;

Described original address base address is added respectively 0, N/4,2N/4 and 3N/4, after obtaining 4 process, writing of buffer units controls address.

4. method according to claim 1, it is characterized in that, after said write process after buffer unit, also comprise: original address base address cumulative 1, derivative factor cumulative 1, is less than the data packet length of initial data after 2^m if add up in interleaving address base address, then buffer memory interleaving address base address again, generate Read-write Catrol address, carry out read-write operation; If be not less than the data packet length of initial data, then added up 2^ (m-1) in the interleaving address base address of buffer memory, then generate Read-write Catrol address, carry out read-write operation; When finishing using in the interleaving address base address of buffer memory, the index factor cumulative 1, if the index factor is not less than N/4, then process ends, otherwise return initialization derivative factor, and perform follow-up flow process.

5. be applicable to the intertexture of WiMAX or an implement device for deinterleaving, it is characterized in that, described device comprises: buffer unit after buffer unit, read-write control unit and process before process, wherein,

Described read-write control unit, wait to interweave or treat that the initial data length N of deinterleaving obtains interleaver matrix row factor m for basis, according to described interleaver matrix row factor m, and calculate Read-write Catrol address in conjunction with interleaving address compaction table, according to described Read-write Catrol address, before process, buffer unit reads the initial data waiting to interweave or treat deinterleaving, buffer unit after write process, completes intertexture or deinterleaving operation;

Described Read-write Catrol address, comprising: before storing the process waiting the initial data interweaving or treat deinterleaving buffer unit read control address, and process after buffer unit write control address;

Described according to the described interleaver matrix row factor, and calculate Read-write Catrol address in conjunction with interleaving address compaction table, according to described Read-write Catrol address, before process, buffer unit reads the initial data waiting to interweave or treat deinterleaving, buffer unit after write process, specifically comprise: initialization original address base address, the index factor, derivative factor, obtain interleaving address base address in conjunction with interleaving address compaction table; Calculate according to interleaving address base address and original address base address and generate Read-write Catrol address; Buffer unit after buffer unit data write process before processing according to described Read-write Catrol address.

6. device according to claim 5, is characterized in that, described read-write control unit obtains the interleaver matrix row factor, is specially: by the mapping table of data query packet length and the interleaver matrix row factor, obtain the interleaver matrix row factor.

7. device according to claim 5, it is characterized in that, described read-write control unit calculates according to interleaving address base address and original address base address and generates Read-write Catrol address, be specially: described interleaving address base address is added 0,1,2 and 3 respectively, before obtaining 4 process, buffer unit reads control address;

Described original address base address is added respectively 0, N/4,2N/4 and 3N/4, after obtaining 4 process, writing of buffer units controls address.

8. device according to claim 5, it is characterized in that, described read-write control unit, also for after buffer unit after write process, original address base address cumulative 1, derivative factor cumulative 1, the data packet length of initial data is less than after 2^m if add up in interleaving address base address, then buffer memory interleaving address base address again, generates Read-write Catrol address, carries out read-write operation; If be not less than the data packet length of initial data, then added up 2^ (m-1) in the interleaving address base address of buffer memory, then generate Read-write Catrol address, carry out read-write operation; When finishing using in the interleaving address base address of buffer memory, the index factor cumulative 1, if the index factor is not less than N/4, then terminates to interweave or deinterleaving operation, otherwise returns initialization derivative factor, and perform follow-up flow process.