CN102801416B - Phase-locked loop circuit - Google Patents

Abstract

A phase-locked loop circuit includes a phase frequency detector, a coarse low-pass filter module, a voltage-controlled oscillator module, and a feedback path. The phase frequency detector is used for comparing the frequency and the phase of the input signal and the feedback signal. The coarse low-pass filter module is coupled to the phase frequency detector and is used for low-pass filtering the control signal with gradually reduced bandwidth to generate a filtering signal, wherein the control signal indicates a comparison result of the input signal and the feedback signal. The voltage-controlled oscillator module has a first voltage-controlled oscillation gain and a second voltage-controlled oscillation gain, and generates an output signal according to the control signal and the filtering signal. The feedback path provides a feedback signal to the pfd according to the output signal.

Description

PLL circuit

technical field

The invention relates to a phase-locked loop circuit, in particular to a phase-locked loop circuit capable of rapidly and accurately locking required frequency and phase.

Background technique

The Phase Lock Loop (PLL) circuit has been developed for a long time, and it is still an important part of technical research, mainly because of its wide application and high development potential. In short, the basic overall function of the phase-locked loop circuit is to use the oscillation source with extremely low frequency variation as a reference, and through the feedback of the closed-loop control system to drive the action of the variable-frequency components, so that it can quickly and Continuously and stably reaching the state of the same phase as the oscillation source is Phase Locked.

In addition, many current PLL circuits adopt a dual-loop design in which a coarse tune loop and a fine tune loop coexist. In consideration of stability, a typical analog dual-loop phase-locked loop uses a large resistor and a large capacitor to form a coarse tuning loop to generate a very low-frequency pole. In addition, for the stability of the dual-loop phase-locked loop during locking, the design of the fine-tuning loop is the main consideration. The traditional dual-loop phase-locked loop architecture has a voltage-controlled oscillator (voltage control oscillator) with low frequency gain (frequency gain; Kvco), and thus has low phase noise (Phase Noise) and excellent power supply rejection ratio (power supply rejection ratio, PSRR).

However, the dual-loop phase-locked loop circuit in the prior art is fixed and excessively limited because of the bandwidth of the coarse-tuning low-pass filter, so the biggest disadvantage of the traditional dual-loop phase-locked loop circuit is that its locking response speed is very slow .

Contents of the invention

The invention provides a phase-locked loop circuit capable of rapidly and accurately locking the required frequency and phase.

The invention proposes a phase-locked loop circuit, which includes a phase-frequency detector, a rough low-pass filter module, a voltage-controlled oscillator module and a feedback path. The phase frequency detector is used to compare the frequency and phase of the input signal and the feedback signal. The coarse adjustment low-pass filter module is used for performing low-pass filtering on a control signal indicating the comparison result of the phase-frequency detector with a gradually narrowed bandwidth to generate a filtered signal. The voltage-controlled oscillator module is used to generate a first oscillating signal according to a control signal with a first voltage-controlled oscillating gain, and is used to generate a second oscillating signal according to a filter signal with a second voltage-controlled oscillating gain, and according to the first The oscillating signal and the second oscillating signal generate an output signal. Wherein the second voltage-controlled oscillation gain is higher than the first voltage-controlled oscillation gain. The feedback path is used to provide a feedback signal to the phase frequency detector according to the output signal.

The invention proposes a phase-locked loop circuit, which includes a phase-frequency detector, a rough low-pass filter module, a voltage-controlled oscillator module and a feedback path. The coarse-tuned low-pass filter module is coupled to the phase-frequency detector and operates with a gradually narrowed bandwidth. The VCO module has a first VCO coupled to the phase frequency detector and a second VCO coupled to the coarse low-pass filter module. The feedback path is coupled between the phase frequency detector and the coarse low-pass filter module.

In an embodiment of the present invention, the above voltage-controlled oscillator module includes a first voltage-controlled oscillator, a second voltage-controlled oscillator and a mixer. The first voltage-controlled oscillator has a first voltage-controlled oscillation gain and is coupled to the phase frequency detector for generating a first oscillation signal according to the control signal. The second voltage-controlled oscillator has a second voltage-controlled oscillation gain and is coupled to the coarse low-pass filter module for generating a second oscillation signal according to the filtered signal. The mixer is coupled to the first voltage-controlled oscillator and the second voltage-controlled oscillator, and is used for mixing the first oscillation signal and the second oscillation signal to generate an output signal.

In an embodiment of the present invention, the bandwidth of the coarse-tuning low-pass filter module is reduced by a predetermined value every preset period.

In an embodiment of the present invention, the aforementioned coarse-tuning low-pass filter module includes a first low-pass filter and a bandwidth controller. The first low-pass filter is coupled to the voltage-controlled oscillator module, and is used for adjusting the bandwidth according to the bandwidth control signal, and performing low-pass filtering on the control signal with the adjusted bandwidth to generate a filtered signal. The bandwidth controller is used to generate and provide a bandwidth control signal to the first low-pass filter, so as to gradually narrow the above-mentioned bandwidth.

In an embodiment of the present invention, the above-mentioned bandwidth controller includes a timer and a second low-pass filter. Timers are used to generate trigger signals. The second low-pass filter is used to generate a bandwidth control signal according to the trigger signal.

In an embodiment of the present invention, the above-mentioned timer generates a trigger signal every preset period, so that the second low-pass filter generates a bandwidth control signal every preset period to instruct the first low-pass filter to reduce above bandwidth.

In an embodiment of the present invention, the above-mentioned first low-pass filter includes a variable resistor and a capacitor. The variable resistor is coupled to the phase frequency detector for changing its resistance value according to the bandwidth control signal. The capacitor has a first end coupled to the system voltage, and a second end coupled to the variable resistor to output a filtered signal.

In an embodiment of the present invention, the above phase-locked loop circuit further includes a charge pump. The charge pump is coupled to the phase frequency detector to generate a control signal according to the comparison result of the phase frequency detector

In an embodiment of the present invention, the above phase-locked loop circuit further includes a loop filter. The loop filter is coupled to the charge pump, and is used for filtering the control signal output by the charge pump to provide to the coarse-tuning low-pass filter module and the voltage-controlled oscillator module.

Based on the above, the bandwidth of the coarse-tuning low-pass filter module of the phase-locked loop circuit of the present invention is gradually reduced. When the phase-locked loop circuit performs frequency locking, the bandwidth of its coarse-tuning low-pass filter module can be changed dynamically, so that the phase-locked loop circuit can quickly and correctly lock the frequency of its output signal to a specific frequency .

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a functional block diagram of a phase-locked loop circuit according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram of a bandwidth controller according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a first low-pass filter according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a first low-pass filter according to another embodiment of the present invention.

FIG. 5 is a circuit diagram of a loop filter of a phase-locked loop circuit according to an embodiment of the present invention.

Reference signs:

100: PLL circuit

110: phase frequency detector

120: Coarse adjustment low-pass filter module

122: Bandwidth controller

124: First low-pass filter

126: Timer

128: second low-pass filter

130: Voltage controlled oscillation module

132: The first voltage-controlled oscillator

134: Second voltage controlled oscillator

136: Mixer

140: Feedback Path

730: Charge pump

740: Loop Filter

C: Capacitance

C1: first capacitor

C2: second capacitor

C _A ～C _n : Capacitance

R: variable resistance

Ra, R1: Resistance

Fref: input signal

Fo: feedback signal

F ₁ : the first oscillation signal

F ₂ : Second oscillation signal

VDD: first system voltage

VSS: second system voltage

K1: the first VCO gain

K2: second voltage controlled oscillation gain

S0～SN: switch

S _C : Control signal

S _F : Filtered signal

St: trigger signal

S _W : Bandwidth control signal

S _W [0]～S _W [N]: bits

S _U : boost control signal

S _D : Buck control signal

Fout: output signal

Detailed ways

In the following embodiments, at the initial stage of the phase-locked loop circuit locking, one of the coarse-tuning low-pass filter modules is set to have a larger bandwidth, so that the frequency of the output signal can be quickly adjusted to around the expected frequency. In addition, at the end of the phase-locked loop circuit locking, the coarse adjustment low-pass filter module is set to have a smaller bandwidth, so that the frequency of the output signal can be accurately adjusted to the expected frequency. As a result, the PLL circuit can quickly and accurately lock the frequency of its output signal to a specific frequency.

Please refer to FIG. 1 , which is a functional block diagram of a phase-locked loop circuit 100 according to a first embodiment of the present invention. The phase frequency detector 110 (phase frequency detector, PFD) is used to compare the frequency and phase of the input signal Fref and the feedback signal Fo, and generate a boost control signal S _U and a buck control signal S _D according to the comparison result.

The charge pump 730 is coupled to the phase frequency detector 110 for receiving and generating the boost control signal S _U and the buck control signal _SD to generate the control signal S _C . In other words, the control signal S _C can indicate the comparison result of the frequency and phase of the input signal Fref and the feedback signal Fo.

In addition, according to design requirements, the PLL circuit 100 may optionally include a primary loop filter 740 . The loop filter 740 is coupled to the charge pump 730 for filtering the control signal S _C output by the charge pump 730 .

The coarse adjustment low-pass filter module 120 is coupled to the phase frequency detector 110 for receiving a control signal S _C indicating a comparison result of the phase frequency detector 110 . As mentioned above, in some embodiments, the coarse adjustment low-pass filter module 120 is coupled to the phase frequency detector 110 through the charge pump 730 , so the control signal S _C is received by the charge pump 730 . In other embodiments, the phase frequency detector 110 can also be coupled to the phase frequency detector 110 through the loop filter 740 , so the control signal S _C can be received by the loop filter 740 .

The coarse low-pass filter module 120 is used for performing low-pass filtering on the control signal S _C with a gradually reduced bandwidth to generate a filtered signal S _F . In other words, when the PLL circuit 100 starts to operate, the bandwidth of the coarse low-pass filter module 120 will be gradually reduced.

FIG. 1 also shows an embodiment of a detailed structure of the coarse low-pass filter module 120 . As shown in FIG. 1 , the coarse adjustment low-pass filter module 120 includes a first low-pass filter 124 and a bandwidth controller 122, wherein the bandwidth of the first low-pass filter 124 is the above-mentioned coarse adjustment low-pass filter The tapered bandwidth of the module 120. The first low-pass filter 124 is coupled to the bandwidth controller 122 for receiving a bandwidth control signal _SW from the bandwidth controller 122 to adjust its bandwidth. In other words, under the control of the bandwidth control signal _SW , the bandwidth of the first low-pass filter 124 (that is, the bandwidth of the coarse low-pass filter module 120 ) is gradually reduced. In addition, the first low-pass filter 124 can receive the control signal S _C , low-pass filter the control signal S _C with the adjusted bandwidth to generate a filtered signal S _F , and provide the filtered signal S _F to the voltage control Oscillation module 130.

The voltage-controlled oscillation module 130 is coupled to the coarse adjustment low-pass filter module 120 and the charge pump 730 (which may pass through the loop filter 740), and is used to generate an output signal Fout according to the control signal S _C and the filter signal S _F simultaneously. . Specifically, the voltage-controlled oscillation module 130 generates the first oscillation signal F ₁ with the first voltage-controlled oscillation gain K1 according to the control signal S _C . In addition, the voltage-controlled oscillation module 130 generates the second oscillation signal _{F 2} with the second voltage-controlled oscillation gain K2 according to the filtered signal S F . Preferably, the second voltage-controlled oscillation gain K2 is higher than the first voltage-controlled oscillation gain K1 , more preferably, the second voltage-controlled oscillation gain K2 is much higher than the first voltage-controlled oscillation gain K1 . The voltage-controlled oscillation module 130 then generates an output signal Fout according to the first oscillation signal _F1 and the second oscillation signal _F2 .

FIG. 1 also shows an embodiment of a detailed structure of the voltage-controlled oscillator module 130 . As shown in FIG. 1 , the VCO module 130 may include a first VCO 132 , a second VCO 134 and a mixer 136 . The first voltage-controlled oscillator 132 has the above-mentioned first voltage-controlled oscillation gain K1 and is coupled to the phase frequency detector 110 for generating the first oscillation signal F ₁ according to the control signal S _C . The second voltage-controlled oscillator 134 has a second voltage-controlled oscillation gain K2 and is coupled to the coarse low-pass filter module 120 for generating a second oscillation signal F ₂ according to the filtered signal S _F . The mixer 136 is coupled to the first voltage-controlled oscillator 132 and the second voltage-controlled oscillator 134 for mixing the first oscillating signal F ₁ and the second oscillating signal F ₂ to generate an output signal Fout. Wherein, the frequency of the output signal Fout is equal to the sum of the frequency of the first oscillating signal F ₁ and the frequency of the second oscillating signal F ₂ .

The VCO module 130 is also coupled to the phase frequency detector 110 via a feedback path 140 . The feedback path 140 can be coupled between the voltage-controlled oscillator module 130 and the phase-frequency detector 110 for providing a feedback signal Fo to the phase-frequency detector according to the output signal Fout.

It should be noted that, in the embodiment shown in FIG. 1 , the output signal Fout and the feedback signal Fo are the same signal. However, the present invention is not limited thereto. For example, in other embodiments, the feedback path 140 includes one or more frequency dividers, that is, the feedback signal Fo may be generated after the output signal Fout is divided by the frequency divider of the feedback path 140 .

Under the above configuration, when the frequency and phase of the input signal Fref are different from the frequency and phase of the feedback signal Fo, the phase-frequency detector 110 will adjust the voltage generated by the voltage-controlled oscillation module 130 by changing the potential of the control signal _SC . The frequency and phase of the feedback signal Fo further make the frequency and phase of the feedback signal Fo approach the frequency and phase of the input signal Fref, and finally make the frequency and phase of the feedback signal Fo and the input signal Fref the same, and complete Locking of output signal Fout and feedback signal Fo.

Specifically, by comparing the frequency and phase of the input signal Fref with the feedback signal Fo by the phase-frequency detector 110, the potential of the control signal S _C can be changed according to the comparison result, and then the voltage-controlled oscillation module 130 can be used to change the potential of the first The frequency of an oscillating signal _F1 . In addition, since the filtered signal S _F is obtained by low-pass filtering the control signal S _C by the coarse adjustment low-pass filter module 120, that is, there is a certain degree of difference between the potential of the filtered signal S _F and the potential of the control signal S _C relevant. Therefore, when the potential of the control signal S _C is adjusted, the potential of the filter signal S _F also changes accordingly, and then the frequency of the second oscillating signal F ₂ can be changed by the voltage-controlled oscillation module 130 . As a result, by adjusting the potential of the control signal S _C , the frequencies of the first oscillating signal F ₁ and the second oscillating signal F ₂ can be changed simultaneously, thereby changing the frequency and phase of the feedback signal Fo. After repeating the above adjustments, the frequency and phase of the feedback signal Fo can approach the frequency and phase of the input signal Fref, and finally achieve the locking of the output signal Fout and the feedback signal Fo

It must be understood that since the coarse low-pass filter module 120 has a gradually narrowed bandwidth, the PLL circuit 100 can quickly and correctly lock the feedback signal Fo to a specific frequency. The principle will be described in detail below.

When the phase-locked loop circuit 100 locks the frequency and phase of the feedback signal Fo, its locking response speed is related to the bandwidth of the coarse-tuning low-pass filter module 120 . When the bandwidth of the coarse-tuning low-pass filter module 120 is larger, the locking response speed of the phase-locked loop circuit 100 is slower, but the locking frequency accuracy is lower. On the contrary, when the bandwidth of the coarse-tuning low-pass filter module 120 is smaller, the locking response speed of the phase-locked loop circuit 100 is faster, but with higher precision.

In this embodiment, after the PLL circuit 100 starts to operate, the bandwidth of the coarse low-pass filter module 120 is set to gradually narrow. In this way, at the initial stage when the phase-locked loop circuit 100 locks the feedback signal Fo, the frequency of the feedback signal Fo can be quickly adjusted to Around the frequency of the input signal Fref. Next, at the end of the phase-locked loop circuit 100 locking the feedback signal Fo, because the coarse adjustment low-pass filter module 120 has a smaller bandwidth, the frequency of the feedback signal Fo can be accurately adjusted to the input signal Fref Frequency of. As a result, the PLL circuit 100 can quickly and accurately lock the feedback signal Fo to a specific frequency.

It should be noted that the detailed structure shown in FIG. 1 is only for illustration purpose. Various other circuits can be used to realize the voltage-controlled oscillation module 130, as long as two oscillation signals can be generated according to the control signal S _C and the filter signal S _F , and then the output signal Fout can be generated according to the two oscillation signals. Can.

Please refer to FIG. 2 , which is a functional block diagram of the bandwidth controller 122 according to an embodiment of the present invention. In this embodiment, the bandwidth controller 122 includes a timer 126 and a second low-pass filter 128 . The timer 126 is used to generate the trigger signal St. The second low-pass filter 128 is coupled to the timer 126 for generating the aforementioned bandwidth control signal _SW according to the trigger signal St.

Preferably, the timer 126 generates the trigger signal St every preset period (for example, 50 milliseconds), so that the second low-pass filter 128 controls the first low-pass filter 124 to reduce its bandwidth. In this way, the bandwidth of the first low-pass filter 124 can be adjusted down successively. In addition, the down-tuning operation can be performed until the bandwidth of the first low-pass filter 124 is reduced to a preset minimum bandwidth. It must be understood that the aforementioned preset period and minimum bandwidth can be set differently according to actual needs, and the present invention is not limited thereto.

In order to realize the above operation mode, in one embodiment, the timer 126 can be configured to generate the trigger signal St every preset period to trigger the second low-pass filter 128 to generate the bandwidth control signal S every preset period _w . Whenever the first low-pass filter 124 receives the bandwidth control signal _SW , its bandwidth is reduced by a predetermined value. As a result, the bandwidth of the first low-pass filter 124 (that is, the bandwidth of the coarsely adjusted low-pass filter module 120 ) can be reduced by a predetermined value every preset period.

It should be noted that the timer 126 can be reset, so that the PLL circuit 100 starts to lock the input signal Fref and the feedback signal Fo again. For example, in one embodiment, when the timer 126 receives the reset signal Rst, it will send out a corresponding trigger signal St, so that the second low-pass filter 128 generates a corresponding bandwidth control signal _SW , And the bandwidth of the first low-pass filter 124 is restored to the original unreduced state. After the timer 126 is reset, the second low-pass filter 128 can be triggered again to narrow the bandwidth of the first low-pass filter 124 .

Please refer to FIG. 3 , which is a circuit diagram of the first low-pass filter 124 according to an embodiment of the present invention. The first low-pass filter 124 includes a variable resistor R and a capacitor C. The variable resistor R is coupled to the phase frequency detector 110 . A first terminal of the capacitor C is coupled to the first system voltage VDD, and a second terminal of the capacitor C is coupled to the variable resistor R to output the filter signal S _F . Under this configuration, the bandwidth controller 122 can transmit the bandwidth control signal _SW to the first low-pass filter 124 to change the resistance value of the variable resistor R, thereby narrowing the bandwidth of the first low-pass filter 124 . In other words, the variable resistor R changes its own resistance value according to the bandwidth control signal _SW .

Please refer to FIG. 4 , which is a circuit diagram of the first low-pass filter 124 according to another embodiment of the present invention. In this embodiment, the first low-pass filter 124 includes a resistor Ra, a plurality of capacitors C _A -C _n , and a plurality of switches S0 -SN. The resistor Ra is coupled to the phase frequency detector 110 . The first terminals of each of the capacitors C _A -C _n are coupled to the first system voltage VDD, the second terminals of the capacitors C _A are coupled to the resistor Ra, and the second terminals of the capacitors C _B -C _n pass through the switches S0 -SN Connect to resistor Ra. In this embodiment, the aforementioned bandwidth control signal _SW is a (N+1)-bit digital control signal, and each bit is used to control one of the switches S0˜SN. For example: Bit _SW [0] is used to control the switch S0, bit _SW [1] is used to control the switch S1, and bit _SW [N] is used to control the switch SN. By controlling the on states of the switches S0-SN, the overall equivalent capacitance value of the capacitors C _A -C _n can be changed, and then the bandwidth of the first low-pass filter 124 can be changed.

It must be understood that the first low-pass filter 124 in FIG. 3 and FIG. 4 is only two kinds of various first low-pass filters that can be used in the phase-locked loop circuit of the present invention, and the present invention does not rely on this limit. For example, Figure 3 and Figure 4 can be implemented in combination. Those skilled in the art should understand that the first low-pass filter can also be implemented with other circuit forms.

Please refer to FIG. 5 , which is a circuit diagram of a loop filter 740 of a phase-locked loop circuit according to an embodiment of the present invention. In this embodiment, the loop filter 740 has a resistor R1, a first capacitor C1 and a second capacitor C2 to form a resistor-capacitor (RC) loop. One end of the first capacitor C1 and the second capacitor C2 are coupled to the second system voltage VSS, the other end of the first capacitor C1 is coupled to one end of the resistor R1 , and the other end of the resistor R1 is coupled to the charge pump 730 . The function of the loop filter 740 is to low-pass filter the control signal S _C output by the charge pump 730 to filter out the high-frequency noise in the control signal S _C , thereby improving the stability of the voltage-controlled oscillator module 130 during operation. It must be understood that the loop filter 740 in FIG. 5 is only one of various low-pass filters that can be used in the PLL circuit of the present invention, and the present invention is not limited thereto. Those skilled in the art should understand that the low-pass filter used in each embodiment of the present invention can be implemented in other circuit forms.

To sum up, when the phase-locked loop circuit of the above-mentioned embodiment performs frequency locking, the bandwidth of the coarse-tuning low-pass filter module can be changed dynamically, and will be gradually reduced, so it can be quickly and accurately The ground locks the frequency of its output signal to a specific frequency.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention, and any person of ordinary skill in the art may make some changes and modifications without departing from the spirit and scope of the present invention.

Claims (17)

1. A phase-locked loop circuit, comprising: a phase frequency detector for comparing the frequency and phase of an input signal and a feedback signal; A coarse-tuning low-pass filter module; a voltage controlled oscillator module; and A feedback path for providing the feedback signal to the phase frequency detector according to an output signal, characterized in that: The coarse adjustment low-pass filter module is used to low-pass filter a control signal indicating the comparison result of the phase frequency detector with a gradually narrowed bandwidth to generate a filtered signal; and The voltage-controlled oscillator module is used to generate a first oscillation signal according to the control signal with a first voltage-controlled oscillation gain, and is used to generate a second oscillation signal according to the filter signal with a second voltage-controlled oscillation gain. an oscillating signal, and generating the output signal according to the first oscillating signal and the second oscillating signal, wherein the second voltage-controlled oscillating gain is higher than the first voltage-controlled oscillating gain. 2. The phase-locked loop circuit according to claim 1, wherein the voltage-controlled oscillator module comprises: A first voltage-controlled oscillator, which has the first voltage-controlled oscillation gain, is coupled to the phase frequency detector, and is used to generate the first oscillation signal according to the control signal; a second voltage-controlled oscillator, which has the second voltage-controlled oscillation gain, and is coupled to the coarse low-pass filter module, for generating the second oscillation signal according to the filtered signal; and A mixer, coupled to the first voltage-controlled oscillator and the second voltage-controlled oscillator, is used for mixing the first oscillation signal and the second oscillation signal to generate the output signal. 3 . The phase-locked loop circuit according to claim 1 , wherein the bandwidth of the coarse low-pass filter module is reduced by a predetermined value every preset period. 4. The phase-locked loop circuit according to claim 1, wherein the coarse adjustment low-pass filter module comprises: a first low-pass filter, coupled to the voltage-controlled oscillator module, for adjusting the bandwidth according to a bandwidth control signal, and performing low-pass filtering on the control signal with the adjusted bandwidth , resulting in the filtered signal; and A bandwidth controller is used to generate and provide the bandwidth control signal to the first low-pass filter to gradually reduce the bandwidth. 5. The PLL circuit according to claim 4, wherein the bandwidth controller comprises: a timer for generating a trigger signal; and A second low-pass filter is used for generating the bandwidth control signal according to the trigger signal. 6. The phase-locked loop circuit according to claim 5, wherein the timer generates the trigger signal every preset period, so that the second low-pass filter generates the bandwidth control signal every preset period to instruct the first low-pass filter to reduce the bandwidth. 7. The phase-locked loop circuit according to claim 4, wherein the first low-pass filter comprises: a variable resistor, coupled to the phase frequency detector, for changing its resistance value according to the bandwidth control signal; and A capacitor has a first terminal coupled to a system voltage, and a second terminal coupled to the variable resistor to output the filtered signal. 8. The PLL circuit according to claim 1, further comprising a charge pump coupled to the phase frequency detector to generate the control signal according to the comparison result of the phase frequency detector. 9. The phase-locked loop circuit according to claim 8, further comprising a loop filter coupled to the charge pump for filtering the control signal output by the charge pump to provide the coarse adjustment low pass filter module and the voltage controlled oscillator module. 10. A phase-locked loop circuit, comprising: a phase frequency detector for comparing the frequency and phase of an input signal and a feedback signal; a coarse low-pass filter module coupled to the phase frequency detector; a voltage controlled oscillator module having a first voltage controlled oscillator coupled to the phase frequency detector; and A feedback path, coupled between the phase frequency detector and the coarse adjustment low-pass filter module, is used to provide the feedback signal to the phase frequency detector according to an output signal, characterized in that: the coarse low pass filter module operates with a progressively narrower bandwidth to low pass filter a control signal indicative of the comparison result of the phase frequency detector to generate a filtered signal; and The voltage-controlled oscillator module further has a second voltage-controlled oscillator coupled to the coarse-tuning low-pass filter module, for generating a first oscillation signal according to the control signal, and for generating a first oscillation signal according to the filtered signal to generate a second oscillating signal, and generate the output signal according to the first oscillating signal and the second oscillating signal. 11. The phase-locked loop circuit according to claim 10, wherein the first voltage-controlled oscillator has a first voltage-controlled oscillation gain, the second voltage-controlled oscillator has a second voltage-controlled oscillation gain, and the second The voltage-controlled oscillation gain is higher than the first voltage-controlled oscillation gain. 12. The PLL circuit according to claim 10, wherein the voltage-controlled oscillator module further comprises a mixer coupled to the first voltage-controlled oscillator and the second voltage-controlled oscillator. 13. The PLL circuit according to claim 10, further comprising a charge pump coupled to the phase frequency detector. 14. The phase-locked loop circuit according to claim 13, further comprising a loop filter, coupled between the charge pump and the coarse low-pass filter module, and coupled between the charge pump and the Between the first VCO of the VCO module. 15 . The phase-locked loop circuit according to claim 10 , wherein the bandwidth of the coarse low-pass filter module is reduced by a predetermined value every preset period. 16. The PLL circuit according to claim 10, wherein the coarse low-pass filter module comprises: a first low-pass filter, coupled to the VCO module, for adjusting the bandwidth according to a bandwidth control signal; and A bandwidth controller is used to generate and provide the bandwidth control signal to the first low-pass filter. 17. The PLL circuit according to claim 16, wherein the bandwidth controller comprises: a timer for generating a trigger signal; and A second low-pass filter is used for generating the bandwidth control signal according to the trigger signal.