CN102800595B - NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method - Google Patents
NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method Download PDFInfo
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- CN102800595B CN102800595B CN201110139434.6A CN201110139434A CN102800595B CN 102800595 B CN102800595 B CN 102800595B CN 201110139434 A CN201110139434 A CN 201110139434A CN 102800595 B CN102800595 B CN 102800595B
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 239000004065 semiconductor Substances 0.000 title abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 96
- 239000000758 substrate Substances 0.000 claims abstract description 79
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 75
- 239000010703 silicon Substances 0.000 claims abstract description 75
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 72
- 239000012535 impurity Substances 0.000 claims abstract description 70
- 238000000137 annealing Methods 0.000 claims abstract description 51
- 238000002347 injection Methods 0.000 claims abstract description 34
- 239000007924 injection Substances 0.000 claims abstract description 34
- 150000002500 ions Chemical class 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
- 229920005591 polysilicon Polymers 0.000 claims description 88
- 238000005468 ion implantation Methods 0.000 claims description 43
- 230000015572 biosynthetic process Effects 0.000 claims description 38
- 238000002513 implantation Methods 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 21
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 abstract 5
- 239000002344 surface layer Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- 238000005516 engineering process Methods 0.000 description 11
- 238000003384 imaging method Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- -1 phosphonium ion Chemical class 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004064 recycling Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses an NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method, which comprises the steps of: providing a silicon substrate, forming a gate oxide on the surface of the silicon substrate, and forming a polycrystalline silicon layer on the surface of the gate oxide; performing ion injecting on a fluoride containing N-type impurity in the polycrystalline silicon layer; etching the gate oxide and the polycrystalline silicon layer to form a grid electrode, and forming a source region and a drain region in the silicon substrates on the two sides of the grid electrode; and annealing the polycrystalline silicon layer. The invention further provides a corresponding COMOS structure forming method. The fluorinion in the polycrystalline silicon layer is diffused to the surface layer of the substrate through annealing treatment and is combined with the silicon to form a silicon-fluorin bond so as to relieve the hot carrier injection effect of the NMOS transistor, and the fluorinion is injected in the substrate in the diffusion mode so as not to be easily changed into gas to escape during the annealing process, so that the dosage of the fluorinion diffused to the substrate can be high.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly can reduce the nmos pass transistor formation method of the hot carrier injection effect of nmos pass transistor and the CMOS structure formation method of correspondence.
Background technology
Along with improving constantly of semiconductor device integrated level, characteristic size reduces gradually, and the length of the raceway groove of MOS transistor also reduces gradually.Simultaneously, input/output device as chip periphery circuit and the core devices as memory all need higher driving voltage, it is very strong that this just causes the electric field in the raceway groove of these devices to become, charge carrier is collided ionization in course of conveying, produce extra hole-electron pair, produce hot carrier, longitudinal voliage makes part hot carrier in jection gate oxide, the parameters such as the threshold voltage of device are caused to be drifted about, form comparatively serious hot carrier injection effect (Hot Carrier Injection, HCI).Because electronics is different from the mean free path in hole, probability 3 orders of magnitude higher than hole of electron injection, therefore nmos pass transistor more easily causes hot carrier injection effect (HCI).
Usually LDD (Lightly Doped Drain is adopted in prior art, lightly doped drain injects) ion implantation is optimized, the patent No. is that the american documentation literature of US 6004852 discloses a kind of method making LDD source-drain area, utilize the dosage and increase LDD Implantation Energy that reduce LDD ion implantation, obtain darker LDD knot, reduce transverse electric field intensity, thus weaken hot carrier in jection problem.But the limited efficiency of said method, but also the problems such as short-channel effect (SCE, Short Channel Effect) may be caused.
Also utilize in prior art and fluorine ion is directly injected into silicon substrate top layer to alleviate hot carrier injection effect, concrete MOS transistor schematic diagram please refer to Fig. 1, described MOS transistor comprises the source region 11 and drain region 12 that are positioned at silicon substrate 10, be positioned at the fluorine ion 14 on silicon substrate 10 top layer, on silicon substrate 10 surface and grid 13 between source region 11 and drain region 12, described fluorine ion 14 utilizes ion implantation technology to be directly injected into silicon substrate top layer.But the fluorine ion that heavy dose is injected into silicon substrate top layer can again form fluorine molecule and overflow from silicon substrate in annealing process.Because surface of silicon is formed with oxide layer film usually, fluorine molecule can not effusion can be gathered between silicon substrate and oxide layer film smoothly, and described oxide layer film can form the projection of air bubble-shaped one by one, has a strong impact on device performance.Therefore, the dosage being injected into the fluorine ion of silicon substrate can not be too high, but the fluorine ion of low dosage can not alleviate hot carrier injection effect effectively.
Summary of the invention
The problem that the present invention solves is to provide nmos pass transistor formation method and corresponding CMOS structure formation method, to reduce the hot carrier injection effect in nmos pass transistor and CMOS structure.
For solving the problem, technical solution of the present invention provides a kind of nmos pass transistor formation method, comprising: provide silicon substrate, forms gate oxide in described surface of silicon, forms polysilicon layer on described gate oxide surface; The fluoride ion of containing N type impurity is injected in described polysilicon layer; Etching is carried out to described gate oxide and polysilicon layer and forms grid, in the silicon substrate of grid both sides, form source region and drain region; Annealing in process is carried out to described polysilicon layer.
Optionally, the fluoride of described containing N type impurity is PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.
Optionally, the Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
Optionally, described annealing temperature is 600 DEG C ~ 1000 DEG C, and the time of annealing is 30min ~ 60min.
Optionally, described annealing in process or carry out in hydrogen, nitrogen wherein a kind of or both mixtures, or carry out in a vacuum.
Technical solution of the present invention also provides a kind of CMOS structure formation method, comprise: silicon substrate is provided, in described silicon substrate, form N well region and the P well region adjacent with N well region, form gate oxide at described N well region and P well region surface, form polysilicon layer on described gate oxide surface; By p type impurity ion implantation in described polysilicon layer; The fluoride ion of containing N type impurity is injected in the polysilicon layer above P well region; Described gate oxide and polysilicon layer being etched, forms grid at N well region and P well region surface, forming source region and drain region to carrying out ion doping in the N well region of grid both sides, P well region respectively; Annealing in process is carried out to described polysilicon layer.
Optionally, described p type impurity is B, In, BF
2, BF
3, InF
3the wherein combination of a kind of or a few person.
Optionally, the Implantation Energy scope of described p type impurity ion implantation is 1KeV ~ 10KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
Optionally, the fluoride of described containing N type impurity is PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.
Optionally, the Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
Optionally, the polysilicon layer of the fluoride of described injection containing N type impurity at least comprises the polysilicon layer of the grid for forming nmos pass transistor.
Optionally, the dosage of the fluoride of the containing N type impurity of described ion implantation is greater than the dosage of the p type impurity of ion implantation.
Optionally, the dosage of the fluoride of the containing N type impurity of described ion implantation is at least the twice of the dosage of the p type impurity of ion implantation.
Optionally, described annealing temperature is 600 DEG C ~ 1000 DEG C, and the time of annealing is 30min ~ 60min.
Optionally, described annealing in process or carry out in hydrogen, nitrogen wherein a kind of or both mixtures, or carry out in a vacuum.
Compared with prior art, the present invention has the following advantages:
By the fluoride of containing N type impurity is injected in polysilicon layer, fluorine ion is diffused into surface of silicon by recycling annealing in process, fluorine ion is combined with silicon on silicon substrate top layer and forms the very large fluosilicic key of bond energy, stop that the hot carrier in raceway groove enters gate oxide, so just greatly alleviate hot carrier injection effect.And be not easy again to become gas effusion when high annealing because fluorine ion is injected into substrate surface by the mode of diffusion, the dosage being diffused into the fluorine ion of substrate surface can be higher, more fluosilicic key can be formed to stop that hot carrier in jection is to gate oxide, reduce the hot carrier injection effect of NMOS.
When forming CMOS structure, because the N-type polycrystalline silicon layer above P well region is formed by N-type impurity ion implantation transoid, therefore the dosage being injected into the containing N type impurity fluoride of described polysilicon layer can be very large, more fluosilicic key can be formed to stop that hot carrier in jection is to gate oxide, and the fluoride of implanting p-type impurity, containing N type impurity only need form a photoresist and carry out mask to ion implantation, simplifies technological process.
Accompanying drawing explanation
Fig. 1 is a kind of MOS structure schematic diagram reducing hot carrier injection effect in prior art;
Fig. 2 is the schematic flow sheet of the nmos pass transistor formation method of the embodiment of the present invention;
Fig. 3 to Fig. 6 is the cross-sectional view of the nmos pass transistor formation method of the embodiment of the present invention;
Fig. 7 is the schematic flow sheet of the CMOS structure formation method of the embodiment of the present invention;
Fig. 8 to Figure 13 is the cross-sectional view of the CMOS structure formation method of the embodiment of the present invention.
Embodiment
The fluorine ion being injected into silicon substrate top layer due to heavy dose can again form fluorine molecule and overflow from silicon substrate in annealing process, inventor finds through research, in NMOS structure manufacturing process, by the fluoride of containing N type impurity is injected in polysilicon layer, fluorine ion is diffused into surface of silicon by recycling annealing in process, fluorine ion is combined with silicon on silicon substrate top layer and forms the very large fluosilicic key of bond energy, stop that the hot carrier in raceway groove enters gate oxide, so just greatly alleviate hot carrier injection effect.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
The invention provides a kind of nmos pass transistor formation method, specifically please refer to Fig. 2, comprise step: step S101, silicon substrate is provided, form gate oxide in described surface of silicon, form polysilicon layer on described gate oxide surface; Step S102, is injected into the fluoride ion of containing N type impurity in described polysilicon layer; Step S103, carries out etching to described gate oxide and polysilicon layer and forms grid, in the silicon substrate of grid both sides, form source region and drain region; Step S104, carries out annealing in process to described polysilicon layer.
Fig. 3 to Fig. 6 is the cross-sectional view of nmos pass transistor formation method of the present invention.
Please refer to Fig. 2 and Fig. 3, perform step S101, silicon substrate 100 is provided, form gate oxide 120 on described silicon substrate 100 surface, form polysilicon layer 140 on described gate oxide 120 surface.
Described silicon substrate 100 can be the surperficial silicon substrate being formed with epitaxial loayer, also can be silicon-on-insulator substrate.In embodiments of the present invention, silicon substrate 100 is the silicon substrate that surface is formed with epitaxial loayer.
The method forming described gate oxide 120 forms gate oxide 120 for utilizing thermal oxidation technology or depositing operation on described silicon substrate 100 surface, and the material of described gate oxide is silicon dioxide.The method forming described polysilicon layer 140 is adopt the method for chemical vapour deposition (CVD) or low-pressure chemical vapor deposition to form polysilicon layer 140 on gate oxidation 120 surface.The technology forming described gate oxide film layer and polysilicon layer film is known to the skilled person technology, does not add detailed description at this.
Please refer to Fig. 2 and Fig. 4, perform step S102, the fluoride ion of containing N type impurity is injected in described polysilicon layer 140.Concrete steps comprise: form photoresist layer (not shown) on described polysilicon layer 140 surface, exposure imaging is carried out to photoresist layer and forms patterned photoresist layer, make mask with described patterned photoresist layer and inject N-type impurity ion 141, fluorine ion 142 in polysilicon layer 140.
The fluoride of described containing N type impurity comprises PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.The Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
Please refer to Fig. 2 and Fig. 5, perform step S103, etching is carried out to described gate oxide 120 and polysilicon layer 140 and forms grid 150, in the silicon substrate 100 of grid 150 both sides, form source region and drain region.
The step that etching forms grid 150 comprises: form photoresist layer (not shown) on described polysilicon layer surface, exposure imaging is carried out to photoresist layer and forms patterned photoresist layer, make mask with described patterned photoresist layer and dry etching is carried out to polysilicon layer and gate oxide, until expose silicon substrate 100.
The step forming source region and drain region in the silicon substrate 100 of grid 150 both sides comprises: form photoresist layer (not shown) at silicon substrate 100 and grid 150 surface, exposure imaging is carried out to photoresist layer and forms patterned photoresist layer, with described photoresist layer and grid 150 for mask, first time N-type impurity ion implantation is carried out to the silicon substrate 100 of grid 150 both sides, form light dope source/drain region 111, the ion of described injection is wherein a kind of or both combination of phosphonium ion, arsenic ion;
Described grid 150 sidewall forms side wall 155, and the material of described side wall 155 can be the laminated construction of silica, silicon nitride wherein one or both;
At silicon substrate 100, grid 150, side wall 155 surface forms photoresist layer (not shown), exposure imaging is carried out to photoresist layer and forms patterned photoresist layer, with described photoresist layer, grid 150 and side wall 155 are mask, second time N-type impurity ion implantation is carried out to the light dope source/drain region 111 of side wall 155 both sides, form heavy doping source/drain region 112, the ion of described injection is phosphonium ion, arsenic ion is a kind of or both combination wherein, the dosage of the dose ratio first time ion implantation of described second time ion implantation is large, generally can large 1 to 2 order of magnitude, and the degree of depth of the depth ratio first time ion implantation of second time ion implantation wants dark.
Optionally, behind formation light dope source/drain region 111, first annealing is carried out to described silicon substrate, behind formation heavy doping source/drain region 112, second annealing is carried out to described silicon substrate, to activate the ion injected.
Please refer to Fig. 2 and Fig. 6, perform step S104, annealing in process is carried out to described polysilicon layer.
Described annealing in process or carry out in hydrogen, nitrogen wherein a kind of or both mixtures, or carry out in a vacuum, annealing temperature is 600 DEG C ~ 1000 DEG C, and the time of annealing is 30min ~ 60min.Please refer to Fig. 6, through the annealing in process of 30 to 60 minutes, fluorine ion 142 in polysilicon layer can be diffused into substrate 100 top layer under gate oxide, and activate fluorine ion 142, fluorine ion 142 is combined with the silicon on substrate 100 top layer and forms fluosilicic key, because the bond energy of fluosilicic key is very large, the hot carrier in jection in described fluosilicic key stop raceway groove, to gate oxide, alleviates nmos pass transistor hot carrier injection effect.
Described annealing in process can after step 2, namely carries out annealing in process to polysilicon layer being injected into after in polysilicon layer by the fluoride ion of containing N type impurity, also can carry out after step 3, namely after formation nmos pass transistor, carry out annealing in process to polysilicon layer.
Be not easy again to become gas effusion when high annealing because fluorine ion is injected into substrate surface by the mode of diffusion, the dosage being diffused into the fluorine ion of substrate surface can be higher, more fluosilicic key can be formed to stop that hot carrier in jection is to gate oxide, reduce the hot carrier injection effect of NMOS.
Grid due to nmos pass transistor in the embodiment of the present invention is N-type grid, and the longitudinal voliage that described N-type grid is formed can suppress part hot carrier in jection to gate oxide, also can alleviate hot carrier injection effect.
The present invention also provides a kind of CMOS structure formation method, specifically please refer to Fig. 7, comprise step: step S201, silicon substrate is provided, N well region and the P well region adjacent with N well region is formed in described silicon substrate, form gate oxide at described N well region and P well region surface, form polysilicon layer on described gate oxide surface; Step S202, by p type impurity ion implantation in described polysilicon layer; Step S203, is injected into the fluoride ion of containing N type impurity in the polysilicon layer above P well region; Step S204, etches described gate oxide and polysilicon layer, forms grid at N well region and P well region surface, forms source region and drain region respectively to carrying out ion doping in the N well region of grid both sides, P well region; Step S205, carries out annealing in process to described polysilicon layer.
Fig. 8 to Figure 13 is the cross-sectional view of CMOS structure formation method of the present invention.
Please refer to Fig. 7 and Fig. 8, perform step S201, silicon substrate 200 is provided, N well region 212 and the P well region 211 adjacent with N well region 212 is formed in described silicon substrate 200, form gate oxide 220 at described N well region 212 and P well region 211 surface, form polysilicon layer 230 on described gate oxide 220 surface.
Described silicon substrate 200 or be formed with the silicon substrate of epitaxial loayer for surface, or be silicon-on-insulator substrate.In embodiments of the present invention, silicon substrate 100 is the silicon substrate that surface is formed with epitaxial loayer.
The method forming P well region 211 and N well region 212 comprises: form photoresist layer (not shown) on described silicon substrate 200 surface, exposure imaging is carried out to photoresist layer and exposes the silicon substrate 200 needing to form P well region, mask is made with patterned photoresist layer, implanting p-type impurity in described silicon substrate 200, forms P well region 211; Photoresist layer (not shown) is again formed on described silicon substrate 200 surface, exposure imaging is carried out to photoresist layer and exposes the silicon substrate 200 needing to form N well region, make mask with patterned photoresist layer, in described silicon substrate 200, inject N-type impurity, form N well region 212.Wherein, described N well region 212 is disposed adjacent with P well region 211.
Between described N well region 212 and P well region 211, form isolation structure 213 to prevent from leaking electricity between N well region 212 and P well region 211, affect device performance.Optionally, described isolation structure is fleet plough groove isolation structure (STI), and the formation method of fleet plough groove isolation structure is known to the skilled person technology, does not add detailed description at this.
The method forming described gate oxide 220 forms gate oxide 220 for utilizing thermal oxidation technology or depositing operation at described N well region 212 and P well region 211 surface, and the material of described gate oxide is silicon dioxide.The method forming described polysilicon layer 230 is adopt the method for chemical vapour deposition (CVD) or low-pressure chemical vapor deposition to form polysilicon layer 230 on gate oxide 220 surface.The technology forming described gate oxide and polysilicon layer is known to the skilled person technology, does not add detailed description at this.
Please refer to Fig. 7 and Fig. 9, perform step S202, by p type impurity 231 ion implantation in described polysilicon layer 230.Described p type impurity is boron (B), indium (In), BF
2, BF
3, InF
3wherein one or more combination.The Implantation Energy scope of described ion implantation is 1KeV ~ 10KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer film.
When the p type impurity 231 injected is BF
2, BF
3, InF
3during the combination of one or more wherein, carry out annealing in process to polysilicon layer, fluorine ion can be diffused into underlayer surface and be combined with silicon and generate fluosilicic key, stops that hot carrier in jection in raceway groove is to gate oxide, the hot carrier injection effect of alleviation PMOS transistor.
Please refer to Fig. 7 and Figure 10, perform step S203, the fluoride ion of containing N type impurity is injected in the polysilicon layer 230 above P well region 211.Concrete steps comprise: form photoresist layer (not shown) on described polysilicon layer 230 surface, exposure imaging is carried out to photoresist layer and exposes the polysilicon layer 230 needing the fluoride injecting containing N type impurity, make mask with patterned photoresist layer, in described polysilicon layer 230, inject N-type impurity ion 232, fluorine ion 233.
Wherein, the polysilicon layer injecting containing N type impurity fluoride at least comprises the polysilicon layer of the grid for forming nmos pass transistor.The fluoride of described containing N type impurity comprises PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.The Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer film.Owing to needing that the grid on P well region is become N-type by P type transoid, the dosage of the containing N type impurity fluoride of ion implantation is greater than the dosage of the p type impurity of ion implantation, and the dosage of the fluoride of described containing N type impurity is at least the twice of the dosage of p type impurity.Because the hot carrier in nmos pass transistor raceway groove is electronics, after the polysilicon layer film above P well region becomes N-type polycrystalline silicon layer from P type polysilicon layer transoid, the grid of the nmos pass transistor formed is N-type grid, N-type grid can suppress hot carrier in jection in raceway groove to gate oxide, alleviates hot carrier injection effect.
Please refer to Fig. 7 and Figure 11, Figure 12, perform step S204, described gate oxide and polysilicon layer being etched, forms grid at N well region 212 and P well region 211 surface, forming source region and drain region to carrying out ion implantation in the N well region 212 of grid both sides, P well region 211 respectively.
Described grid comprises and is positioned at the grid 251 on P well region 211 and the grid 252 on N well region 212, and grid 251 and grid 252 can synchronously be formed.Please refer to Figure 11, the concrete steps forming grid comprise: form photoresist layer (not shown) on described polysilicon layer surface, exposure imaging is carried out to photoresist layer and exposes the polysilicon layer that needs etch away, mask is made with patterned photoresist layer, dry etching is carried out to polysilicon layer and gate oxide, until expose substrate 200.The method forming described grid is known to the skilled person technology, does not add detailed description at this.
Please refer to Figure 12, in the P well region 211 of grid 251 both sides, carry out N-type ion implantation form source/drain region 261, in the N well region 212 of grid 252 both sides, carry out P type ion implantation form source/drain region 262.In other embodiments, can exchange with the position in source region in P well region and drain region in N well region.The N-type ion of described ion implantation is wherein a kind of or both combination of phosphonium ion, arsenic ion, and the P type ion of described ion implantation is wherein a kind of or both combination of boron ion, indium ion.
After described ion implantation, annealing in process can be carried out to described silicon substrate 200, to activate the ion injected.
Optionally, the source region of formation and the step in drain region comprise: in the substrate of grid both sides, carry out the first ion implantation, form lightly doped source-drain area; Described gate lateral wall forms side wall; In the substrate of side wall both sides, carry out the second ion implantation, form heavily doped source-drain area.The dosage of the dose ratio first time ion implantation of described second time ion implantation is large, generally can large 1 to 2 order of magnitude, and the degree of depth of the depth ratio first time ion implantation of second time ion implantation wants dark.After the lightly doped source-drain area of formation, the first annealing is carried out to described silicon substrate, after the heavily doped source-drain area of formation, the second annealing is carried out to described silicon substrate, to activate the ion injected.
Please refer to Fig. 7, perform step S205, annealing in process is carried out to described polysilicon layer.Described annealing in process or carry out in hydrogen, nitrogen wherein a kind of or both mixtures, or carry out in a vacuum, annealing temperature is 600 DEG C ~ 1000 DEG C, and the time of annealing is 30min ~ 60min.Please refer to Figure 13, through the annealing in process of 30 to 60 minutes, fluorine ion 233 in polysilicon layer can be diffused into substrate 200 top layer under gate oxide, and activate fluorine ion 233, fluorine ion 233 is combined with the silicon of underlayer surface and forms fluosilicic key, because the bond energy of fluosilicic key is very large, described fluosilicic key stops that in raceway groove, hot carrier in jection, to gate oxide, alleviates the hot carrier injection effect of nmos pass transistor.
Described annealing in process can after step 3, namely carries out annealing in process to polysilicon layer being injected into after in polysilicon layer by the fluoride ion of containing N type impurity, also can carry out after step 4, namely after formation CMOS structure, carry out annealing in process to polysilicon layer.
The embodiment of the present invention is by being injected in polysilicon layer by fluoride, fluorine ion is diffused into substrate surface by recycling annealing in process, fluorine ion to be combined with silicon at substrate surface and to form the very large fluosilicic key of bond energy, stop that the hot carrier in raceway groove enters gate oxide, so just greatly alleviate hot carrier injection effect.And be not easy again to become gas effusion when high annealing because fluorine ion is injected into substrate surface by the mode of diffusion, the dosage being diffused into the fluorine ion of substrate surface can be higher, can form more fluosilicic key to stop that hot carrier in jection is to gate oxide.
When forming CMOS structure, because the N-type polycrystalline silicon layer above P well region is formed by N-type impurity ion implantation transoid, therefore the dosage being injected into the containing N type impurity fluoride of described polysilicon layer can be very large, more fluosilicic key can be formed to stop that hot carrier in jection is to gate oxide, and the fluoride of implanting p-type impurity, containing N type impurity only need form a photoresist and carry out mask to ion implantation, simplifies technological process.
Grid due to PMOS transistor is P-type grid electrode, and the grid of nmos pass transistor is N-type grid, and the longitudinal voliage that described P-type grid electrode, N-type grid are formed can suppress part hot carrier in jection to gate oxide, also can alleviate hot carrier injection effect.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a nmos pass transistor formation method, comprising:
Silicon substrate is provided, forms gate oxide in described surface of silicon, form polysilicon layer on described gate oxide surface;
By p type impurity ion implantation in described polysilicon layer;
The fluoride ion of containing N type impurity is injected in described polysilicon layer, make fluorine ion be diffused into silicon substrate top layer to be combined with silicon and to generate fluosilicic key, the dosage being injected into the containing N type impurity fluoride of described polysilicon layer must be greater than the dosage of the p type impurity in the polysilicon layer be injected into above P well region;
Etching is carried out to described gate oxide and polysilicon layer and forms grid, in the silicon substrate of grid both sides, form source region and drain region;
Annealing in process is carried out to described polysilicon layer.
2. nmos pass transistor formation method as claimed in claim 1, it is characterized in that, the fluoride of described containing N type impurity is PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.
3. nmos pass transistor formation method as claimed in claim 1, is characterized in that, the Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
4. nmos pass transistor formation method as claimed in claim 1, it is characterized in that, described annealing temperature is 600 DEG C ~ 1000 DEG C, and the time of annealing is 30min ~ 60min.
5. the nmos pass transistor method of being formationed as claimed in claim 1, is characterized in that, described annealing in process or carry out in hydrogen, nitrogen wherein one or both mixtures, or carries out in a vacuum.
6. a CMOS structure formation method, comprising:
Silicon substrate is provided, in described silicon substrate, forms N well region and the P well region adjacent with N well region, form gate oxide at described N well region and P well region surface, form polysilicon layer on described gate oxide surface;
By p type impurity ion implantation in described polysilicon layer;
The fluoride ion of containing N type impurity is injected in the polysilicon layer above P well region, make fluorine ion be diffused into silicon substrate top layer to be combined with silicon and to generate fluosilicic key, the dosage being injected into the containing N type impurity fluoride of described polysilicon layer must be greater than the dosage of the p type impurity in the polysilicon layer be injected into above P well region;
Described gate oxide and polysilicon layer being etched, forms grid at N well region and P well region surface, forming source region and drain region to carrying out ion doping in the N well region of grid both sides, P well region respectively;
Annealing in process is carried out to described polysilicon layer.
7. CMOS structure formation method as claimed in claim 6, it is characterized in that, described p type impurity is B, In, BF
2, BF
3, InF
3the wherein combination of a kind of or a few person.
8. CMOS structure formation method as claimed in claim 6, it is characterized in that, the Implantation Energy scope of described p type impurity ion implantation is 1KeV ~ 10KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
9. CMOS structure formation method as claimed in claim 6, it is characterized in that, the fluoride of described containing N type impurity is PF
3, PF
5, AsF
3, AsF
5wherein a kind of or wherein several combinations.
10. CMOS structure formation method as claimed in claim 6, is characterized in that, the Implantation Energy scope that the fluoride ion of described containing N type impurity injects is 1KeV ~ 20KeV, and implantation dosage scope is 1E13atom/cm
2~ 1E16atom/cm
2, the degree of depth of injection is less than the thickness of polysilicon layer.
11. CMOS structure formation methods as claimed in claim 6, is characterized in that, the polysilicon layer of the fluoride of described injection containing N type impurity at least comprises the polysilicon layer of the grid for forming nmos pass transistor.
12. CMOS structure formation methods as claimed in claim 6, is characterized in that, the dosage of the fluoride of the containing N type impurity of described ion implantation is greater than the dosage of the p type impurity of ion implantation.
13. CMOS structure formation methods as claimed in claim 12, is characterized in that, the dosage of the fluoride of the containing N type impurity of described ion implantation is at least the twice of the dosage of the p type impurity of ion implantation.
14. CMOS structure formation methods as claimed in claim 6, it is characterized in that, described annealing temperature is 600 DEG C ~ 1000 DEG C, the time of annealing is 30min ~ 60min.
15. CMOS structure formation methods as claimed in claim 6, is characterized in that, described annealing in process or carry out in hydrogen, nitrogen wherein a kind of or both mixtures, or carry out in a vacuum.
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| US10854459B2 (en) * | 2017-09-28 | 2020-12-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure passivating species drive-in method and structure formed thereby |
| CN112997272B (en) * | 2018-11-20 | 2024-03-29 | 长江存储科技有限责任公司 | Formation methods and annealing equipment for epitaxial layers and 3D NAND memory |
| CN111933696B (en) * | 2020-10-14 | 2020-12-25 | 南京晶驱集成电路有限公司 | Method for manufacturing semiconductor device |
| CN112382642B (en) * | 2020-11-25 | 2022-08-16 | 华虹半导体(无锡)有限公司 | Method for manufacturing silicon-rich oxide layer for CIS |
| CN118299271A (en) * | 2024-06-06 | 2024-07-05 | 杭州积海半导体有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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| US5814863A (en) * | 1996-05-23 | 1998-09-29 | Chartered Semiconductor Manufacturing Company, Ltd. | Substrate with gate electrode polysilicon/gate oxide stack covered with fluorinated silicon oxide layer and fluorinated corners of gate oxide layer |
| CN101572250A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, p-type MOS transistor and manufacturing method thereof |
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| US5814863A (en) * | 1996-05-23 | 1998-09-29 | Chartered Semiconductor Manufacturing Company, Ltd. | Substrate with gate electrode polysilicon/gate oxide stack covered with fluorinated silicon oxide layer and fluorinated corners of gate oxide layer |
| CN101572250A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, p-type MOS transistor and manufacturing method thereof |
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