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CN102799479A - Mainboard with multifunctional basic input output system (BIOS) and test method thereof - Google Patents

Mainboard with multifunctional basic input output system (BIOS) and test method thereof Download PDF

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Publication number
CN102799479A
CN102799479A CN2011101380396A CN201110138039A CN102799479A CN 102799479 A CN102799479 A CN 102799479A CN 2011101380396 A CN2011101380396 A CN 2011101380396A CN 201110138039 A CN201110138039 A CN 201110138039A CN 102799479 A CN102799479 A CN 102799479A
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China
Prior art keywords
bios
pin
gpio interface
function
mainboard
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Pending
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CN2011101380396A
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Chinese (zh)
Inventor
唐新桥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
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Hongfujin Precision Industry Shenzhen Co Ltd
Hon Hai Precision Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Hongfujin Precision Industry Shenzhen Co Ltd, Hon Hai Precision Industry Co Ltd filed Critical Hongfujin Precision Industry Shenzhen Co Ltd
Priority to CN2011101380396A priority Critical patent/CN102799479A/en
Priority to TW100118783A priority patent/TW201248169A/en
Publication of CN102799479A publication Critical patent/CN102799479A/en
Pending legal-status Critical Current

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Abstract

The invention discloses a mainboard with a multifunctional basic input output system (BIOS). The mainboard also comprises a general purpose input output (GPIO) interface, a jumper wire and a power supply, wherein the multifunctional BIOS is connected with the GPIO interface, and comprises the program code of a test version BIOS and the program code of a delivery version BIOS; the multifunctional BIOS selects to execute the program code of the test version BIOS or the program code of the delivery version BIOS according to the state bit of the GPIO; and the jumper wire comprises three pins, wherein the first pin is connected with the power supply, the second pin is connected with the GPIO interface, and the third pin is grounded. The invention also provides a test method for the mainboard with the multifunctional BIOS. By the test method, the function of the test version BIOS can be realized when the mainboard with the multifunctional BIOS is tested, and the function of the shipment version BIOS can be realized after the delivery of the mainboard.

Description

Mainboard and method of testing thereof with multi-functional BIOS
Technical field
The present invention relates to a kind of mainboard and method of testing thereof with multi-functional BIOS.
Background technology
In the test process of some mainboards, the client tends to cause testing process to carry out normally to the specific (special) requirements of shipment version BIOS.For example, the customer requirement burning has the computing machine of shipment version BIOS to get in the operating system of client's independent research, then tests the operating system that computer-chronograph just can't enter into test usefulness.In this case; Factory prepares the BIOS burning document of two versions usually at present; First off-line burning beta version BIOS on mainboard, burning shipment version BIOS again again before mainboard test finishing back shipment, or tool using changes beta version BIOS into shipment version BIOS.But this several method all needs BIOS developer to safeguard the BIOS of two kinds of versions, increases development effort and cost.In addition, in testing process, also need the increase program revise bios version, this all has certain negative effect to testing process management and control and test duration.
Summary of the invention
In view of above content, be necessary to provide a kind of mainboard with multi-functional BIOS, this multi-functional BIOS can realize the function of beta version BIOS when mainboard is tested, can also after the mainboard shipment, realize the function of shipment version BIOS.
Also be necessary to provide a kind of method of testing of multi-functional BIOS mainboard, can make this multi-functional BIOS when mainboard is tested, realize the function of beta version BIOS, after the mainboard shipment, realize the function of shipment version BIOS.
A kind of mainboard with multi-functional BIOS; This mainboard also comprises GPIO interface, wire jumper and power supply; Wherein: said multi-functional BIOS is connected with said GPIO interface; Comprise the program code of beta version BIOS and the program code of shipment version BIOS, said multi-functional BIOS selects to carry out the program code of beta version BIOS or the program code of shipment version BIOS according to the mode bit of this GPIO; Said wire jumper comprises three Pin pin, and a Pin pin links to each other with said power supply, and the 2nd Pin pin links to each other with said GPIO interface, the 3rd Pin pin ground connection.
A kind of method of testing of multi-functional BIOS mainboard may further comprise the steps: read step: when the computer starting of this mainboard was installed, said multi-functional BIOS read the level information of this GPIO interface, thereby obtained the mode bit of this GPIO; Select step: multi-functional BIOS selects to carry out the function of beta version BIOS or the function of shipment version BIOS according to the mode bit of this GPIO.
Compared to prior art, the present invention has mainboard and the method for testing thereof of multi-functional BIOS, can make this multi-functional BIOS when mainboard is tested, realize the function of beta version BIOS, after the mainboard shipment, realizes the function of shipment version BIOS.
Description of drawings
Fig. 1 is the Organization Chart that the present invention has the mainboard preferred embodiment of multi-functional BIOS.
Fig. 2 is that the program code of multi-functional BIOS is realized synoptic diagram.
Fig. 3 is the process flow diagram of the method for testing preferred embodiment of the multi-functional BIOS mainboard of the present invention.
The main element symbol description
Mainboard 1
Multi-functional BIOS 2
The GPIO interface 3
Wire jumper 4
Power supply 5
Resistance 6
The Pin pin 100、200、300
Following embodiment will combine above-mentioned accompanying drawing to further specify the present invention.
Embodiment
Consulting shown in Figure 1ly, is the Organization Chart that the present invention has mainboard 1 preferred embodiment of multi-functional BIOS.This mainboard 1 comprises multi-functional BIOS (Basic Input Output System, Basic Input or Output System (BIOS)) 2, GPIO (General Purpose Input Output, general I/O) interface 3 and wire jumper 4.
Said multi-functional BIOS 2 is one group of ROM (read-only memory) (Read-only Memory that are cured on the mainboard 1; ROM) program on, it is in store to be equipped with that most important basic input/output routine, system are provided with information, startup self-detection program and system's self-triggered program etc. in the computing machine of mainboard 1.That it provides the bottom for this computing machine and the most directly hardware setting and control.In the present embodiment; Newly-increased one section computer program in this multi-functional BIOS 2; This section computer program possibly be divided into one or more software modules; Be used for when mainboard 1 is tested, making multi-functional BIOS 2 to realize the function of beta version BIOS, after mainboard 1 shipment, make multi-functional BIOS 2 realize the function of shipment version BIOS.
Said beta version BIOS is meant generally speaking, the BIOS of burning when mainboard 1 test.Through this beta version BIOS, can make the computing machine that mainboard 1 is installed get into the required environment of test, in the operating system like test usefulness.
Said shipment version BIOS is meant according to client's the specific (special) requirements BIOS in mainboard 1 burning.Mainboard 1 shipment after this shipment version of burning BIOS.Through this shipment version BIOS, can make the computing machine that mainboard 1 is installed get into the environment of customer requirement, in the operating system like client's independent research.
The program code difference of this beta version BIOS and shipment version BIOS is little; Generally be some boot sequences parameter is set and to the difference of the use-pattern of some hardware resources; Require SATA (the Serial Advanced Technology Attachment among the BIOS when for example testing; Serial Advanced Technology Attachment) pattern is set to IDE (Integrated Drive Electronics; Ide) pattern, and the SATA pattern among the BIOS that shipment requires is set to RAID (Redundant Array of Independent Disk, raid-array) pattern.
Comprise the program code of beta version BIOS and the program code of shipment version BIOS among the multi-functional BIOS 2, wherein the same program code section of beta version BIOS and shipment version BIOS can be shared.Select to carry out different programs code section among beta version BIOS and the shipment version BIOS through case statements such as IF statements among the multi-functional BIOS 2.
As shown in Figure 2, be that the program code of multi-functional BIOS 2 is realized synoptic diagram.In the program code of multi-functional BIOS 2, the global variable of a Boolean type can be set earlier, and the program code part of selecting to carry out beta version BIOS according to the value of this global variable is set, or the program code part of shipment version BIOS.For example; When this global variable is " TRUE "; Can carry out beta version bios program code part, thereby make multi-functional BIOS 2 realize the function of beta version BIOS, when this global variable is " FALSE "; Can carry out shipment version bios program code part, thereby make multi-functional BIOS 2 realize the function of shipment version BIOS.
Consult shown in Figure 1ly again, multi-functional BIOS 2 can come to be this global variable assignment through the value that reads said GPIO interface 3 mode bits, thereby selects to realize the function of beta version BIOS, still realizes the function of shipment version BIOS.
GPIO interface 3 can be positioned at the South Bridge chip group of mainboard 1.GPIO interface 3 is connected with wire jumper 4 through resistance 6, and this wire jumper 4 comprises 3 Pin pin, is respectively Pin pin 100, Pin pin 200 and Pin pin 300, and wherein Pin pin 100 is connected to power supply 5, and Pin pin 200 connects GPIO interface 3,300 ground connection of Pin pin.Between Pin pin 200 and GPIO interface 3, also be connected with resistance 6, this resistance 6 is used for preventing that GPIO interface 3 from burning in power up.In other embodiments, the resistance 6 between GPIO interface 3 and the Pin pin 200 can not wanted yet.
When making Pin pin 100 with 200 short circuits of Pin pin through the jumping cap, GPIO interface 3 will be a high level owing to connecting power supply 5, and when making Pin pin 200 with 300 short circuits of Pin pin through the jumping cap, GPIO interface 3 will be a low level owing to ground connection.Multi-functional BIOS 2 can obtain the mode bit of GPIO interface 3 through reading GPIO interface 3 residing level informations, and this level information is one of high level or low level.For example, the mode bit of GPIO interface 3 is that 1 expression GPIO interface 3 is in high level, and the mode bit of GPIO interface 3 is that 0 expression GPIO interface 3 is in low level.
The two states position that multi-functional BIOS 2 can be provided with GPIO interface 3 respectively with the corresponding relation of the function of the function of beta version BIOS and shipment version BIOS.For example, when the mode bit that reads GPIO interface 3 as multi-functional BIOS 2 is 1, will select to carry out beta version bios program code part.When the mode bit that reads GPIO interface 3 as multi-functional BIOS 2 is 0, will select to carry out shipment version bios program code part.Therefore when needs are tested mainboard 1, can make Pin pin 100 and 200 short circuits of Pin pin through jumping cap, the mode bit that makes GPIO interface 3 is 1, and multi-functional BIOS 2 selects to carry out beta version bios program code part, thereby realizes the function of beta version BIOS.When test finishes when needing shipment to mainboard 1, can make Pin pin 200 and 300 short circuits of Pin pin through jumping cap, the mode bit of GPIO interface 3 is 0, multi-functional BIOS 2 selects to carry out shipment version bios program code parts, thereby realizes the function of shipment version BIOS.
Consulting shown in Figure 3ly, is the process flow diagram of the method for testing preferred embodiment of the multi-functional BIOS mainboard of the present invention.
The two states position that GPIO interface 3 is set in multi-functional BIOS 2 earlier respectively with the corresponding relation of the function of the function of beta version BIOS and shipment version BIOS.
Step S01 is connected with Pin pin 200 at GPIO interface 3, and Pin pin 100 is connected with power supply 5; After Pin pin 300 ground connection; When the computer starting of mainboard 1 was installed, multi-functional BIOS 2 read the level information of GPIO interface 3, thereby obtained the mode bit of GPIO interface 3.When Pin pin 100 and 200 short circuits of Pin pin, GPIO interface 3 is a high level owing to connecting power supply 5, and the mode bit of GPIO interface 3 is first numerical value (as 1) at this moment.When Pin pin 200 and 300 short circuits of Pin pin, GPIO interface 3 is owing to ground connection is low level, and the mode bit of GPIO interface 3 is second value (as 0) at this moment.
Step S02, multi-functional BIOS 2 selects to realize the function of beta version BIOS or the function of shipment version BIOS according to the mode bit of this GPIO interface 3.
Above embodiment is only unrestricted in order to technical scheme of the present invention to be described; Although the present invention is specified with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that; Can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the spirit and the scope of technical scheme of the present invention.

Claims (9)

1.一种具有多功能BIOS的主板，其特征在于，该主板还包括GPIO接口、跳线和电源，其中： 1. A kind of mainboard with multifunctional BIOS, it is characterized in that, this mainboard also comprises GPIO interface, jumper and power supply, wherein: 所述多功能BIOS与所述GPIO接口连接，包括测试版本BIOS的程序代码和出货版本BIOS的程序代码，所述多功能BIOS根据该GPIO的状态位选择执行测试版本BIOS的程序代码或出货版本BIOS的程序代码； The multi-function BIOS is connected to the GPIO interface, including the program code of the test version BIOS and the program code of the shipping version BIOS, and the multi-function BIOS selects to execute the program code of the test version BIOS or the shipping version according to the status bit of the GPIO. Program code of version BIOS; 所述跳线包括三个Pin脚，第一Pin脚与所述电源相连，第二Pin脚与所述GPIO接口相连，第三Pin脚接地。 The jumper includes three pins, the first pin is connected to the power supply, the second pin is connected to the GPIO interface, and the third pin is grounded. 2.如权利要求1所述的具有多功能BIOS的主板，其特征在于，所述第二Pin脚和GPIO接口之间还连接有电阻。 2. The motherboard with multi-function BIOS as claimed in claim 1, wherein a resistor is connected between the second Pin and the GPIO interface. 3.如权利要求1或2所述的具有多功能BIOS的主板，其特征在于，当第二Pin脚与第一Pin脚短路时，GPIO接口为高电平，此时GPIO接口的状态位为第一数值；当第二Pin脚与第三Pin脚短路时，GPIO接口为低电平，此时GPIO接口的状态位为第二数值。 3. the motherboard with multi-function BIOS as claimed in claim 1 or 2, is characterized in that, when the second Pin was short-circuited with the first Pin, the GPIO interface was a high level, and now the state position of the GPIO interface was The first value; when the second Pin and the third Pin are short-circuited, the GPIO interface is at low level, and the status bit of the GPIO interface is the second value at this time. 4.如权利要求3所述的具有多功能BIOS的主板，其特征在于，所述第一数值为1，第二数值为0。 4. The motherboard with multi-function BIOS according to claim 3, wherein the first value is 1, and the second value is 0. 5.一种权利要求1中所述主板的测试方法，其特征在于，该方法包括以下步骤： 5. a method for testing main board described in claim 1, is characterized in that, the method comprises the following steps: 读取步骤：当安装有该主板的计算机启动时，所述多功能BIOS读取该GPIO接口的电平信息，从而获得该GPIO的状态位； Reading step: when the computer with the motherboard installed starts, the multifunctional BIOS reads the level information of the GPIO interface, thereby obtaining the status bit of the GPIO; 选择步骤：多功能BIOS根据该GPIO的状态位选择执行测试版本BIOS的功能或出货版本BIOS的功能。 Selection step: the multi-function BIOS selects to execute the function of the test version BIOS or the function of the shipping version BIOS according to the status bit of the GPIO. 6.如权利要求5所述的主板测试方法，其特征在于，该方法在读取步骤前还包括第一设置步骤：设置GPIO接口的状态位与测试版本BIOS的功能和出货版本BIOS的功能的对应关系。 6. mainboard test method as claimed in claim 5, is characterized in that, this method also comprises the first setting step before reading step: the status bit of GPIO interface is set and the function of test version BIOS and the function of shipping version BIOS corresponding relationship. 7.如权利要求5所述的主板测试方法，其特征在于，该方法还包括第二设置步骤： 7. motherboard testing method as claimed in claim 5, is characterized in that, this method also comprises second setting step: 设置第二Pin脚与第一Pin脚短路，使得GPIO接口为高电平，此时GPIO接口的状态位为第一数值；或 Set the second Pin to be short-circuited with the first Pin, so that the GPIO interface is at a high level, and the status bit of the GPIO interface is the first value at this time; or 设置第二Pin脚与第三Pin脚短路，使得GPIO接口为低电平，此时GPIO接口的状态位为第二数值。 The second pin and the third pin are short-circuited so that the GPIO interface is at a low level, and the status bit of the GPIO interface is the second value at this time. 8.如权利要求7所述的主板测试方法，其特征在于，所述选择步骤包括： 8. main board testing method as claimed in claim 7, is characterized in that, described selection step comprises: 如果GPIO接口的状态位为第一数值，则选择执行测试版本BIOS的功能；或 If the state bit of the GPIO interface is the first value, then select the function of executing the test version BIOS; or 如果GPIO接口的状态位为第二数值，则选择执行出货版本BIOS的功能。 If the status bit of the GPIO interface is the second value, the function of the BIOS of the shipped version is selected to be executed. 9.如权利要求8所述的主板测试方法，其特征在于，所述第一数值为1，第二数值为0。 9. The motherboard testing method according to claim 8, wherein the first numerical value is 1, and the second numerical value is 0.
CN2011101380396A 2011-05-26 2011-05-26 Mainboard with multifunctional basic input output system (BIOS) and test method thereof Pending CN102799479A (en)

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TW100118783A TW201248169A (en) 2011-05-26 2011-05-30 Motherboard with a multi-function BIOS and testing method

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CN107818032A (en) * 2017-10-24 2018-03-20 郑州云海信息技术有限公司 A kind of mainboard, information Method of printing, system, device and storage medium
CN108959169A (en) * 2018-06-26 2018-12-07 郑州云海信息技术有限公司 A kind of list mainboard multi version program adaptation method, system, device and storage medium
CN110162436A (en) * 2019-04-25 2019-08-23 深圳市同泰怡信息技术有限公司 A kind of normal mode and diagnostic mode switching method of BIOS POST
CN111858212A (en) * 2020-07-14 2020-10-30 深圳市同泰怡信息技术有限公司 Mainboard testing method, device, storage medium and equipment based on UEFI SHELL interface
CN111983437A (en) * 2020-08-25 2020-11-24 深圳市旗开电子有限公司 5G module product GPIO port test circuit and test method

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Publication number Priority date Publication date Assignee Title
CN107818032A (en) * 2017-10-24 2018-03-20 郑州云海信息技术有限公司 A kind of mainboard, information Method of printing, system, device and storage medium
CN108959169A (en) * 2018-06-26 2018-12-07 郑州云海信息技术有限公司 A kind of list mainboard multi version program adaptation method, system, device and storage medium
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CN110162436A (en) * 2019-04-25 2019-08-23 深圳市同泰怡信息技术有限公司 A kind of normal mode and diagnostic mode switching method of BIOS POST
CN111858212A (en) * 2020-07-14 2020-10-30 深圳市同泰怡信息技术有限公司 Mainboard testing method, device, storage medium and equipment based on UEFI SHELL interface
CN111983437A (en) * 2020-08-25 2020-11-24 深圳市旗开电子有限公司 5G module product GPIO port test circuit and test method
CN111983437B (en) * 2020-08-25 2023-09-08 深圳市旗开电子有限公司 5G module product GPIO port test circuit and test method

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Application publication date: 20121128