CN102779852B - SiC vertical double diffusion metal oxide semiconductor structure (VDMOS) device with composite gate dielectric structure - Google Patents

Abstract

A SiC VDMOS device with a composite gate dielectric structure belongs to the technical field of power semiconductor devices. According to the difference in electric field strength and defect density in different regions under the gate dielectric, the present invention adopts the idea of partition electric field modulation: high-k gate dielectric is used in the channel region with high defect density and low electric field, thereby avoiding the use of SiO ₂ A large number of trap states caused by the /SiC interface significantly reduces the influence of FN tunneling current, and at the same time, due to the relatively small electric field strength in the channel injection region, it weakens the gate dielectric breakdown caused by the small conduction band/valence band offset. The reduction of voltage; while the SiO ₂ gate dielectric is used in the JFET region with low defect density and high electric field (the JFET region is formed by epitaxy without ion implantation, the surface quality is good, and the SiO ₂ /SiC interface state is relatively low), and the SiO ₂ dielectric can Provide a sufficiently high conduction band offset to avoid premature breakdown of the gate dielectric.

Description

A SiC VDMOS device with composite gate dielectric structure

technical field

The invention belongs to the technical field of power semiconductor devices, and relates to a double diffused metal oxide semiconductor field effect transistor (DMOS) device structure, in particular to a silicon carbide (SiC) DMOS device with a composite gate dielectric structure. the

Background technique

Silicon carbide (SiC), as a wide-bandgap semiconductor material that has attracted much attention in recent years, has excellent physical properties such as wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. High power, high frequency, and strong irradiation fields have broad application prospects. the

Compared with gallium nitride (GaN) and other wide-bandgap semiconductor materials, SiC materials can directly generate silicon dioxide (SiO ₂ ) through thermal oxidation, which makes SiC an ideal material for making high-power MOSFET devices. The structure of a conventional SiC DMOS device is shown in Figure 1, and the device gate dielectric is SiO ₂ . However, due to the existence of a large number of traps at the SiC/SiO ₂ interface, this leads to low channel mobility and serious gate dielectric reliability problems in SiC DMOS devices. To solve this problem, the most commonly used method in the world is to perform gate oxidation or annealing in an atmosphere of nitrogen monoxide (NO) or nitrous oxide (N ₂ O) to remove the carbon residue at the interface, thereby Reduce interface traps, improve device inversion layer channel mobility and gate dielectric reliability. However, this method increases the fixed charge while reducing the interface state, which causes the threshold voltage shift of SiC DMOS devices. On the other hand, due to the difference in the dielectric constants of SiC and _SiO2 , according to Gauss's law, the electric field strength in oxide is about 3 times that in SiC. It is generally believed that the critical breakdown electric field of the SiC material close to the oxide layer is 2MV/cm, so the electric field strength in the oxide layer is as high as 6MV/cm, which causes the semiconductor material and the gate metal to inject electrons into the gate dielectric, resulting in Fowler-Nordheim (FN) Tunneling current leads to dielectric time-dependent breakdown (time-dependent dielectric breakdown, TDDB), which makes SiCDMOS devices face very serious gate dielectric reliability problems. For Si MOSFET devices, since the critical breakdown electric field of the Si material itself is an order of magnitude lower than that of the SiC material, the electric field strength in the gate dielectric is not large, and the reliability of the gate dielectric is not obvious.

Since the electric field strength in the gate dielectric is inversely proportional to the dielectric constant, and the FN tunneling current that affects the reliability of the gate dielectric is proportional to the electric field strength in the dielectric, it is replaced by a dielectric material with a high dielectric constant (high-k) The gate dielectric currently used is SiO ₂ , thereby reducing the electric field intensity in the dielectric layer, suppressing FN tunneling current, and improving the reliability of the gate dielectric. The structure of the high-k gate dielectric SiC DMOS device is shown in Figure 2. However, since the dielectric breakdown electric field and the conduction band/valence band offset of the high-k gate dielectric are smaller than those of SiO ₂ , using the high-k gate dielectric alone will reduce the breakdown voltage of the gate dielectric. Therefore, foreign researchers proposed a SiC DMOS device with a multilayer gate dielectric structure, as shown in Figure 3. First, a layer of SiO ₂ is thermally grown on the surface of SiC, and then a layer of high-k gate dielectric is deposited on the SiO ₂ layer. The multi-layer gate dielectric structure provides a sufficiently high conduction band offset through the SiO ₂ dielectric on the one hand, and reduces FN tunneling current through the high-k dielectric on the other hand. However, due to the many defects after surface ion implantation, there are still a large number of trap states at the SiO ₂ /SiC interface in the channel implantation region, which not only reduces the channel mobility, but also has a large number of SiC/SiO ₂ interface traps and high field The induced traps together form the FN tunneling current, and this gate structure can only partially alleviate the gate dielectric breakdown caused by the FN tunneling current.

Contents of the invention

The object of the present invention is to provide a SiC VDMOS device with a composite gate dielectric structure, which can effectively reduce the FN tunneling current of the device and improve the long-term reliability of the gate dielectric. the

The core idea of the present invention is to introduce a composite gate dielectric structure into the traditional SiC VDMOS device structure, mainly according to the difference in electric field strength and defect density in different regions under the gate dielectric layer, and adopt the idea of segmental electric field modulation. The high-k gate dielectric is used in the low electric field region, and the _SiO2 gate dielectric is used in the high electric field region, thereby reducing the electric field strength in the gate dielectric, reducing FN tunneling current, and improving the reliability of the gate dielectric.

Technical scheme of the present invention is as follows:

A SiC VDMOS device with a composite gate dielectric structure, its cell structure is shown in Figure 4, including: metal gate electrode 1, polysilicon gate 2, gate dielectric, metal source electrode 5, silicon carbide N ⁺ source region 6, carbonized Silicon P ⁺ contact region 7, silicon carbide P-base region 8, silicon carbide N ^– drift region 9, silicon carbide N ⁺ substrate 10, metal drain electrode 11; the cells are followed by metal drain electrode 11, carbide Silicon N ⁺ substrate 10, silicon carbide N ⁻ drift region 9; there is a silicon carbide P-base region 8 on both sides of the top of the silicon carbide Nˉ drift region 9, and each silicon carbide P-base region 8 has independent but The silicon carbide N ⁺ source region 6 and the silicon carbide P ⁺ contact region 7 are in contact with each other; on both sides of the cell surface are the metal source electrodes 5 that are in contact with both the silicon carbide N ⁺ source region 6 and the silicon carbide P ⁺ contact region 7, the element In the middle of the cell surface is the gate dielectric that is in contact with the SiC N ⁺ source region 6, the SiC P-base region 8 and the SiC Nˉ drift region 9; the surface of the gate dielectric is a polysilicon gate 2, and the surface of the polysilicon gate 2 is a metal gate electrode 1 . The gate dielectric is a composite gate dielectric structure, which is composed of a high dielectric constant (high-k) gate dielectric 3 and a SiO ₂ gate dielectric 4 . Among them, the SiO ₂ gate dielectric 4 covers the surface of the silicon carbide N ^- drift region 9 between the two silicon carbide P-base regions 8, that is, the surface of the JFET region of the device; and the high dielectric constant gate dielectric 3 covers the two silicon carbide The surface of the P-base region 8 is the surface of the channel region of the device. The dielectric constant of the high dielectric constant gate dielectric 3 is higher than that of SiO ₂ .

Working principle of the present invention:

The SiC VDMOS device with composite gate dielectric structure provided by the present invention adopts the idea of partition electric field modulation according to the difference in electric field strength and defect density in different regions under the gate dielectric: in the channel region with high defect density and low electric field, adopt high-k gate dielectric, thereby avoiding the use of a large number of trap states caused by the SiO ₂ /SiC interface, which significantly reduces the influence of FN tunneling current, and at the same time, due to the relatively small electric field strength in the channel injection region, it weakens the conduction band/valence The reduction of the breakdown voltage of the gate dielectric caused by the relatively small band offset; while the SiO ₂ gate dielectric is used in the JFET region with low defect density and high electric field (the JFET region is formed by epitaxy, without ion implantation, and the surface quality is good, SiO ₂ /SiC interface state is relatively low), the SiO ₂ dielectric can provide a sufficiently high conduction band offset, thereby avoiding the premature breakdown of the gate dielectric.

Description of drawings

Figure 1 is a schematic diagram of the traditional SiC VDMOS device structure. the

Figure 2 is a schematic diagram of the structure of a high-k gate dielectric SiC VDMOS device. the

Figure 3 is a schematic diagram of the structure of a multilayer gate dielectric SiC VDMOS device. the

Fig. 4 is a schematic structural diagram of a composite gate dielectric SiC VDMOS device provided by the present invention. the

Fig. 5 is a schematic diagram of an extended structure of a compound gate dielectric SiC VDMOS device structure provided by the present invention. the

In Figures 1 to 5: 1 is the metal gate electrode, 2 is the polysilicon gate, 3 is the high dielectric constant (high-k) gate dielectric, 4 is the SiO ₂ gate dielectric, 5 is the metal source electrode, and 6 is silicon carbide N ⁺ source region, 7 is the silicon carbide P ⁺ contact region, 8 is the silicon carbide P-base region, 9 is the silicon carbide N ^- drift region, 10 is the silicon carbide N ⁺ substrate, and 11 is the metal drain electrode.

Detailed ways

In order to make the technical solution to be explained in the present invention and the superiority of the present invention clearer, the specific implementation manners of the present invention will be described in detail below in conjunction with the accompanying drawings. The specific embodiments described here are only used to explain the present invention, not to limit the present invention. the

A SiC VDMOS device with a composite gate dielectric structure, its cell structure is shown in Figure 4, including: metal gate electrode 1, polysilicon gate 2, gate dielectric, metal source electrode 5, silicon carbide N ⁺ source region 6, carbonized Silicon P ⁺ contact region 7, silicon carbide P-base region 8, silicon carbide Nˉdrift region 9, silicon carbide N ⁺ substrate 10, metal drain electrode 11; cells from bottom to top are metal drain electrode 11, silicon carbide N ⁺ substrate 10, silicon carbide N ^- drift region 9; there is a silicon carbide P-base region 8 on both sides of the top of the silicon carbide N-drift region 9, and each silicon carbide P-base region 8 has mutually independent but mutually Contacted silicon carbide N ⁺ source region 6 and silicon carbide P ⁺ contact region 7; on both sides of the cell surface are metal source electrodes 5 that are in contact with both the silicon carbide N ⁺ source region 6 and the silicon carbide P ⁺ contact region 7, the cell In the middle of the surface is the gate dielectric in contact with the silicon carbide N ⁺ source region 6, the silicon carbide P-base region 8 and the silicon carbide N ^– drift region 9; the surface of the gate dielectric is a polysilicon gate 2, and the surface of the polysilicon gate 2 is a metal gate electrode 1 . The gate dielectric is a composite gate dielectric structure, which is composed of a high dielectric constant (high-k) gate dielectric 3 and a SiO ₂ gate dielectric 4 . Among them, the SiO ₂ gate dielectric 4 covers the surface of the silicon carbide N ^- drift region 9 between the two silicon carbide P-base regions 8, that is, the surface of the JFET region of the device; and the high dielectric constant gate dielectric 3 covers the two silicon carbide The surface of the P-base region 8 is the surface of the channel region of the device. The dielectric constant of the high dielectric constant gate dielectric 3 is higher than that of SiO ₂ .

In the above technical solutions, the composite gate dielectric structure may be implemented in different manners. for example:

1. First deposit SiO 2 gate dielectric 4 on the surface of the silicon carbide N ^- drift region 9 between the two silicon carbide P-base regions 8 (i.e., the surface of the JFET region of the device), and then deposit the _SiO2 gate dielectric 4 on the surface of the two silicon carbide P-base regions 8 A high dielectric constant gate dielectric 3 is deposited on the surface of the device (that is, the surface of the channel region of the device).

Two, first deposit SiO 2 gate dielectric 4 on the surface of the silicon carbide Nˉ drift region 9 between the two silicon carbide P-base regions 8 (that is, the surface of the JFET region of the device), and then deposit the SiO ₂ gate dielectric 4 on the surface of the two silicon carbide P-base regions 8 The surface (that is, the surface of the channel region of the device) and the surface of the SiO ₂ gate dielectric 4 are deposited with a high dielectric constant gate dielectric 3 (as shown in FIG. 5 ).

3. First, deposit a high dielectric constant gate dielectric 3 on the surface of the two silicon carbide P-base regions 8 (that is, the surface of the channel region of the device), and then deposit the silicon carbide between the two silicon carbide P-base regions 8 N ^- Deposit SiO 2 gate dielectric 4 on the surface of drift region 9 (that is, the surface of the JFET region of the device) and the surface of high dielectric constant gate dielectric ₃ .

All of the above three methods can realize the composite gate dielectric structure, and there is no obvious difference in the effect on SiC VDMOS devices. the

Claims (5)

1. a SiC VDMOS device with gate stack structure, its structure cell comprises: metal gate electrode (1), polysilicon gate (2), gate medium, source metal electrode (5), silicon carbide N ⁺source region (6), carborundum P ⁺contact zone (7), carborundum P-base district (8), carborundum N – drift region (9), silicon carbide N ⁺substrate (10), the metal leakage utmost point (11); Cellular is the metal leakage utmost point (11), silicon carbide N from the bottom up successively ⁺substrate (10), carborundum N – drift region (9); In both sides, top, carborundum N – drift region (9), there is respectively a carborundum P-base district (8), in each carborundum P-base district (8), there is silicon carbide N separate but that contact with each other ⁺source region (6) and carborundum P ⁺contact zone (7); Unit's cellular surface both sides are and silicon carbide N ⁺source region (6) and carborundum P ⁺the source metal electrode (5) that contact zone (7) all contacts, in the middle of first cellular surface is and silicon carbide N ⁺the gate medium that source region (6), carborundum P-base district (8) and carborundum N – drift region (9) all contact; Gate medium surface is polysilicon gate (2), and polysilicon gate (2) surface is metal gate electrode (1);

It is characterized in that, described gate medium is gate stack structure, by high-dielectric-coefficient grid medium (3) and SiO ₂gate medium (4) is composited; SiO wherein ₂gate medium (4) is covered in the surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. surface, the JFET district of device; And high-dielectric-coefficient grid medium (3) is covered in the surface in two carborundum P-base districts (8), the channel region of device is surperficial; The dielectric constant of described high-dielectric-coefficient grid medium (3) is higher than SiO ₂dielectric constant.

2. the SiC VDMOS device with gate stack structure according to claim 1, is characterized in that, described high-dielectric-coefficient grid medium (3) material is HfO ₂, Si ₃n ₄, TiO ₂, Al ₂o ₃or ZrO ₂.

3. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: the first surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. the JFET district surface deposition SiO of device ₂gate medium (4), then on the surface in two carborundum P-base districts (8), i.e. the channel region surface deposition high-dielectric-coefficient grid medium (3) of device.

4. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: the first surface, carborundum N – drift region (9) between two carborundum P-base districts (8), i.e. the JFET district surface deposition SiO of device ₂gate medium (4), then on the surface in two carborundum P-base districts (8), i.e. surface, channel region and the SiO of device ₂gate medium (4) surface deposition high-dielectric-coefficient grid medium (3).

5. the SiC VDMOS device with gate stack structure according to claim 1 and 2, it is characterized in that, the implementation of described gate stack structure is: first on the surface in two carborundum P-base districts (8), it is the channel region surface deposition high-dielectric-coefficient grid medium (3) of device, then the surface, carborundum N – drift region (9) between two carborundum P-base districts (8), the i.e. surface, JFET district of device and high-dielectric-coefficient grid medium (3) surface deposition SiO ₂gate medium (4).