CN102768819A - OLED real-time display drive control system and control method thereof - Google Patents

Abstract

The invention relates to an OLED (organic light emitting diode) real-time display driving control system which comprises a video decoding module, a video processor and a video memory. Video signals are inputted through an input end of the video decoding module, an output end of the video decoding module is connected with the video processor which is connected with the video memory, an output end of the video processor is connected with an OLED display module, an FPGA (field programmable gate array) serves as the video processor, and an SRAM (static random access memory) serves as the video memory. The control method of the OLED real-time display driving control system includes four portions of video decoding module initialization, video acquisition, video storage and video displaying, and the four portions are in cooperative operation under the control of the video processor to finally realize real-time display of video images on the OLED display module. The FPGA is used as the video processor while the SRAM is used as the video memory, data processing speed can be greatly increased by the aid of the control method, and the OLED real-time display driving control system has real-time processing and video image information storing capacities to enable the OLED to play dynamic video images in real time.

Description

OLED real-time display drive control system and control method thereof

technical field

The invention relates to a drive control system for controlling an OLED display device to perform real-time display and a control method adopted by the system.

Background technique

OLED (Organic Electroluminescent Diode) is an electroluminescent display device. The organic material is driven by the current flowing through the screen to produce a luminous effect, so it belongs to the current-driven light-emitting element. OLED technology is a new type of flat-panel display technology. Compared with the current mainstream flat-panel display technology LCD, OLED technology has the advantages of low energy consumption, large viewing angle, small size, fast response speed, full solid state, and wide operating temperature environment. , has been widely used in the field of digital display, and with the continuous improvement of theoretical research and continuous improvement of manufacturing technology, there is a tendency to replace LCD technology and become the mainstream technology of flat panel display.

The traditional OLED display driving control scheme uses a single-chip microcomputer as a microprocessor, and uses flash as an image information memory. The data processing speed of the single-chip microcomputer and the reading and writing speed of the flash are difficult to meet the requirements of high-speed video image processing, which causes OLED to play video images repeatedly, and cannot perform real-time dynamic playback.

Contents of the invention

The object of the present invention is to provide a driving control system capable of driving OLEDs for real-time display and a control method adopted by the system.

In order to achieve the above object, the technical scheme adopted in the present invention is:

An OLED real-time display driving control system, used to drive an OLED display module to realize real-time display, it includes a video decoding module, a video processor, a video memory, the video signal is input by the input terminal of the video decoding module, and the video The output end of the decoding module is connected with the video processor, the video memory is connected with the video processor, the output end of the video processor is connected with the OLED display module, and the Said video processor adopts FPGA, and said video memory adopts SRAM.

Preferably, the video storage includes two video storage modules, and the video storage modules are respectively connected to the video processor.

A control method of the above-mentioned OLED real-time display drive control system, which includes

(1) Video decoding module initialization: when the OLED real-time display drive control system is started, the video processor initializes and configures each register in the video decoding module;

(2) Video acquisition: After the initialization and configuration of the video decoding module is successful, if the video decoding module detects a video signal at its input end, the video decoding module will decode the video signal Output digital signal and several synchronous reference signals to described video processor behind, described video processor collects the image information of every frame image in described digital signal;

Described synchronous reference signal comprises parity field sign signal, field synchronous reference signal, line synchronous reference signal, pixel clock; Set described video decoding module to input in the digital signal of described video processor, every frame image The resolution is m×n; when collecting the image information of a frame of image, the high-level interval and the low-level interval of the odd-even field flag signal correspond to the odd-numbered field and the even-numbered field of a frame of image respectively. In the odd field or the even field, when the field synchronization reference signal is at a high level, the video processor collects the m/2 pixel rows in the odd field or the even field, The image data of n effective pixels in each pixel row; in each of the high-level effective intervals of the field synchronization reference signal, the horizontal synchronization reference signal has m/2 high-level effective intervals, And each of the high-level effective intervals of the horizontal synchronization reference signal includes n pixel clocks, and at the rising edge of each pixel clock, the video processor collects each effective pixel image data;

(3) Video storage: the video processor writes the collected image information into the video memory in units of frames; the resolution of each frame of image written into the video memory is a×b (a≤m, b≤n);

The storage space in the video memory is divided into at least a storage groups, each of which contains at least b storage units; when the write enable signal of the video memory is valid, each frame of image The image data of the effective pixels in the memory is written in the storage unit of the video memory, and when the write enable signal of the video memory is invalid, the video processor prepares the image of the effective pixels to be written next Data and the address of the corresponding storage unit in the video memory;

The address includes the group address of the storage group where the storage unit is located, and the unit address of the location of the storage unit in the storage group where it is located; The low bit address generated by the parity field flag signal through the inverter, in the effective interval of the field synchronization reference signal, the effective line counter starts counting on the rising edge of the line synchronization reference signal, and counts when it is full Cleared after a/2 numbers; the unit address is generated by the effective pixel counter, and in the effective interval of the horizontal synchronization reference signal, the effective pixel counter starts counting on the rising edge of the pixel clock , and cleared to zero after counting b numbers;

(4) Video display: After configuring the drive chip inside the OLED display module, the video processor reads the image information in the video memory and outputs it to the OLED display module for dynamic display. show.

Preferably, during the initialization process of the video decoding module, the video processor initializes and configures the registers in the video decoding module through the IIC bus; when each of the registers is initialized and configured, the The video processor first sends the start signal and then sends the address of the video decoding module, and when the video decoding module detects that the address sent by the video processor is the same as its own address, the video decoding module The module sends the first response signal, the video processor transmits the address of the register to be accessed after receiving the first response signal, and the video decoding module sends the second response after receiving the address of the register signal, the video processor transmits the data that needs to be written into the register after receiving the second response signal, and the video decoding module transmits the third response signal after receiving the data, the After receiving the third responder, the video processor sends a stop bit to end the data transmission.

Preferably, in the video acquisition process, a state machine is used to overall control the process; in the initial state, when the state machine detects that the parity field flag signal is low, it enters Second state; in the second state, when the state machine detects that the parity field flag signal is high, it enters the third state; in the third state, when When the state machine detects that the vertical synchronization reference signal is high level, it enters the fourth state; in the fourth state, when the horizontal synchronization reference signal is high level, the When the state machine detects that the field synchronization reference signal is low, it enters the fifth state; in the fifth state, when the state machine detects When the vertical synchronization reference signal is at a high level, it enters the sixth state; in the sixth state, the image information is collected when the horizontal synchronization reference signal is at a high level, and when When the state machine detects that the vertical synchronization reference signal is at low level, it returns to the initial state.

Preferably, when the resolution of each frame of image in the digital signal transmitted to the video processor by the video decoding module is greater than the resolution of each frame of image written in the video memory by the video processor When the resolution is high (that is, when a<m, b<n), the write enable signal of the video memory is controlled to divide the frequency of the pixel clock by x (x is a positive integer) to make the image of each frame The resolution is reduced from m×n to a'×b', where a'=(m/x), b'=(n/x); if a'>a, b'>b, extract each frame of image The first a row of pixel rows and the first b effective pixels in the a row of pixel rows are used to reduce the image resolution.

Preferably, when the video memory in the OLED real-time display drive control system includes two video storage modules, the image information of two adjacent frames of images is alternately stored in the two video storage modules , and alternately read the image information from the two video storage modules.

Preferably, configuring the drive chip inside the OLED display module includes specifying the data transmission format and transmission bit width of the OLED display module, specifying the image display start address and end address in the X direction, and specifying the image display in the Y direction. start address and end address.

Due to the use of the above-mentioned technical solutions, the present invention has the following advantages compared with the prior art: the present invention adopts FPGA as video processor, SRAM as video memory, and in combination with control method, can greatly improve data processing speed, and has real-time processing and storage The ability of video image information enables OLED to play dynamic video images in real time.

Description of drawings

Accompanying drawing 1 is the system frame diagram of OLED real-time display drive control system of the present invention.

Accompanying drawing 2 is the flow chart of video processor initialization configuration video decoding module register in the control method of OLED real-time display driving control system of the present invention.

Figure 3 is a diagram of the relationship between effective pixels and horizontal synchronization reference signals in the control method of the OLED real-time display drive control system of the present invention.

Figure 4 is a diagram of the relationship between effective pixels and pixel clock signals in the control method of the OLED real-time display drive control system of the present invention.

Figure 5 is a schematic diagram of the state of the state machine in the control method of the OLED real-time display drive control system of the present invention.

Accompanying drawing 6 is the timing diagram of writing SRAM in the control method of the OLED real-time display driving control system of the present invention.

Accompanying drawing 7 is the logical block diagram of the writing address signal generator of the video memory in the control method of the OLED real-time display driving control system of the present invention.

Fig. 8 is a display flowchart of the OLED display module in the control method of the OLED real-time display driving control system of the present invention.

Detailed ways

The present invention will be further described below in conjunction with the embodiments shown in the accompanying drawings.

Embodiment 1: an OLED real-time display driving control system, which is used to drive an OLED display module to realize real-time display. See attached drawing 1. It includes a video decoding module, a video processor, and a video memory, the video signal is input by the input end of the video decoding module, the output end of the video decoding module is connected with the video processor, the video memory is connected with the video processor, and the video processor The output end is connected with the OLED display module, the video processor adopts FPGA, and the video memory adopts SRAM. The video storage includes two video storage modules, the video storage modules are independent SRAMs, and the video storage modules are respectively connected with the video processor FPGA.

The control method of the above-mentioned OLED real-time display drive control system specifically includes four parts: video decoding module initialization, video acquisition, video storage, and video display. displayed in real time.

(1) Video decoding module initialization: When the OLED real-time display drive control system is powered on and started, the video processor FPGA initializes and configures each register in the video decoding module.

The decoding module adopts SAA7111A chip, which includes 32 registers inside, and each function of the chip is controlled by these 32 registers. During the initialization process of the video decoding module, the video processor FPGA initializes and configures the registers in the video decoding module through the IIC bus, the video processor FPGA acts as a master device, and the video decoding module acts as a slave device. IIC bus is composed of data line SDA and clock line SCL, and the data transfer rate is 100kbit/s in standard mode. When initializing and configuring each register, see Figure 2, the video processor FPGA first sends the start signal, and then sends the address of the video decoding module (including 7-bit address code and 1-bit W/R, here is 0x48H) , when the video decoding module detects that the address sent by the video processor FPGA is the same as its own address, the video decoding module sends the first acknowledgment signal ACK; the video processor FPGA transmits the address of the register that needs to be accessed after receiving the first acknowledgment signal ACK Address, the video decoding module sends the second response signal after receiving the address of the register; the video processor FPGA transmits the data that needs to be written into the register after receiving the second response signal, and the video decoding module transmits the third response signal after receiving the data, When the video processor FPGA receives the third response signal, it indicates that the transmission is successful, and then sends a stop bit to end the data transmission.

(2) Video capture: After the initial configuration of the video decoding module is successful, the video decoding module enters the working state. If the video decoding module detects the PAL analog video signal at its input end, the video decoding module outputs digital signals in RGB format and several synchronous reference signals to the video processor FPGA after its internal AD conversion and decoding processing. In order to accurately extract the image information of each frame of image, the synchronization reference signal includes parity field mark signal RTS0, field synchronization reference signal VREF, horizontal synchronization reference signal HREF, and pixel clock LLC2, wherein the frequency of pixel clock LLC2 is 13.5MHz.

It is set that the video decoding module inputs the digital signal to the video processor FPGA, and the resolution of each frame of image is m×n. In this embodiment, the resolution is 576×720 as an example. The video processor FPGA collects the image information of each frame image in the digital signal. When collecting the image information of a frame of image, referring to the accompanying drawings 3 and 4, the high-level interval and the low-level interval of the parity field flag signal RTS0 correspond to the odd field and the even field of a frame of image respectively, and its rise The edge indicates the start of a frame of image. In odd or even fields, when the field synchronization reference signal VREF is at a high level, the video processor FPGA collects m/2 pixel rows (that is, 288 pixel rows) in odd or even fields, and n effective pixels (that is, 720 effective pixels per line), and the low level of the field synchronization reference signal VREF corresponds to the field blanking period. Specifically, in the high-level effective intervals of each vertical synchronization reference signal VREF, the horizontal synchronization reference signal HREF has m/2 (that is, 288) high-level effective intervals, corresponding to odd fields or even fields m/2 (that is, 288) pixel rows, and the low level of the row synchronization reference signal HREF corresponds to the row blanking period. At the same time, in the high-level effective interval of each line synchronization reference signal HREF, n (ie 720) pixel clocks are included, and on the rising edge of each pixel clock, the video processor FPGA collects the image data of each effective pixel , so as to collect the image information of each frame of image.

In the above-mentioned image acquisition process, the most important thing is to accurately determine the start and end time of each frame of image information, so the state machine is used to control the process as a whole. Referring to Figure 5, in the initial state, when the state machine detects that the parity field flag signal RTS0 is low (RTS0=0), it enters the second state; in the second state, when the state machine detects When the parity field flag signal RTS0 is high level (RTS0=1), it means that a new frame of image starts, and then it enters the third state; in the third state, when the state machine detects that the field synchronization reference signal VREF is high level ( When VREF=1), it means that the image data of the first field is coming soon, and then it enters the fourth state; in the fourth state, the image information is collected when the line synchronization reference signal HREF is high level (HREF=1), When the state machine detects that the field synchronization reference signal VREF is low (VREF=0), it means that the first field of image data is over, and then it enters the fifth state; in the fifth state, when the state machine detects the field synchronization reference signal VREF When it is high level (VREF=1), it indicates that the second field image data is coming, and then it enters the sixth state; in the sixth state, when the horizontal synchronization reference signal HREF is high level (HREF=1) The image information is collected. When the state machine detects that the field synchronization reference signal VREF is low (VREF=0), it means that the second field of image data is over, and then it returns to the initial state to prepare for the detection of the next frame of image information. Through these six states, you can accurately know the start and end moments of a frame of image, and prepare for the accurate reproduction of the image in the future.

(3) Video storage: The video processor FPGA writes the image information collected by it into the video memory SRAM in units of frames. Set the resolution of each frame of image written into the video memory SRAM as a×b (a≤m, b≤n). In this embodiment, a progressive scan OLED display module with a resolution of 128×160 is used, therefore, the resolution of each frame of image written into the video memory SRAM is 128×160. At this time, it is necessary to perform resolution reduction processing on each frame of image when writing data.

Referring to FIG. 6 , A[14:0] is the address line of the video memory SRAM, and DATA[15:0] is the data line of the video memory SRAM. The video memory SRAM samples the data DATA[15:0] at the rising edge of the write enable signal WE, so the video processor FPGA prepares the data and its corresponding address at the falling edge of the write enable signal WE. The write enable signal WE that controls the video memory SRAM is divided by x of the pixel clock LLC2 (x is a positive integer) to reduce the resolution of each frame of image from m×n to a'×b', where a'=(m /x), b'=(n/x). In this embodiment, the write enable signal WE is divided by four of the pixel clock LLC2, that is, one pixel is taken for every four pixels. On this basis, one pixel row is taken for every four pixel rows, and the resolution of the image can be made The resolution is reduced from 576×720 to 255×180. The resolution of the image obtained at this time is still greater than the resolution of the OLED display module, therefore, further resolution reduction processing is required. At this time, extract the first a row of pixels of each frame image, the first b effective pixels in the a row of pixels, that is, extract the first 128 pixel rows of each frame of image, the first 160 effective pixels of each pixel row, The resolution of the image is further reduced to 128×160 of the resolution of the OLED display module, thereby reducing the resolution of the image.

When writing SRAM, since the image data of the digital signal output by the video decoding module adopts an interlaced scanning method, the pixel row of odd-numbered field scanning is 0, 2, 4, 6, ..., 126 rows, and the pixel row of even-numbered field scanning is 1st, 3, 5, 7, ..., 127 lines, and the OLED used in this system is a progressive scanning format, so the interlaced image data must be deinterlaced to meet the requirements of the OLED display module, which requires attention when writing The generation mechanism of the address signal.

The storage space in the video memory SRAM is divided into at least a storage groups, and each storage group contains at least b storage units. When the write enable signal WE of the video memory SRAM was effective, the image data of the effective pixels in each frame of image was written in the storage unit of the video memory SRAM in turn; when the write enable signal WE of the video memory SRAM was invalid, the video processor The FPGA prepares the image data of the next effective pixel to be written and the address of the corresponding storage unit in the video memory SRAM.

The address includes a group address for locating the storage group where the storage unit is located, and a unit address for locating the location of the storage unit in the storage group where the storage unit is located, wherein the group address is the high bit in the address, and the unit address is the low bit in the address. Referring to FIG. 7, the group address includes the high address generated by the effective row counter and the low address generated by the parity field flag signal RTS0 through the inverter. In the effective interval of the vertical synchronization reference signal VREF (VREF=1), the effective row counter starts counting on the rising edge of the horizontal synchronization reference signal HREF, and is cleared after counting a/2 counts. In this way, combined with the low address generated by the field synchronization reference signal VREF passing through the inverter, it can be ensured that the data written during the odd field is located in the 0th, 2nd, 4th, 6th, ..., (a-2) of the storage space In the storage group, the data written during the even field period is located in the 1st, 3rd, 5th, 7th, ..., (a-1) storage groups in the storage space. The unit address is generated by the effective pixel counter. In the effective interval of the horizontal synchronization reference signal HREF (HREF=1), the effective pixel counter starts counting on the rising edge of the pixel clock LLC2, and is cleared after counting b.

In combination with this embodiment, the video memory SRAM adopts a chip with a capacity of 256k×16Bit and a maximum access speed of 100MHz. The size of the image displayed by the OLED display module is 20k×16 Bit. Take out the storage space of 32k in the video memory SRAM, divide it into 128 storage groups, and each storage group allocates 256 storage units. When storing, a row of pixels of the OLED display module corresponds to a storage group of the video memory SRAM. To realize the conversion from interlaced to progressive, it is only necessary to store the 64 lines of image data collected during the odd field into storage groups 0, 2, 4, ..., 126 in sequence, and store the 64 lines of image data collected during the even field into In the 1st, 3rd, 5th, ..., 127th storage groups, like this, the image data of the 0-127th storage groups in the video memory SRAM is just corresponding to the 0th-127th line of a frame image, constitutes a complete step-by-step line scan image. The 256 storage units in each storage group only occupy 160, although it is a bit wasteful, but after such processing, the de-interlacing circuit structure is greatly simplified.

The storage unit is located by the address line A[14:0], where A[14:8] is the group address, which locates the storage group where the storage unit is located, and A[7:0] is the unit address, which locates the storage unit where it is located. The location in the storage group. When the vertical synchronization reference signal VREF is high level (VREF=1), the effective line counter starts counting on the rising edge of the horizontal synchronization reference signal HREF, and generates the upper 6 bits A[14:9 of the write address signal of the video memory SRAM ], when 64 pixels are counted, the effective line counter is cleared. When the horizontal synchronization reference signal HREF is high level (HREF=1), the effective pixel counter starts counting on the rising edge of the pixel clock LLC2, and generates the lower 8 bits A[7:0] in the write address signal of the video memory SRAM , when 160 pixels are counted, the effective pixel counter is cleared. A[8] used as the video memory SRAM write address signal after inverting the parity field flag signal RTS0 ensures that the storage unit of the data written during the odd field is located in the 0th, 2, 4, ..., 126 storage groups, The memory cells of data written during the even field are located in the 1st, 3rd, 5th, . . . , 127th memory groups.

In order to solve the conflict of writing the processed image data into the video storage module and obtaining image data from the video storage module, the video memory SRAM of this system uses two physically independent SRAM video storage modules to store two adjacent frames of images. The two video storage modules are alternately in the state of being written and being read, that is, the image information of two adjacent frames of images is alternately stored in the two modules, and the image information is alternately read out from the two image processing modules. The specific implementation process is as follows: the first video storage module stores the first frame image in the first frame image acquisition cycle, outputs the first frame image in the second frame image acquisition cycle, and stores the third frame image in the third frame image acquisition cycle. frame image, output the third frame image in the fourth frame image acquisition cycle, and so on. The second video storage module starts working when the second frame image arrives, stores the second frame image in the second frame image acquisition cycle, outputs the second frame image in the third frame image acquisition cycle, and outputs the second frame image in the fourth frame image acquisition cycle. The fourth frame of image is stored in the image acquisition period, the fourth frame of image is output in the fifth frame of image acquisition period, and so on. In this way, a double-frame switching mechanism is realized. Although this method delays the captured image by one frame before being displayed, it will not miss any frame of image information.

(4) Video display: The OLED display module uses a color display device, and its internal drive chip makes the interface with the video processor FPGA relatively simple. First configure the driver chip inside the OLED display module, including specifying the data transmission format and transmission bit width of the OLED display module, specifying the image display start address and end address in the X direction, and specifying the image display start address and end address in the Y direction address. After configuration, the video processor FPGA reads the image information in the video memory SRAM and outputs it to the OLED display module for dynamic display. The process is shown in Figure 8.

The OLED real-time display driving control system and its control method have the following advantages:

(1) The structure is simple, the cost is low, and it is easy to implement.

As for how to realize the acquisition and display of analog video signals, the traditional solution uses a large number of analog discrete components, which is not only complicated, but also difficult to debug. The invention adopts integrated circuit design, has few peripheral analog devices, small volume and simple structure. The general-purpose component design is adopted, and the components used are easy to purchase, low in cost, and easy to implement.

(2) Flexible to use and easy to modify.

Corresponding software can be customized according to user requirements. For example, to change the image display mode, parameters such as image brightness, contrast, screen width, and display direction can be adjusted by modifying the configuration of the video decoder chip and OLED.

(3) The real-time online playback of video signals is realized.

Since FPGA is a hardware circuit, its working nature is similar to multi-threaded operation in programming, and the processing of data is carried out in parallel, and it has the ability to process high-speed video image data. The invention realizes the real-time collection and display of video signals, so that the OLED display module can display images at a speed of 25 frames per second, and the picture is clear and smooth.

The above-mentioned embodiments are only to illustrate the technical concept and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and not to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention shall fall within the protection scope of the present invention.

Claims (8)

1. A OLED real-time display drive control system, used to drive the OLED display module to realize real-time display, it includes a video decoding module, a video processor, a video memory, and the video signal is input by the input terminal of the video decoding module, and the The output end of the video decoding module is connected with the video processor, the video memory is connected with the video processor, and the output end of the video processor is connected with the OLED display module , it is characterized in that: described video processor adopts FPGA, and described video memory adopts SRAM. 2 . The OLED real-time display driving control system according to claim 1 , wherein the video memory includes two video storage modules, and the video storage modules are respectively connected to the video processor. 3 . 3. A control method of the OLED real-time display drive control system according to claim 1, characterized in that: it comprises (1) Video decoding module initialization: when the OLED real-time display drive control system is started, the video processor initializes and configures each register in the video decoding module; (2) Video acquisition: After the initialization and configuration of the video decoding module is successful, if the video decoding module detects a video signal at its input end, the video decoding module will decode the video signal Output digital signal and several synchronous reference signals to described video processor behind, described video processor collects the image information of every frame image in described digital signal; Described synchronous reference signal comprises parity field sign signal, field synchronous reference signal, line synchronous reference signal, pixel clock; Set described video decoding module to input in the digital signal of described video processor, every frame image The resolution is m×n; when collecting the image information of a frame of image, the high-level interval and the low-level interval of the odd-even field flag signal correspond to the odd-numbered field and the even-numbered field of a frame of image respectively. In the odd field or the even field, when the field synchronization reference signal is at a high level, the video processor collects the m/2 pixel rows in the odd field or the even field, The image data of n effective pixels in each pixel row; in each of the high-level effective intervals of the field synchronization reference signal, the horizontal synchronization reference signal has m/2 high-level effective intervals, And each of the high-level effective intervals of the horizontal synchronization reference signal includes n pixel clocks, and at the rising edge of each pixel clock, the video processor collects each effective pixel image data; (3) Video storage: the video processor writes the collected image information into the video memory in units of frames; the resolution of each frame of image written into the video memory is a×b (a≤m, b≤n); The storage space in the video memory is divided into at least a storage groups, each of which contains at least b storage units; when the write enable signal of the video memory is valid, each frame of image The image data of the effective pixels in the memory is written in the storage unit of the video memory, and when the write enable signal of the video memory is invalid, the video processor prepares the image of the effective pixels to be written next Data and the address of the corresponding storage unit in the video memory; The address includes the group address of the storage group where the storage unit is located, and the unit address of the location of the storage unit in the storage group where it is located; The low bit address generated by the parity field flag signal through the inverter, in the effective interval of the field synchronization reference signal, the effective line counter starts counting on the rising edge of the line synchronization reference signal, and counts when it is full Cleared after a/2 numbers; the unit address is generated by the effective pixel counter, and in the effective interval of the horizontal synchronization reference signal, the effective pixel counter starts counting on the rising edge of the pixel clock , and cleared to zero after counting b numbers; (4) Video display: After configuring the drive chip inside the OLED display module, the video processor reads the image information in the video memory and outputs it to the OLED display module for dynamic display. show. 4. The control method of the OLED real-time display drive control system according to claim 3, characterized in that: in the initialization process of the video decoding module, the video processor passes the IIC bus to the video decoding module. The registers are initialized and configured; when each of the registers is initialized, the video processor first sends the start signal and then sends the address of the video decoding module, and the video decoding module detects the When the address sent by the video processor is the same as its own address, the video decoding module sends the first response signal, and the video processor transmits the address of the register to be accessed after receiving the first response signal , the video decoding module sends a second response signal after receiving the address of the register, and the video processor transmits the data that needs to be written into the register after receiving the second response signal, The video decoding module transmits a third response signal after receiving the data, and the video processor sends a stop bit to end data transmission after receiving the third response signal. 5. the control method of OLED real-time display driving control system according to claim 3 is characterized in that: in described video collection process, adopt state machine to carry out overall control to this process; Under initial state, when described When the state machine detects that the parity field flag signal is low, it enters the second state; in the second state, when the state machine detects that the parity field flag signal is high level, it enters the third state; in the third state, when the state machine detects that the field synchronization reference signal is high, it enters the fourth state; in the In the fourth state, the image information is collected when the horizontal synchronization reference signal is at a high level, and when the state machine detects that the vertical synchronization reference signal is at a low level, it enters the first Five states; in the fifth state, when the state machine detects that the field synchronization reference signal is high, it enters the sixth state; in the sixth state, in the When the horizontal synchronization reference signal is at a high level, the image information is collected, and when the state machine detects that the vertical synchronization reference signal is at a low level, it returns to the initial state. 6. The control method of the OLED real-time display driving control system according to claim 3, characterized in that: when the resolution of each frame image in the digital signal transmitted to the video processor by the described video decoding module is greater than When the resolution of each frame of image in the video memory is written by the video processor (that is, when a<m, b<n), the write enable signal of the video memory is controlled to be the The pixel clock is divided by x (x is a positive integer) to reduce the resolution of the image described in each frame from m×n to a'×b', where a'=(m/x), b'=(n /x); if a'>a, b'>b, extract the first a row of pixels in each frame image, and the first b effective pixels in the a row of pixels to reduce the image resolution. 7. The control method of the OLED real-time display driving control system according to claim 3, characterized in that: when the video memory in the OLED real-time display driving control system comprises two described video storage modules The image information of two adjacent frames of images is alternately stored in the two video storage modules, and the image information is alternately read out from the two video storage modules. 8. The control method of the OLED real-time display drive control system according to claim 3, characterized in that: configuring the drive chip inside the OLED display module includes specifying the data transmission format and transmission bit width of the OLED display module , Specify the image display start address and end address in the X direction, and specify the image display start address and end address in the Y direction.

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