CN102708264B - Honeycomb hexagonal field programmable gata array (FPGA) structure - Google Patents

Abstract

The invention belongs to the technical field of programmable logic devices, in particular to a honeycomb hexagonal field programmable logic array (FPGA) structure. The FPGA array of the present invention is composed of hexagonal units, and the basic logic unit structure is hexagonal, which is a completely symmetrical structure and is convenient for physical realization when the array is expanded. Programmable wiring resources have a three-axis structure and are distributed in three diagonal directions (0 degrees, 120 degrees, 240 degrees). The wiring resource structure can be divided into double lines, five times lines and long lines according to the length of the interconnection lines. Interconnecting lines of two times the line and five times the line can be connected to each unit of a ring at a corresponding distance, and the long line is a point connection structure, distributed in three axis directions, and a straight line connection with a distance of 12 can be realized. The interconnection structure of the present invention has torus connection characteristics, evenly distributed connection lines, high utilization rate and fast speed, and is beneficial to improving logic density and timing performance.

Description

A Honeycomb Hexagonal Field Programmable Logic Array Structure

technical field

The invention belongs to the technical field of programmable devices, and in particular relates to a field programmable device structure.

Background technique

A field programmable logic device (FPGA) consists of a programmable logic block (PLB) and a programmable interconnect, and the programmable logic block is connected through a programmable interconnect. In large-scale FPGA chips, wiring resources account for more than 70% of the chip area, and interconnection delays also account for more than 70% of the overall delay. Therefore, the performance of wiring resources largely determines the performance of FPGA devices. Traditional programmable interconnect resources are usually planar structures composed of horizontal interconnect resources and vertical interconnect resources [1-2], which are connected to each other through a switch matrix, as shown in Figure 1. As the scale of FPGA becomes larger and larger, the interconnection resources of the traditional planar structure restrict the improvement of FPGA scale and speed.

This is because the traditional interconnection structure divides interconnection resources into horizontal interconnection resources and vertical interconnection resources, and the two logic units interconnected in the application are often not on a horizontal or vertical line, so regardless of the two How close the logic unit is, at least one programmable switch is required to connect the two logic units, which has a great impact on the speed of the FPGA.

In order to solve this problem, literature [3] proposed a 45-degree wiring resource type, but this is only a simple extension of the traditional structure. In the industry, XILINX proposed the concept of direct interconnection [1] (direct connection) in the VIRTEX-II chip. The main idea is to add an interconnection resource called direct interconnection, which can directly connect 8 chips next to a logic unit. A logic unit, as shown in Figure 2, does not need to go through a programmable switch, which can speed up the speed of some adjacent distance connections, but it is still powerless for other longer connections.

In the recent VIRTEX-5 chip, part of the 5x line of XILINX adopts the inflection line structure [4] (also called hard wired, hard wired), as shown in Figure 3, the 5x line output by unit 1 can respectively reach Unit 2, 3, 4, 5, 6 and other 5 positions with equal distances, among which unit 6 and unit 1 are in the same vertical channel, the number of connecting lines is 12, and the number of connecting lines in other positions is 3. This 5-fold line inflection structure speeds up the speed of medium-distance links, but this kind of inflection line is only a minority in VIRTEX-5, and its main structure is still based on the horizontal and vertical channel structure, which is essentially a channel-based interconnection structure.

references:

[1] V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs [M], Kluwer Academic Publishers, 1999.

[2] Ian Kuon, Russell Tessier, and Jonathan Rose, "FPGA Architecture: Survey and Challenges", Now Publishers Inc, 2008

[3] Sumanta Chaudhuri, "Diagonal Tracks in FPGAs: A Performance Evaluation", International Symposium on Field Programmable Gate Arrays 2009, p245-248

[4] Xilinx, Inc., Virtex/Virtex-II/Virtex-4/Virtex-5/Spartan/Spartan-II/Spartan-3 FP-GA Family Complete Data Sheet.

[5] Altera Corp., Stratix/Stratix-II/Stratix-III/Cyclone/Cyclone-II Device Handbook.

[6] David Lewis, "The Stratix II logic and routing architecture", 13th international symposium on Field-programmable gate arrays 2005, P14-20.

Contents of the invention

Aiming at the deficiency of the traditional structure, the present invention proposes a hexagonal honeycomb field programmable logic array structure based on torus connection. The wiring distribution of the structure is uniform, the utilization rate is high, and the speed is fast, which is beneficial to improving logic density and timing performance.

The cellular hexagonal field programmable logic (FPGA) array structure based on torus connection proposed by the present invention is composed of programmable logic block (PLB) and programmable connection resources, as shown in Figure 4, the interconnection structure is as follows :

Hexagonal : The basic programmable logic block (PLB) unit is a honeycomb hexagonal structure, and the FPGA array is composed of several hexagonal PLB units.

Three-axis : Programmable wiring resources are distributed in three diagonal directions: 0°, 120°, and 240°, which are recorded as X, Y, and Z in turn; wiring resources are distributed in each axis; for example Shown by dotted line X Y Z in Fig. 4.

Hierarchical interconnection : Programmable routing resources are composed of three types of connection resources: double line, five times line and long line:

In the quadrilateral array structure, the distance between two units defines the shortest distance between two units along the connection direction, that is, the sum of the length and width of the rectangle with these two units as the diagonal. Similarly, the distance between any two cells in the hexagonal array is also defined as the shortest distance along the three symmetry axes.

The double line can realize the connection between two units with a distance of 1 and 2 in any direction; the five times line can realize the connection between two units with a distance of 5 in any direction; the long line can realize any two units on the same axis Connections between cells with a distance of 12.

Torus connection : Starting from any PLB, the double line and the five-time line can be connected to each unit of a ring with a distance of 2 or 5 from it.

Symmetrical structure : This structure is a completely symmetrical (centrosymmetric) structure, which is convenient for physical realization when the array is expanded.

The global wiring resources described in the present invention have the characteristics of torus connection:

(1) In traditional programmable logic devices, the interconnection lines are only connected to several points on the straight line. In the present invention, a certain type of interconnection lines from one PLB can be connected to all PLBs on a ring, as shown in Figure 4.

(2) Interconnection lines of different lengths form multiple achievable interconnection rings.

(3) An interconnection line can be deflected by 60 degrees at different positions to reach the interconnection ring.

(4) There may be different connections from one PLB to the same PLB on the interconnection ring, as shown in Figure 4.

The hexagonal PLB represents a logical unit, arranged in a honeycomb hexagonal structure. As an example, the dark gray mark PLB is used as the center point in the figure, and the thin solid line indicates the connection between PLBs. It can be seen from the figure that the central PLB can be directly connected to all gray PLBs and light gray PLBs, through double lines And the five-fold line, the central PLB can be connected to all the PLBs on the three rings 1, 2, and 5 centered on it, so this structure is a ring-connected structure. At the same time, the long lines are distributed in the three directions of X\Y\Z like the traditional FPGA, and the number of long lines is distributed axisymmetrically in the three directions of XYZ, so it is a three-axis structure.

Description of drawings

Figure 1 shows the traditional FPGA routing resource structure.

Figure 2 direct interconnection line structure.

Figure 3 shows the structure of the VIRTEX-5 inflection line.

Figure 4 shows the hexagonal routing resource structure proposed in this paper.

Detailed ways

The wiring resource structure of the present invention can be divided into three types of connection resources according to the length of the interconnection line: the double line, the five-fold line and the long line. The double line can realize the connection between two units with a distance of 1 and 2 in any direction. connect. The fivefold line can realize the connection between two units with a distance of 5 in any direction. The long line can realize the connection between any two units with a distance of 1 and 2 on the same axis. Each hexagonal unit has 6 sides. In order to effectively distinguish the interconnection lines, the interconnection lines can be considered to start from one side of the central PLB and terminate at one side of another PLB.

The double line is to connect two PLBs with a distance of 2. At the same time, the double line has a middle tap, and can also be connected to two adjacent PLBs on the passing path. Therefore, all the double lines starting from the central PLB are connected to the distance All PLBs on the two rings for 1 and 2.

The fivefold line connects two PLBs with a distance of 5. The fivefold line starting from the central PLB turns 60 degrees after passing through different distances and connects to different PLBs on the ring with a distance of 5.

From the starting point and end point of the connection, the connection starts from the 6 sides of the central PLB and terminates with the inner side of the ring. Therefore, the number of connections originating from the central PLB is proportional to the perimeter of the ring and the channel width, which refers to the number of connections of the same kind with the same origin and termination point. The double line terminates inside the 2nd ring, and there are 18 sides in total inside the 2nd ring, so when the channel width is 1, the minimum number of 2x lines is 18; similarly, the quintuple line terminates inside the 5th ring, and there are a total of 18 sides inside the 5th ring. 72 sides, so when the channel width is 1, the minimum number of 5 times lines is 72;

The length of the long line is 12, and the long line is only available in the three axis directions. The long line does not turn, and only connects two PLBs on the same axis.

From the perspective of functional distinction, the long line is responsible for the long-distance backbone connection, and the load must be small and the speed fast; the five-fold line and the two-fold line are used as local short-circuit connections. With the point connection structure of the vertical channel, the signals connected at any position can reach the destination through relatively few switches, thereby improving the timing performance.

Claims (2)

1. A Field Programmable Logic Device array structure is characterized in that it is made of programmable logic blocks and programmable connection resources; wherein, each PLB unit is a honeycomb regular hexagonal structure, and the FPGA array is made of some PLB units, And it is a centrally symmetrical structure; Programmable wiring resources are distributed in three diagonal directions: 0°, 120°, and 240°, which are recorded as X, Y, and Z in turn; wiring resources are distributed in both directions of each axis ; Programmable connection resources are composed of three connection resources: double line, five times line and long line, among which: The double line realizes the connection between two PLB units with a distance of 1 and 2 in any direction; the five times line realizes the connection between two PLB units with a distance of 5 in any direction; the long line realizes the connection between any two distances on the same axis It is the connection between 12 PLB units, forming a hierarchical interconnection; Starting from any PLB unit, the double line and five times line are connected to each unit of a ring with a distance of 2 or 5 from the PLB unit, forming a ring connection; Among them, the symbol FPGA is a field programmable logic device, and the PLB is a programmable logic block. 2. the field programmable logic device array structure according to claim 1, is characterized in that: Through double lines, each PLB unit is connected to 6 adjacent PLB units with a distance of 1, and to 12 PLB units with a distance of 2; through five times lines, each PLB unit is connected to 30 adjacent PLB units with a distance of 5 The PLB units are connected, and the long lines connect the three PLB units with a distance of 12 on the axis.