CN102683368B - Complementary metal oxide semiconductor (CMOS) imaging sensor and producing method thereof - Google Patents

Abstract

The invention relates to a CMOS image sensor and a manufacturing method thereof. The CMOS image sensor includes: a semiconductor substrate including a first active region, wherein the first active region includes a photodiode, a transistor, and a second active region, wherein the second active region Adjacent to the well of the photodiode and having the same conductivity type as the well of the photodiode, the second active region is connected to a reference potential, wherein the second active region and the well of the photodiode Formed by one ion implantation.

Description

CMOS image sensor and manufacturing method thereof

technical field

The present invention relates to image sensors, and in particular to a CMOS image sensor and a manufacturing method thereof.

Background technique

Compared with CCD (Charge Coupled Device), CMOS image sensor has the advantages of high integration, low power consumption and low cost, and has been more and more widely used. Its photosensitive unit, that is, the pixel, is used to complete photoelectric conversion, which plays a decisive role in the quality of the image.

The most common pixel structures are 3T and 4T. Figures 1 and 2 show a pixel with a 4T structure. As shown in FIG. 1 , a photodiode 11 , a transfer transistor 12 , a reset transistor 13 , a source follower transistor 14 , and a row gate transistor 15 are fabricated in the active region. Wherein, the photodiode 11 is used to convert the light signal into an electric signal, so as to achieve the purpose of light sensing. Specifically, the photodiode 11 generates photocarriers under the irradiation of incident light. When the transfer transistor 12 is turned on, the electrons are collected by the floating diffusion region FD, and at the same time, the source of the source follower transistor 14 follows the change of the gate voltage, and the gate voltage The change in is read when the row gate transistor 15 is turned on, thereby generating an electrical signal. The floating diffusion FD can be reset by turning on the reset transistor 13 .

However, in the existing pixel structure, when the photodiode 11 is irradiated by strong light, photo-generated carriers exceeding the well capacity will overflow to adjacent pixels, resulting in image crosstalk or halo.

Aiming at this problem, one solution is to make the potential barrier between the photodiode 11 and the floating diffusion region FD lower, so that the overflowed electrons are easily pulled to the floating diffusion region FD.

However, there is still a need for other techniques for mitigating or eliminating image crosstalk or halos.

Contents of the invention

One problem with the aforementioned method of lowering the potential barrier between the photodiode 11 and the floating diffusion FD is that usually the photodiode 11 and the floating diffusion FD are defined by different photolithographic steps, and therefore, the entire sensor As far as the chip surface is concerned, the distance between the photodiode 11 and the floating diffusion region FD of different pixels is not uniform, resulting in uneven effects of lateral overflow drain among different pixels.

According to one aspect of the present invention, a CMOS image sensor is provided, including: a semiconductor substrate including a first active region, wherein the first active region includes a photodiode, a transistor, and a second active region , wherein the second active region is adjacent to the well of the photodiode and has the same conductivity type as the well of the photodiode, the second active region is connected to a reference potential, wherein the second The active region and the well of the photodiode are formed by one ion implantation.

In one example, the first active region further includes at least two lateral doped regions having the same conductivity type as the first active region, located between the well of the photodiode and Between the second active regions, the width of the lateral doped region is equal to or greater than the width of the gap between the well of the photodiode and the second active region.

In one example, the at least two lateral doped regions cover adjacent corners of the well and adjacent corners of the second active region.

In one example, the first active region further includes a first vertical doped region, the first vertical doped region has the same conductivity type as the first active region, and is located below the gap, Adjacent corners of the well and adjacent corners of the second active region are covered.

In one example, the first active region further includes a second vertical doped region, the second vertical doped region has the same conductivity type as the first active region, and is located above the gap, Adjacent corners of the well and adjacent corners of the second active region are covered.

In one example, the first active region further includes at least one vertical doped region having the same conductivity type as the first active region, located between the well of the photodiode and the Below the gap between the second active regions, covering adjacent corners of the well and adjacent corners of the second active region.

In one example, the first active region includes two photodiodes, and the second active region is located between wells of the two photodiodes.

In one example, the first active region further includes a heavily doped region connected to the second active region, the heavily doped region having the same conductivity type as the second active region.

According to another aspect of the present invention, there is provided a method for manufacturing the CMOS image sensor of the present invention, comprising the following steps: forming a first active region on a semiconductor substrate; simultaneously forming a photoelectric sensor in the first active region A well of the diode and a second active region adjacent to the well; forming an electrical connection of the second active region to a reference potential.

In one example, the well of the photodiode and the second active region are formed by ion implantation.

In one example, the method further includes: simultaneously forming at least two lateral doped regions in the first active region, wherein the lateral doped regions have the same conductivity as that of the first active region. Type, located between the well of the photodiode and the second active region, the width of the lateral doped region is equal to or greater than the gap between the well of the photodiode and the second active region width.

In one example, the method further includes forming a first vertical doped region in the first active region, wherein the first vertical doped region has the same conductivity type as the first active region , located below the gap, covering adjacent corners of the well and adjacent corners of the second active region.

In one example, the method further includes forming a second vertical doped region in the first active region, wherein the second vertical doped region has the same conductivity type as the first active region , located above the gap, covering adjacent corners of the well and adjacent corners of the second active region.

Description of drawings

Embodiments of the present invention can be better understood with reference to the following figures. Parts in the drawings are not necessarily drawn to scale:

FIG. 1 is a top view of a pixel with a 4T structure;

Fig. 2 is a cross-sectional view of the 4T structure pixel in Fig. 1 along the direction indicated by the arrow;

Figure 3a is a schematic diagram of pixels according to an embodiment of the CMOS image sensor of the present invention;

Figure 3b is a variant of the embodiment shown in Figure 3a;

Fig. 3c is another variation example of the embodiment shown in Fig. 3a;

Figure 4a is a schematic diagram of another embodiment of a CMOS image sensor according to the present invention;

Figure 4b is a variant of the embodiment shown in Figure 4a;

Fig. 4c is another variation example of the embodiment shown in Fig. 4a;

Fig. 4d is another variation example of the embodiment shown in Fig. 4a;

Fig. 5a is a top view of a pixel of the embodiment shown in Fig. 4a;

Figure 5b is an exemplary cross-sectional view of the embodiment shown in Figure 4a;

Figure 5c is yet another exemplary cross-sectional view of the embodiment shown in Figure 4a;

Fig. 6a is a schematic diagram of pixels according to yet another embodiment of the CMOS image sensor of the present invention;

Figure 6b is an exemplary cross-sectional view of the embodiment shown in Figure 6a;

Figure 6c is yet another exemplary cross-sectional view of the embodiment shown in Figure 6a;

Fig. 7a is a schematic diagram of pixels according to yet another embodiment of the CMOS image sensor of the present invention;

Figure 7b is an exemplary cross-sectional view of the embodiment shown in Figure 7a;

Figure 8a is a schematic diagram of another embodiment of a CMOS image sensor according to the present invention;

Figure 8b is a schematic diagram of yet another embodiment of a CMOS image sensor according to the present invention; and

FIG. 9 is a schematic diagram of yet another embodiment of a CMOS image sensor according to the present invention.

In the above-mentioned drawings, like reference numerals should be understood to indicate the same, similar or corresponding features or functions.

Detailed ways

In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings show, by way of example, specific embodiments in which the invention can be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments in accordance with the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not limiting, and the scope of the invention is defined by the appended claims.

In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings, which constitute a part of this invention, show by way of example specific embodiments in which the invention can be practiced. In this regard, directional terms such as "left", "right", "top", "bottom", "front", "rear", "lead", "forward", "rear", etc., Refer to the directions described in the accompanying drawings for use. Components of embodiments of the present invention may thus be positioned in a variety of different orientations, and directional terms are used for purposes of illustration and not limitation. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Accordingly, the following detailed description is not limiting, and the scope of the invention is defined by the appended claims.

According to an embodiment of the CMOS image sensor of the present invention, the CMOS image sensor includes a semiconductor substrate (for example, N-type or P-type silicon wafer), and the semiconductor substrate includes a first active region (for example, epitaxially grown on the semiconductor P-type epitaxial layer on the substrate), as shown in FIG.

The second active region 31 will be described in detail below.

The second active region 31 is adjacent to the well of the photodiode 11 (the position and area of the well are shown schematically in the box labeled 11 in Fig. 3a), and the second active region 31 has a The same conductivity type, that is to say, when the well of the photodiode is N-type, the second active region 31 is also N-type, and when the well of the photodiode is P-type, the second active region 31 It is also P-type. Further, the second active region 31 is connected to the reference potential V _REF . Also, the second active region 31 and the well of the photodiode 11 are formed by one ion implantation.

It should be noted that the meaning of the reference potential V _REF is: when the well of the photodiode is N-type, the reference potential V _REF is a higher potential than the well of the photodiode, and the well of the photodiode is P In the case of the type, the reference potential V _REF is a lower potential than the well of the photodiode; it should also be noted that the reference potential V _REF can be the same potential as the reset potential (which can be obtained by setting the second active region 31 is connected to the connection point marked 16), and the reference potential V _REF can also be a potential different from the reset potential.

Although the connection structure between the second active region 31 and the reference potential _VREF is not shown in FIG. The specific composition and manner of connecting a region to a potential will not be described in detail here.

The advantages of the embodiment of the CMOS image sensor according to the present invention as shown in FIG. 3a are explained below:

The second active region 31 is disposed adjacent to the well of the photodiode 11 and connected to the reference potential V _REF , so when the CMOS image sensor is illuminated by strong light, the photogenerated carriers exceeding the well capacity of the photodiode 11 are pulled to The second active region 31, thereby reducing or avoiding the overflow of photo-generated carriers to adjacent pixels, since the second active region 31 and the well of the photodiode 11 are formed by one ion implantation, so as far as the entire sensor chip surface is concerned, The distance D1 between the second active region 31 of each pixel and the well of the photodiode 11 is the same, so the anti-blooming effect of each pixel is the same, thereby obtaining a CMOS image sensor with uniform anti-blooming effect.

Fig. 3b is a modification example of the embodiment shown in Fig. 3a, as shown in the figure, the second active region 31 is arranged adjacent to the left side of the well of the photodiode 11, because the second active region 31 and the photodiode 11 The well is formed by one ion implantation, and the distance D2 between the second active region 31 of each pixel and the well of the photodiode 11 is the same.

Fig. 3c is another modification example of the embodiment shown in Fig. 3a, as shown in the figure, the second active region 31 is arranged adjacent to the right side of the well of the photodiode 11, because the second active region 31 and the photodiode 11 The well is formed by one ion implantation, and the distance D3 between the second active region 31 of each pixel and the well of the photodiode 11 is the same.

It should be noted that the second active region 31 can be arranged at any suitable distance and orientation relative to the well of the photodiode 11 . For example, the closer the second active region 31 is to the well of the photodiode 11, the easier it is for overflow carriers to be pulled to the second active region 31, while the photogenerated carriers used to generate photoelectric signals are pulled to the second active region. The inclination of the source region 31 is correspondingly increased, and the distance and orientation of the second active region 31 relative to the well of the photodiode 11 can be adjusted according to the actual anti-blooming requirements and the specific structure of the sensor.

Fig. 4a is a schematic diagram of another embodiment of a CMOS image sensor according to the present invention. In this embodiment, the first active region further includes two lateral doped regions 41 . Specifically, the lateral doped region 41 has the same conductivity type as the first active region, that is, when the first active region is P-type, the lateral doped region 41 is also P-type. In the case that the active region is N-type, the lateral doped region 41 is also N-type. Further, the lateral doped region 41 is located between the well of the photodiode 11 and the second active region 31, and the width of the lateral doped region 41 is greater than the width between the well of the photodiode 11 and the second active region 31. The width of the gap, so that the two lateral doped regions 41 respectively cover the adjacent corners of the well and the adjacent corners of the second active region 31 .

In addition to being able to achieve the advantages of the embodiment of FIG. 3a, the embodiment of FIG. 4a can also achieve the following advantages:

Since the two laterally doped regions 41 occupy the outer part of the gap between the well of the photodiode 11 and the second active region 31, the photogenerated carriers leak from the photodiode 11 to the second active region 31. The channel (shown by the arrow in the figure) is limited, and as a result, the tendency of the photo-generated carriers used to generate photoelectric signals to be pulled to the second active region 31 is reduced, and at the same time under strong light conditions Carriers exceeding the well capacity can still be drained.

In addition to the above advantages, the embodiment of Figure 4a can also achieve the following advantages:

The two or more lateral doped regions 41 can be defined in one photolithography and completed by one ion implantation or diffusion, so that the size of the restricted carrier channel is uniform on the entire sensor chip.

In addition, since the anti-halation effect is not sensitive to the position of the restricted carrier channel relative to the gap between the well of the photodiode 11 and the second active region 31, the lateral doped region 41 relative to the photodiode The overlay accuracy of the well 11 and the second active region 31 is not high, so the embodiment of FIG. 4a is simple and feasible in process.

Fig. 4 b is a modification example of the embodiment shown in Fig. 4 a, in this example, the width of lateral doped region 41 is equal to the width of the gap between the well of photodiode 11 and the second active region 31, still can obtain Confined flow paths for photogenerated carriers.

Figure 4c is another variant of the embodiment shown in Figure 4a, in this example, the width of the lateral doped region 41 is equal to the width of the gap between the well of the photodiode 11 and the second active region 31, still can A restricted flow path of photogenerated carriers is obtained.

Fig. 4d is another variation example of the embodiment shown in Fig. 4a, in this example, the first active region further includes three lateral doped regions 41, and the three lateral doped regions 41 are set to allow two Confined flow paths for photogenerated carriers.

5a is a top view of the pixel of the embodiment shown in FIG. 4a, and FIG. 5b is an exemplary cross-sectional view along the line 5-5' of the embodiment shown in FIG. 4a. As shown in the figure, the lateral doped region 41 is The Z direction extends from the chip surface to a certain depth, for example, may be approximately equal to the depth of the second active region 31 . The lateral doped region 41 can be formed by ion diffusion, for example.

Fig. 5c is another exemplary cross-sectional view of the embodiment shown in Fig. 4a. As shown in the figure, the lateral doped region 41 extends to a certain depth from below the chip surface in the Z direction, for example, may be approximately equal to the second The depth of the active region 31. The lateral doped region 41 can be formed by ion implantation, for example.

FIG. 6 a is a schematic diagram of a pixel of another embodiment of a CMOS image sensor according to the present invention. In this embodiment, the first active region further includes a vertical doped region 61 . Specifically, the vertical doped region 61 has the same conductivity type as the first active region, that is, when the first active region is P-type, the vertical doped region 61 is also P-type. If the active region is N-type, the vertical doped region 61 is also N-type. Further, the vertical doped region 61 is located between the well of the photodiode 11 and the second active region 31, and the width of the vertical doped region 61 is greater than the width between the well of the photodiode 11 and the second active region 31. The width of the gap.

6b is an exemplary cross-sectional view of the embodiment shown in FIG. 6a. In this configuration, the first active region includes a vertical doped region 61 between the well of the photodiode 11 and the second active region 31. Above the gap (in the Z direction), the flow path of photogenerated carriers is restricted below the gap.

FIG. 6c is another exemplary cross-sectional view of the embodiment shown in FIG. 6a. In this configuration, the first active region includes two vertical doped regions 61, located in the well of the photodiode 11 and the second active region 31. Above and below the gap (in the Z direction), thereby restricting the flow path of photogenerated carriers to the middle part of the gap.

In addition to being able to achieve the advantages of the embodiment of FIG. 3a, the embodiment of FIG. 6a can also achieve the following advantages:

Since the two vertical doped regions 61 occupy a part of the gap between the well of the photodiode 11 and the second active region 31 , there is a passage for the photo-generated carriers to discharge from the photodiode 11 to the second active region 31 (shown by the arrow in the figure) is confined, and as a result, the tendency of the photo-generated carriers used to generate the photoelectric signal to be pulled to the second active region 31 is reduced, and at the same time the well capacity is exceeded under strong light conditions Carriers can still be discharged.

In addition to the above-mentioned advantages, the embodiment of FIG. 6c can also achieve the following advantages:

The distance between the two or more vertical doped regions 61 in the Z direction can be controlled by controlling the energy of ion implantation, so that the size of the restricted carrier channel is uniform on the entire sensor chip, thereby preventing halo The effect is uniform across the sensor chip, so the embodiment of Fig. 6a-c is simple and easy to process.

Fig. 7a is a schematic diagram of a pixel according to yet another embodiment of a CMOS image sensor of the present invention. In this example, the first active region includes two lateral doped regions 41 and one vertical doped region 61, and Fig. 7b is a schematic diagram of Fig. 7a The cross-sectional view of the illustrated embodiment along the curve 7-7', as shown in the figure, the vertical doped region 61 is located in the gap between the well of the photodiode 11 and the second active region 31 (in the Z direction ), so that the two lateral doped regions 41 and one vertical doped region 61 jointly limit the flow path of photogenerated carriers, as shown by the arrow in FIG. 7b.

As disclosed in the foregoing part, on the basis of the embodiment shown in FIG. 7, a vertical doped region may be further included, which is located in the gap between the well of the photodiode 11 and the second active region 31 (in the Z direction). ) above.

Figure 8a is a schematic diagram of another embodiment of the CMOS image sensor according to the present invention, as shown in the figure, two photodiodes 11, 11' share a second active region 31 as the overflow of photo-generated carriers under strong light conditions The path can be defined in the photolithography step so that the distances between the second active region 31 and the two photodiodes 11 and 11 ′ are respectively equal, so as to obtain the same anti-halation effect.

Fig. 8b is a schematic diagram of another embodiment of the CMOS image sensor according to the present invention, as shown in the figure, two photodiodes 11, 11' share a second active region 31 as the overflow of photo-generated carriers under strong light conditions Furthermore, lateral doped regions 41 are respectively provided between the second active region 31 and the two photodiodes 11 and 11 ′.

According to the foregoing disclosure, the embodiment in FIG. 8 b may further include a vertical doped region 61 .

9 is a schematic diagram of another embodiment of the CMOS image sensor according to the present invention, the first active region further includes a heavily doped region connected to the second active region 31, the heavily doped region has a The active regions 31 have the same conductivity type, thereby reducing the contact resistance of the second active region 31 .

According to another aspect of the present invention, there is provided a method for a CMOS image sensor according to the present invention, comprising the steps of: forming a first active region on a semiconductor substrate; A well of the diode and a second active region adjacent to the well; forming an electrical connection of the second active region to a reference potential.

In one example, the well of the photodiode and the second active region are formed by ion implantation.

In one example, the method further includes: simultaneously forming at least two lateral doped regions in the first active region, wherein the lateral doped regions have the same conductivity as that of the first active region. Type, located between the well of the photodiode and the second active region, the width of the lateral doped region is equal to or greater than the gap between the well of the photodiode and the second active region width.

In one example, the method further includes forming a first vertical doped region in the first active region, wherein the first vertical doped region has the same conductivity type as the first active region , located below the gap, covering adjacent corners of the well and adjacent corners of the second active region.

In one example, the method further includes forming a second vertical doped region in the first active region, wherein the second vertical doped region has the same conductivity type as the first active region , located above the gap, covering adjacent corners of the well and adjacent corners of the second active region.

It can be understood that the above described embodiments are only used to describe rather than limit the present invention, and those skilled in the art can understand that modifications and variations can be made to the present invention as long as they do not deviate from the spirit and scope of the present invention. Modifications and variations as described above are considered to be within the scope of the invention and the appended claims. The protection scope of the present invention is defined by the appended claims. Furthermore, any reference signs in the claims shall not be construed as limiting the invention. The verb "comprise" and its conjugations do not exclude the presence of other elements or steps than those stated in a claim. The indefinite article "a" or "a" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims (11)

1. a cmos image sensor, comprising:

Semiconductor chip, comprises the first active area,

Wherein, described first active area comprises photodiode, transistor, and the second active area,

Wherein, the trap of the contiguous described photodiode in described second active area, and there is the conduction type identical with the trap of described photodiode, described second active area is connected to reference potential, wherein, the trap of described second active area and described photodiode is injected by primary ions and is formed, when the trap of described photodiode is N-type, described reference potential is the current potential higher compared to the trap of described photodiode, when the trap of described photodiode is P type, described reference potential is the current potential lower compared to the trap of described photodiode;

Wherein, described first active area also comprises at least two horizontal doped regions, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.

2. cmos image sensor as claimed in claim 1, wherein, described at least two horizontal doped regions cover the adjacent corners of described trap and the adjacent corners of described second active area.

3. cmos image sensor as claimed in claim 1, wherein, described first active area also comprises first longitudinal doped region, described first longitudinal doped region has the conduction type identical with described first active area, be positioned at the below in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.

4. cmos image sensor as claimed in claim 3, wherein, described first active area also comprises second longitudinal doped region, described second longitudinal doped region has the conduction type identical with described first active area, be positioned at the top in described gap, cover the adjacent corners of described trap and the adjacent corners of described second active area.

5. cmos image sensor as claimed in claim 1, wherein, described first active area also comprises at least one longitudinal doped region, described longitudinal doped region has the conduction type identical with described first active area, the below in the gap between the trap and described second active area of described photodiode, covers the adjacent corners of described trap and the adjacent corners of described second active area.

6. cmos image sensor as claimed in claim 1, wherein, described first active area comprises two photodiodes, and described second active area is between the trap of described two photodiodes.

7. cmos image sensor as claimed in claim 1, described first active area also comprises the heavily doped region being connected to described second active area, and described heavily doped region has the conduction type identical with described second active area.

8., for the manufacture of a method for cmos image sensor according to claim 1, comprise the following steps:

Form the first active area on the semiconductor substrate,

Form the trap of photodiode and the second active area of contiguous described trap in described first active area simultaneously,

Form described second active area to be connected with the electricity of reference potential;

Wherein, this manufacture method also comprises:

Form at least two horizontal doped regions in described first active area simultaneously,

Wherein, described horizontal doped region has the conduction type identical with described first active area, between the trap and described second active area of described photodiode, the width of described horizontal doped region is equal to, or greater than the width in the gap between the trap of described photodiode and described second active area.

9. method as claimed in claim 8, wherein, trap and second active area of described photodiode are formed by ion implantation.

10. method as claimed in claim 8, also comprises:

First longitudinal doped region is formed in described first active area,

Wherein, described first longitudinal doped region has the conduction type identical with described first active area, is positioned at the below in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.

11. methods as claimed in claim 10, also comprise:

Second longitudinal doped region is formed in described first active area,

Wherein, described second longitudinal doped region has the conduction type identical with described first active area, is positioned at the top in described gap, covers the adjacent corners of described trap and the adjacent corners of described second active area.