CN102623423B - Integrated circuit pattern and multiple patterning method - Google Patents

Abstract

The invention discloses an integrated circuit pattern, which comprises a group of material lines, wherein the material lines are provided with X-direction parts and Y-direction parts. The X and Y directional portions have first and second pitches, and the second pitch is larger, for example, at least 3 times larger than the first pitch. The X-direction portions are parallel to each other and the Y-direction portions are parallel to each other. The end region of the Y-direction portion includes a main line portion and an offset portion. The bias portion includes a bias element spaced apart from and electrically connected to the main line portion. The offset portion defines a contact area for use in subsequent pattern transfer steps. A method of providing contact areas for use in subsequent pattern transfer steps using multiple patterning during integrated circuit processing.

Description

Integrated circuit pattern and multiple patterning method

technical field

The present invention relates to integrated circuit patterns and their manufacture, including the use of multiple patterning methods for the manufacture of integrated circuits, through which the access of material lines formed thereby can be facilitated.

Background technique

Integrated circuits are commonly used to make a variety of electronic devices, such as memory chips. There is a strong desire to reduce the size of integrated circuits so that the density of individual components can be increased, and thus the functionality of integrated circuits can be increased. The minimum pitch (the minimum distance between two adjacent structures of the same type (eg, the same point of two adjacent gate conductors) on an integrated circuit is often used as a proxy measure for the density of the circuit.

Increases in circuit density are often limited by the resolution of available lithographic equipment. The minimum size of features and spaces that a given lithography tool can produce is related to its resolution capability.

The sum of the minimum feature width and the minimum space width that can be produced by a given lithography equipment is the minimum pitch that can be produced by this equipment. The minimum feature width is often approximately equal to the minimum space width, so the minimum pitch that can be produced with a given lithography equipment is approximately equal to twice the minimum feature width that can be produced.

One approach to shrinking the pitch of integrated circuit devices below the minimum pitch produced by lithography is through the use of double or quadruple patterning (sometimes referred to herein as multiple patterning). With this approach, a single mask is typically used to construct a series of parallel lines of material on the substrate. Different methods can then be used to transform each parallel material line into multiple parallel material lines. Methods typically do so using a sequence of deposition and etch steps. Different approaches are discussed in Xie, Peng and Smith, Bruce W., "Analysis of higher-level pitch segmentation for sub-32nm lithography", Optical Microlithography XXII, Proc. of SPIE Vol.7274, 72741 Y, c 2009 SPIE. One approach, discussed in the examples below, is to use self-aligned sidewall spacers to build roughly two or four parallel material lines for each material line built from the original mask.

Contents of the invention

The present invention is based in part on the recognition of the problems created by reducing the pitch to sub-lithographic dimensions. That is, while the spacing between material lines may be sublithographic, the requirements for access lines (typically via access elements such as vertical plugs) are not fully compatible with sublithographic dimensions. The mask used to define the plug is photolithographic in size, and the tolerance for misalignment of the mask increases the required size for the access area.

An example of an integrated circuit pattern includes a set of material lines on a substrate, the lines of material defining a plurality of lines of a pattern having an X-direction portion and a Y-direction portion. The length of the X-direction part is actually longer than the length of the Y-direction part. The X-direction part has a first distance, and the Y-direction part has a second distance, and the second distance is larger than the first distance. The X-direction parts are parallel to each other, and the Y-direction parts are parallel to each other. The Y-direction portion includes the end region. The end area of the Y-direction portion includes a main line portion and an offset portion. The biasing section includes a biasing element, which is separated from the main line section and electrically connected to the main line section. The offset portion defines a contact area for use in a subsequent pattern transfer step.

In some examples, the offset portion is located in the end region. In some examples, the second pitch is at least 3 times larger than the first pitch. In some examples, the lines are lithographically formed lines, and the first spacing has sublithographic dimensions and the second spacing has lithographic dimensions. In some examples, the lines are photolithographically formed lines, and the contact pickup areas have photolithographic dimensions. In some examples, the Y-direction portion includes a continuous loop bias portion that contacts and is located to one side of the main line portion. In some examples, an offset portion is disposed along an associated main line portion and includes elements extending generally parallel to the associated main line portion and extending generally perpendicular to the associated main line portion. In some examples, the laterally displaced region is along the mainline portion, and at least some of the offset portion is located in the laterally displaced region.

One example of a multiple patterning method used during integrated circuit processing provides contact areas for subsequent pattern transfer steps and is implemented as follows. A set of parallel line patterns is selected as a set of parallel first material lines. The group of parallel first material lines is formed above a substrate, and each first material line defines a pattern, which has an X-direction portion and a Y-direction portion. The length of the X-direction portion of the first material line is actually longer than the length of the Y-direction portion of the first material line. The step of selecting the parallel line pattern includes: selecting a first pitch for the X-direction part, and selecting a second pitch for the Y-direction part, the second pitch is greater than the first pitch, the X-direction parts are parallel to each other, and the Y-direction part is mutually parallel. At least two second material lines are formed parallel to each first material line to form a parallel X-direction portion of the second material line and a parallel Y-direction portion of the second material line. The Y-direction portion of the second material line includes an end region. The step of forming the second material line includes: forming a Y direction portion, which has a main line portion and an offset portion. The bias part includes a bias element, which is connected to the main line part and is electrically connected to the main line part. The offset portion defines a contact area for use in a subsequent pattern transfer step.

In some examples, the offset portion is formed in the end region. In some examples, the step of forming the Y-direction portion includes: forming a continuous loop bias portion that contacts the main line portion and is located on one side of the main line portion. In some examples, the step of forming the Y-direction portion includes forming an offset portion including at least one offset element extending laterally from the main portion. In some examples, the step of forming the Y-direction portion includes: forming an offset portion disposed along the main line portion and including elements extending approximately parallel to the main line portion and approximately perpendicular to the main line portion. In some examples, the step of forming the Y-direction portion includes: forming a portion of the laterally displaced region along the main line, and at least some of the offset portions are located in the laterally displaced region.

The technical solution of the invention facilitates the access of the material lines thus formed.

In order to have a clearer understanding of the above-mentioned and other aspects of the present invention, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

Figures 1 to 8 show a first example of a quadruple patterning process in simplified form.

Figure 1 is a top plan view of nested, looped material lines having parallel X-direction sections and parallel Y-direction sections, with parallel X-direction sections between the X-direction sections, constructed within a substrate from a correspondingly shaped mask. The spacing is smaller than the spacing between sections in the Y direction.

Figure 2 shows the construction of spacer layers on each side of the material line of Figure 1, thereby doubling the density with subsequent pitch reduction.

Figure 3 shows the construction of spacer layers on each side of the material line of Figure 2, thereby quadrupling the line density of Figure 1 with subsequent pitch reduction.

FIG. 4 shows a top plan view of a mask used with the configuration of FIG. 3 .

FIG. 5 shows the alignment of the mask of FIG. 4 with the configuration of FIG. 3 covering portions of the Y-direction portion.

Fig. 6 shows the result of the removal of the part of the Y-direction part covered by the mask of Fig. 4 creating the end region of the material line.

FIG. 7 is a plan view of a mask to be used with the configuration of FIG. 6 to build supplemental features.

FIG. 8 shows the result of using the mask of FIG. 7 and appropriate subsequent process steps, such as exposure and etching, for constructing supplementary features, especially contact pads and bit lines or word line.

Figures 9-16 show in simplified form a second example of a quadruple patterning process similar to the process of Figures 1-8, but in which nested, looped lines of material exist in the form of L-shaped segments.

Figures 17A-17C illustrate three additional examples of sets of nested, looped lines of material.

Figure 18 is a simplified flowchart showing the basic steps implemented using the multiple patterning method of the present invention discussed above with reference to Figures 1-17.

Figures 19-32 show the fabrication flow for an example of quadruple patterning using BESNOS WL.

FIG. 33 is a block diagram schematically showing the relationship among word line area, contact area, and peripheral circuit driver area.

Figures 34-36 show the use of an I-shape design in a two-fold patterning process to build the bias portion of the Y-direction portion, the bias portion contains the bias element and elements connecting the bias element to the main line portion.

Figures 37-39 show a process similar to that of Figures 34-36 but using a double I-shape design in the double patterning process.

Figures 40-42 show a process similar to that of Figures 37-39.

Figures 43-45 show a process similar to that of Figures 34-36 but using an E-shaped design in the double patterning process.

Figures 46-48 show a process similar to that of Figures 43-45.

Figures 49-51 show a process similar to that of Figures 34-36 but using a double F-shaped design in the double patterning process.

Figures 52-55 show a process similar to that of Figures 37-39 but using a double P design in the quadruple patterning process.

[Description of main component symbols]

10: group

12: The first material line

14: Substrate

16: X direction part

18: Y direction part

20: First pitch

22: second spacing

24: Length

26: Length

28: width

30: width

32: Second material line/spacer layer

34: Second material line

34: third material line/spacer layer

36: mask

38: Y points to the word/bit line part

40: X direction part

42: end area

44: mask

46: Contact Pad/Contact/Contact Area

48: Circuit interconnection line

52: L-shaped section

54: mask

55: Location

56: Y direction part/end element

60-70: Method steps

76: Substrate

78: First floor

80: second floor

82: The third floor

84: The fourth floor

86: Sixth floor

90: seventh floor

92: Eighth Floor

94: Photoresist lines

96: Construction

98: SiN layer

100: side wall spacer

102: film

104: side wall spacer

106: mask

107: polysilicon part

108: Lamination

109: SiO ₂ part

110: mask

112: Lamination

113: SiO ₂ part

114: polysilicon part

116: Lamination

118: SiO ₂ part

120: storage unit

122: etched components

124: word line/etched element

128: charge storage area

130: String selection line

132: word line area

134: contact area

136: Peripheral circuit driver area

150: section

152: section

154: Y direction part

156: Main line part

158: Main line part

160: Offset section

162: Bias element

164: Connection elements

166: Distance

168: width

170, 171, 172: Sections

174, 175: Lateral shift area

176: Connecting Areas

178: Y direction part

180, 181: main line part

182, 183: Bias part

184: Bias element

186: Connection elements

188: section

190: Main section

192: Y direction part

194, 196: main line part

198: Offset section

200: Bias element

202: Connecting elements

204: section

206: Main section

208, 210: first and second lateral displacement regions

212: Connection area

214: Y direction part

216, 218: main line part

220: Offset section

222: Distance

224: width

230: Main section

232, 234: Lateral shift area

236: Connection area

238: Island segment

240: hole

242: Y direction part

244, 245, 246, 247: main line part

248, 249, 250, 251: offset part

254: Bias element

256: Connection elements

258: Distance

260: width

262: Dimensions

Detailed ways

We understand and appreciate that the process steps and configurations described herein do not illustrate a complete manufacturing flow for the manufacture of integrated circuits. The present invention may be implemented in conjunction with various integrated circuit fabrication techniques conventionally used in known techniques, or developed in the future.

The following description will generally refer to specifically configured embodiments and methods. It should be understood that there is no intent to limit the invention to the disclosed embodiments and methods in detail, but that the invention may be practiced using other features, elements, methods and embodiments. The described preferred embodiments are used to illustrate the invention, not to limit its scope as defined by the claims. Those of ordinary skill in the art will recognize various equivalent changes to the accompanying description. Identical elements in the various embodiments and examples are generally denoted by the same reference numerals.

The various examples discussed below are generally referred to as using photolithography and photolithography steps, which involve transferring patterns from one object to the next, typically through the use of masks and photoresists in integrated circuit is completed during fabrication. However, the invention is not limited thereto, but may instead include steps such as writing the pattern directly on the substrate or other material which may be constructed in the future using other techniques such as e-beam. The photolithography step and other pattern writing or transfer techniques are sometimes commonly referred to as pattern transfer steps.

Figures 1-8 show a first example of a quadruple patterning process in simplified form.

1 is a top plan view of a set 10 of nested annular first material lines 12 constructed on a substrate 14 from corresponding suitable masks. The first material line 12 has a parallel X-direction portion 16 and a parallel Y-direction portion 18 . The spacing 20 between the X-direction sections 16 is smaller than the spacing 22 between the Y-direction sections 18 . The distance 22 is preferably at least twice the distance 22, more preferably at least three times the distance 22, and even more preferably four times the distance 22. The length 24 of the X-direction portion 16 is substantially greater than the length 26 of the Y-direction portion 18, typically by orders of magnitude greater, such as at least 30 times greater. However, for purposes of illustration, the length 24 of the X-direction portion 16 is not drawn to scale, but is greatly reduced. In this example, the width 28 of each X-direction portion 16 may be, for example, about 60 nm, and the width 30 of each Y-direction portion 18 may be, for example, about 150 nm. Because pitch 22 is greater than pitch 20, this extra width for Y-direction portion 18 can be accommodated.

FIG. 2 shows a spacer layer 32 built on each side of the X-direction portion 16 and the Y-direction portion 18 of the first material line 12 of FIG. 1 . The spacer layer 32 acts as a set of second material lines 32 . This effectively doubles the line density compared to the density of the lines 12 of the first material, taking advantage of the necessary reduction in pitch. In subsequent processing steps, the X-direction portion 16 and the Y-direction portion 18 of the first material line 12 are removed, leaving only the spacer layer 32 as the second material line.

FIG. 3 shows building up a spacer layer 34 on each side of the second material line 32 of FIG. 2, thereby quadrupling the line density from that of FIG. 1 with the necessary reduction in spacing. As with portions 16 and 18 , the second material line 32 is removed during a subsequent processing step, leaving only the spacer layer 34 as the third material line 34 .

FIG. 4 is a top plan view of mask 36 for use with the configuration of FIG. 3 . The mask 36 is a portion for shielding the Y-direction portion 38 of the spacer layer 34 of FIG. 3 ; in this example, the X-direction portion 40 is not altered by using the mask 36 as shown in FIG. 5 . Use of the mask 36 allows part of the Y-direction portion 38 of the spacer layer 34 to be removed. The result of this removal (shown in FIG. 6 ) builds up end region 42 along Y-direction portion 38 .

FIG. 7 is a plan view of a mask 44 to be used with the configuration of FIG. 6 to build supplementary features. In this example, the supplementary features include contact pads and circuit interconnect lines to be applied to the end region 42 of the Y-direction portion 38 . FIG. 8 shows the result of using mask 44 and appropriate post-processing steps (such as exposure and etching steps) for building supplementary features, especially contact pads 46 and circuitry in end region 42 along Y-direction portion 38. Interconnect line 48 . The pitch of the Y-direction portions 38 is preferably sufficient for dimensional lithographically fabricated pads and alignment tolerances, while the pitch of the X-direction portions 40 is not compressed by these issues and thus may be sub-lithographic.

The increased spacing between the end regions 42 of the Y-direction portion 38 when compared to the pitch of the X-direction portion 40 is important because it allows the use of known lithographically-to-scale contacts that are otherwise formed. Pads 46 or larger pads are used to provide electrical access to the dimensionally sublithographically fabricated and spaced X-direction portions 40 of the third material line 34 . The third material line 34 is generally used as a word line or a bit line, which enables the X-direction portion 40 and the Y-direction portion 38 to be generally an X-directed word/bit line portion 40 and a Y-directed word/bit line portion 38, respectively. By providing sufficient space between the innermost X-direction portions 40 of these lines of material 34 , circuit interconnect lines 48 can be placed between the innermost X-direction portions as shown in FIG. 8 . In other examples, circuit interconnect lines 48 may be disposed outside of the outermost X-direction portions 40 of the lines of material 34 . The circuit interconnect lines 48 may be lithographically or sub-lithographically fabricated lines to size.

Figures 9-16 show in simplified form a second example of a quadruple patterning process, which is similar to the first example of the quadruple patterning process of Figures 1-8. Therefore, this second example will not be described in detail. However, the main differences are as follows. The nested, looped material strands 12 of the set 10 are present in the form of L-shaped sections 52 . Thus, pairs of L-shaped segments 52 build up this nested, looped line of material. The mask 54 of Figure 12 is sized to cover not only a portion of the Y-direction portion 38 but also a portion of the X-direction portion 40, see FIG. 56 and are electrically connected to each other.

17A-17C show three additional examples of sets 10 of nested, looped lines of material 12 . A contact pad will be formed at location 55 along Y-direction portion 56 .

Figure 18 is a simplified flowchart showing the basic steps implemented in the multiple patterning method of the present invention. Beginning at 68, a set of parallel wire patterns, typically a nested ring pattern, is selected for a set 10 of parallel first material lines 12. The first material line 12 has a parallel X-direction portion 16 which may actually be longer than the parallel Y-direction portion 18, for example 100 or 1000 times longer. Next, at 62, the first and second spacings 20, 22 for the X-direction and Y-direction portions 16, 18 are selected. These pitches are chosen such that the second pitch 22 is larger than the first pitch 20, for example 4-8 times larger. At 64 , the set 10 of parallel first material lines 12 is formed over a substrate 14 . Two second material lines 32 are formed at 66 . The second material line 32 is parallel to the first material line 12 . At 68 , two third lines of material 34 are formed parallel to each second line of material 32 . Doing so creates a parallel X-direction portion 40 and a parallel Y-direction portion 38 for the third material line. The Y-direction portion 38 of the second material line 34 includes an end region 42 . At 70 , supplementary features are built, such as enlarged contact pads 46 and circuit interconnection lines 48 in the end region 42 .

Figures 19-32 show the manufacturing process of an example of patterning self-aligned spacers using BE-SONOS WL quadruple, BE-SONOS stands for charge trapping memory cell. FIG. 19 shows substrate 76 including first through eighth layers 78 - 92 and photoresist lines 94 formed on first layer 78 . In this example, the first, third and sixth layers 78, 82 and 88 are composed of polysilicon (commonly denoted poly), while the second and fourth layers 80 and 84 are composed of _SiO2 . The sixth layer 86 is made of WSi. The eighth layer 92 is Si. The seventh layer 90 is a composite of five layers for use as a charge storage structure for BE-SONOS with alternating _SiO2 and SiN layers, where the _SiO2 layers are the first, third and third calculated from above five floors. The first, second and third layers 78, 80 and 82 are considered sacrificial layers because they are completely removed during the patterning process. Other materials and configurations of materials may also be used.

Referring to FIG. 20 , a photoresist line 94 is used to etch the first layer 78 to build a structure 96 , which corresponds to the first material line 12 of FIG. 1 . FIG. 21 shows the result of having a SiN layer 98 deposited over the configuration of FIG. 20 . FIG. 22 shows the result of anisotropic etching of this layer 98 , which removes those parts of layer 98 covering formation 96 other than layer 80 . Doing so leaves sidewall spacers 100 on each side of construction 96 , where the sidewall spacers correspond to spacers 32 of FIG. 2 . FIG. 23 shows the result of etching structure 96 leaving sidewall spacers 100 . FIG. 24 shows the configuration of FIG. 23 after a thin film 102 of polysilicon has been deposited thereon. In FIG. 25, the film 102 above the sidewall spacers 100 and covering these portions of the second layer 80 is removed, thereby leaving polysilicon sidewall spacers 104 on each side of the SiN sidewall spacers 100. superior.

In FIG. 26, a photoresist mask 106 is used to cover portions of the configuration of FIG. 25 that have not been removed. Mask 106 may be considered the inverse of mask 36 of FIG. 4 . FIG. 27 shows the result of removing the polysilicon sidewall spacers 104 not protected by the photoresist mask 106 and the subsequent removal of the photoresist mask 106 . 28 shows the result of etching the SiN sidewall spacers 100 and those portions of the second layer 80 not covered by the sidewall spacers 104; doing so leaves the polysilicon/ _SiO2 stack 108 on the third layer 82. Stack 108 includes an upper polysilicon portion 107 and a lower SiO ₂ portion 109 . Comparing the two formations 96 on the right hand side of the formation of FIG. 20 with the polysilicon/ _SiO2 stack 108 on the right hand side of the formation of FIG. 28, we can see that the number of vertical formations has changed from 2 to 4 times and becomes 8.

FIG. 29 shows a photoresist mask 110 on the construction of FIG. 28 , which generally corresponds to mask 44 of FIG. 7 . FIG. 30 shows the configuration of FIG. 29 after those portions of third layer 82 not covered by stack 108 or mask 110 have been etched. The upper polysilicon portion 107 is removed leaving stack 112 . The stack 112 includes an upper SiO ₂ portion 113 and a lower polysilicon portion 114 . In FIG. 30, the photoresist mask 110 has also been removed. FIG. 31 shows the result of an oxide etch that removes the upper SiO ₂ portion 113 and any portion of the fourth SiO ₂ layer 84 not covered by the polysilicon portion 114 and builds up the stack 116 . Stack 116 includes polysilicon portion 114 and SiO ₂ portion 118 .

32 shows the result of etching those portions of layers 86, 88, and 90 not covered by layer stack 116, removing polysilicon portion 114 and partially removing _SiO2 portion 118, leaving a portion with etched elements 122, 124 (typically A column of memory cells 120 (WSi and polysilicon) together form a plurality of columns of word lines 124 , and the word lines 124 are located above the charge storage region 128 . In this example, storage unit 120 forms a NAND string. This etching step also builds string select lines 130 extending in the same direction as word lines 124 in this example. Since the fourth layer 84 is generally much thicker than the seventh layer 90, a portion of the SiO ₂ portion 118 may remain after the entire seventh layer 90 has been etched through.

FIG. 33 is a block diagram showing closely spaced X-directed word line portions 40 and wider spaced Y-directed word line portions 38 in word line region 132 . In a typical memory circuit, there will typically be thousands of word lines 124 . In this example, two different contact regions 134 are disposed adjacent to and connected to the word line region 132 . Contacts 46 are disposed within contact regions 134 along the more widely spaced (larger pitch) Y-directed word line portions 38 . Peripheral circuit driver area 136 is disposed between and connected to contact regions 134 . The following configurations of this type provide effective layout of the actual area of the integrated circuit for high density storage: (1) wordlines in wordline region 132; (2) wordline region 132 if one or more contact regions 134 are along Y-directed word line portion 38 includes contacts 46 ; and (3) one or more associated peripheral circuit driver areas 136 contact region 134 .

The following discussion of FIGS. 34-55 will illustrate various modifications to the methods and configurations described above for partially constructing contact regions in the Y direction. The examples of FIGS. 34-51 use a double patterning approach with the understanding of quadruple patterning used with the examples of FIGS. 52-55 , or larger patterns may also be used.

FIG. 34 shows a Y-direction portion 18 comprising a relatively short Y-direction portion segment 150 adjacent to a main Y-direction portion segment 152 . Section 150 is sometimes referred to as an island section 150 . FIG. 35 shows that conductive spacer layer 34 is formed on either side of segment 152 and surrounds segment 150 . FIG. 36 shows the configuration of FIG. 35 after sections 150 , 152 have been removed, thereby leaving a Y-direction portion 154 comprising main line portions 156 , 158 and offset portion 160 . The biasing portion 160 includes a biasing element 162 (spaced apart from and generally parallel to the main line portion 158 ) and a plurality of connecting elements 164 (electrically connecting the biasing element 162 to the main line portion 158 ). The Y-direction portion 154 forms a contact region 46 for subsequent photolithography steps. The distance 166 between the Y-direction portion segments 150 , 152 is preferably greater than the width 168 of the mainline portions 156 , 158 . Distance 166 is preferably less than three times width 168 . This form of patterning is sometimes referred to as an I-shaped design for double patterning because of the I-shape of the island segments 150 .

Figures 37-39 relate to a double I-shape design for double patterning. The Y-direction section 18 comprises Y-direction section sections 170 , 171 which are arranged adjacent to the main Y-direction section section 172 . The main Y-direction subsection 172 has first and second laterally displaced regions 174 , 175 connected by a connecting region 176 . FIG. 38 shows that conductive spacer layer 34 is formed on either side of segment 172 and surrounds island segments 170 , 171 . FIG. 39 shows the configuration of FIG. 38 after removing sections 170 , 171 , and 172 , thereby leaving a Y-direction portion 178 comprising main line portions 180 , 181 and offset portions 182 , 183 . The biasing portions 182, 183 each include a biasing element 184 (separated from and generally parallel to the main line portions 180, 181) and a plurality of connection elements 186 (to electrically connect the biasing element 184 thereto). Each mainline section 180, 181). The Y-direction portion 178 forms the contact region 46 for subsequent photolithography steps.

Figures 40-42 show an alternative to the example of Figures 37-39, in which like elements are denoted by like reference numerals.

Figures 43-45 relate to an E-shaped design for double patterning. FIG. 43 shows a Y-direction portion 18 comprising three relatively short, laterally directed segments 188 extending laterally from and generally perpendicular to a main segment 190. FIG. 44 shows conductive spacer layers 34 formed on either side of segment 190 and surrounding segment 188 . FIG. 45 shows the configuration of FIG. 44 with segments 188 , 190 removed leaving a Y-direction portion 192 including main line portions 194 , 196 and offset portion 198 . Biasing portion 198 includes a biasing element 200 spaced apart from and substantially parallel to mainline portion 196 and connecting element 202 , wherein connecting element 202 electrically connects biasing element 200 to mainline portion 196 . The Y-direction portion 192 forms a contact region 46 for subsequent photolithography steps. In this example, contact region 46 includes portions of both offset portion 198 and mainline portions 194 , 196 ; in other examples, contact region 46 cannot include a portion of mainline portion 194 . The distance 222 between the Y-direction portion segments 188 is preferably greater than or equal to the width 224 of the mainline portions 194 , 196 . Distance 222 is preferably less than 4 times width 224 . These dimensions typically have similar designs, such as those shown in FIGS. 46-49 and 49-51 .

Figures 46-48 show alternatives to the example of Figures 43-45, wherein like elements are indicated by like reference numerals.

Figures 49-51 relate to a double F-shaped design for double patterning. FIG. 49 shows a Y-direction portion 18 comprising a main section 206 having first and second laterally displaced regions 208 , 210 connected by a connecting region 212 . Portion 18 also includes two relatively short laterally directed sections 204 extending laterally from and generally perpendicular to main section 206 . FIG. 50 shows that conductive spacer layer 34 is formed on either side of segment 206 and surrounds segment 204 . FIG. 51 shows the configuration of FIG. 47 after removal of segments 204 , 206 thereby leaving a Y-direction portion 214 comprising main line portions 216 , 218 and offset portions 220 extending laterally from main line portions 216 , 218 . The bias portion 220 is electrically connected to the main line portions 216 , 218 . The Y-direction portion 214 establishes a contact region 46 associated with each of the main line portions towards 216, 218 for use in subsequent photolithographic steps.

Figures 52-55 relate to a double P-shape design for quadruple patterning. FIG. 52 shows a Y-direction portion 18 comprising a main section 230 having first and second laterally displaced regions 232 , 234 connected by a connecting region 236 . Section 18 also includes two relatively short island sections 238 spaced apart from main section 230 . A hole 240 is formed in the connecting region 236 . FIG. 53 shows the configuration of FIG. 52 after the spacer layer 32 is formed along the edge of the Y-direction portion 18 . FIG. 54 shows the formation of the conductive spacer layer 34 along the edge of the spacer layer 32 after the Y-direction portion 18 has been removed. FIG. 55 shows the configuration of FIG. 54 after removal of the spacer layer 32, thereby leaving a Y-direction portion 242 comprising main line portions 244, 245, 246, 247 and offset portions extending laterally from their associated main line portions. 248, 249, 250, 251. Each biasing section 248-251 includes a biasing element 254 that is electrically connected to its associated mainline section via a connecting element 256. The Y-direction portion 242 forms a set of four contact regions 46 for subsequent photolithography steps. Within each offset portion is a conductive element that does not need to be electrically connected to any other structure but does help provide mechanical stability to the resulting contact area 46 . The distance 258 between the island section 238 and the area 232 of the main section 230 is preferably greater than or equal to twice the width 260 of the main line portion 244-247, and preferably less than or equal to five times the main line portion 244-247. 247 by 260 in width. Dimension 262 is preferably greater than or equal to width 260 of main line portions 244-247, and preferably less than or equal to three times width 260 of main line portions 244-247.

The invention discussed above with reference to FIGS. 34-55 can be used in general semiconductor devices (including memory and logic elements) for building various features (such as gates) other than the metallization patterns discussed above. pole). The invention is also applicable to various integrated circuit processing technologies, including shallow trench isolation.

Any and all patents, patent applications, and printed publications cited above are incorporated by reference herein.

In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention belongs may make various minor changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by what is defined by the claims.

Claims (28)

1. An integrated circuit pattern, characterized in that, comprising: a set of material lines over a substrate, the lines of material defining a pattern of lines having a plurality of x-direction portions and a plurality of y-direction portions, the length of the x-direction portions being longer than the length of the y-direction portions ; The X-direction portions have a first pitch, and the Y-direction portions have a second pitch, and the second pitch is greater than the first pitch; The X-direction portions are parallel to each other, and the Y-direction portions are parallel to each other; These Y-direction portions contain a plurality of end regions; and The end regions of the Y-direction portions include main line portions and bias portions, the bias portions include bias elements spaced apart from the main line portions and electrically connected to the main line portions, the bias portions Partially defines a plurality of contact areas for use in subsequent pattern transfer steps, wherein the bias element is parallel to the main line part and is electrically connected to the main line part through a plurality of connecting elements, and the distance between the Y direction part sections is larger than the main line part width. 2. The integrated circuit pattern according to claim 1, wherein the offset portions are located at the end regions. 3. The integrated circuit pattern according to claim 1, wherein the lengths of the X-direction portions are at least 30 times the lengths of the Y-direction portions. 4. The integrated circuit pattern according to claim 1, wherein the second pitch is at least twice as large as the first pitch. 5. The integrated circuit pattern according to claim 1, wherein the second pitch is at least four times larger than the first pitch. 6. The integrated circuit pattern according to claim 1, wherein the X-direction portions are perpendicular to the Y-direction portions. 7. The integrated circuit pattern according to claim 1, wherein the lines comprise a plurality of word lines or a plurality of bit lines. 8 . The integrated circuit pattern according to claim 1 , wherein the lines are lithographically formed lines, the first spacing has a sublithographic dimension, and the second spacing has a lithographic dimension. 9. The integrated circuit pattern according to claim 1, wherein the Y-direction portions and the X-direction portions define a set of nested circular parallel lines. 10. The integrated circuit pattern according to claim 1, wherein the lines are photolithographically formed lines, and the contact regions have a plurality of photolithographic dimensions. 11. The integrated circuit pattern according to claim 1, wherein the Y-direction portions comprise a continuous loop bias portion contacting the main line portion and located at one side of the main line portion. 12. The integrated circuit pattern of claim 11, wherein the bias portions comprise at least one bias element extending laterally from the main line portions. 13. The integrated circuit pattern according to claim 1, wherein an offset portion is disposed along an associated main line portion and comprises a plurality of elements extending parallel to the associated main line portion or perpendicular to the associated main line portion part. 14. The integrated circuit pattern of claim 1, comprising a plurality of laterally displaced regions along the main line portions, at least some of the offset portions being located in the laterally displaced regions. 15. A method of multiple patterning for use during integrated circuit processing, characterized in that it is used to provide a plurality of contact areas for subsequent pattern transfer steps, the method comprising: selecting a set of parallel line patterns for a set of parallel first material lines; The group of parallel first material lines is formed above a substrate, each first material line defines a pattern having an X-direction portion and a Y-direction portion, the lengths of the X-direction portions of the first material lines are shorter than the lengths of the first material lines The lengths of the Y-direction portions of a material line are long; The step of selecting the parallel line patterns includes: selecting a first pitch for the X-direction portions, and selecting a second pitch for the Y-direction portions, the second pitch being larger than the first pitch, the X-direction portions being parallel to each other, and These Y-direction portions are parallel to each other; forming at least two second material lines parallel to each first material line to construct parallel X-direction portions of the second material lines and parallel Y-direction portions of the second material lines, the Y-direction portions of the second material lines the orientation section contains multiple end regions; and The step of forming the second material lines includes: forming the Y-direction portions having a plurality of main line portions and a plurality of offset portions, the offset portions including a plurality of bias elements separated from the main line portions and electrically connected to These main line parts, these offset parts define a plurality of contact areas for subsequent pattern transfer steps, wherein the bias elements are parallel to the main line parts and are electrically connected to the main line parts through a plurality of connecting elements, and the Y direction part section The distance between them is greater than the width of the main line section. 16. The method of claim 15, wherein the offset portions are formed in the end regions. 17. The method of claim 15, wherein the step of forming the Y-direction portions comprises: forming a continuous loop bias portion contacting the main line portion and located at one side of the main line portion. 18. The method of claim 15, wherein the step of forming the Y-direction portions comprises: forming an offset portion comprising at least one offset element extending laterally from the main line portion. 19. The method of claim 15, wherein the step of forming the Y-direction portions comprises: forming an offset portion disposed along the main line portion and comprising a plurality of elements extending substantially parallel to the The main line portion is at or substantially perpendicular to the main line portion. 20. The method according to claim 15, wherein the step of forming the Y-direction portions comprises: forming a plurality of laterally displaced regions along the main line portions, at least some of the offset portions are located in the laterally displaced regions . 21. The method of claim 15, wherein the second material lines comprise a plurality of word lines or bit lines. 22. The method according to claim 15, wherein the step of forming the at least two second material lines further comprises: forming two additional lines of material parallel to each of the first lines of material; and Two second lines of material are formed parallel to each of the additional lines of material. 23. The method of claim 15, wherein the step of selecting the parallel line patterns comprises selecting a set of nested annular parallel line patterns for a set of nested annular parallel first material lines. 24. The method according to claim 15, further comprising: removing at least part of the Y-direction portions to construct the terminal regions. 25. The method of claim 15, wherein one of the first material lines defines at least one of: a continuous rectangular shape; a rectangular shape having a portion along the Y directions a gap of one of them; a rectangular shape with a gap along the Y-direction portions; and a rectangular shape with only a Y-direction portion. 26. The method of claim 15, wherein the lengths of the X-direction portions are at least 30 times the lengths of the Y-direction portions. 27. The method of claim 15, wherein the second distance is at least twice the first distance. 28. The method of claim 15, wherein the second distance is at least four times the first distance.