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CN102569426A - PN junction voltage-controlled varactor and preparation method thereof - Google Patents

PN junction voltage-controlled varactor and preparation method thereof Download PDF

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Publication number
CN102569426A
CN102569426A CN2010105983595A CN201010598359A CN102569426A CN 102569426 A CN102569426 A CN 102569426A CN 2010105983595 A CN2010105983595 A CN 2010105983595A CN 201010598359 A CN201010598359 A CN 201010598359A CN 102569426 A CN102569426 A CN 102569426A
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Prior art keywords
epitaxial loayer
ion implanted
implanted layer
metal
substrate
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CN2010105983595A
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CN102569426B (en
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金勤海
陆涵蔚
吴兵
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a PN junction voltage-controlled varactor, a first epitaxial layer with the same conductivity type is arranged on a substrate, the first epitaxial layer contains at least one trench, a heavily doped ion implantation layer with the conductivity type opposite to that of the epitaxial layer is covered on the inner wall of the trench and the upper surface of the first epitaxial layer, a second epitaxial layer is filled in the trench, and the second epitaxial layer has the same conductivity type with the first epitaxial layer. The heavily doped ion implantation layer is connected through a front metal to form one electrode of the voltage-controlled varactor, the second epitaxial layer is also connected through the front metal to form the other electrode of the voltage-controlled varactor, and the two electrodes are separated by photoetching and etching. The back surface of the substrate is connected with a back metal, and when a chip is packaged, the back metal is connected with the electrode connected with the second epitaxial layer. The result of the invention shows that the junction area of a PN junction is enlarged, and the regulation range of capacitance value is widened. The invention further discloses a preparation method of the PN junction voltage-controlled varactor.

Description

PN junction voltage control variodenser and preparation method thereof
Technical field
The present invention relates to a kind of PN junction voltage control variodenser.
Background technology
Phase-locked loop has in analog circuit and radio circuit extremely widely to be used, and voltage control variodenser is a Primary Component in the phase-locked loop.The capacitance adjustable extent of voltage control variodenser plays fundamental influence to the performance of phase-locked loop.
Existing voltage control variodenser mainly contains two kinds of structures: a kind of is to adopt mos capacitance; Wherein Semiconductor substrate S (for example silicon) is through light dope; Between metal or polysilicon gate and substrate, add bias voltage, substrate forms depletion layer, thereby the voltage-regulation depletion widths is regulated the capacitance of variodenser; Another kind is the PN junction structure, regulates the capacitance that the width of tying depletion region is regulated variodenser through its reverse biased.The capacity valve regulating range of these two kinds of variodensers can both improve through changing structure.
Summary of the invention
The technical problem that the present invention will solve provides a kind of PN junction voltage control variodenser, and it has bigger capacity valve regulating range.
For solving the problems of the technologies described above; PN junction voltage control variodenser of the present invention; For on substrate, having first epitaxial loayer of identical conduction type, comprise at least one groove in said first epitaxial loayer, the inwall of said groove and the said first epitaxial loayer upper surface are coated with the conduction type ion implanted layer opposite with epitaxial loayer; Second epitaxial loayer is filled in the said groove; Said ion implanted layer is connected to form an electrode of voltage control variodenser through metal, and said second epitaxial loayer also is connected to form another electrode of voltage control variodenser through metal, and said second epitaxial loayer is connected through metal with said substrate simultaneously.
The invention still further relates to a kind of preparation method of PN junction voltage control variodenser, comprise the steps:
(1) first epitaxial loayer that growth and substrate have the identical conduction type on substrate;
(2) adopt ion implantation technology, form ion implanted layer in said first epi-layer surface, the conduction type of said ion implanted layer is opposite with said first epitaxial loayer;
(3) deposit etching barrier layer on said first epitaxial loayer;
(4) adopt photoetching process to define groove, then said etching barrier layer of etching and said first epitaxial loayer form groove;
(5) utilize said etching barrier layer, adopt ion implantation technology to inject ion at said trench wall, it injects the identical of energy and implantation concentration and step (2), and the inclination angle of ion beam is made as the 7-80 degree, at said trench wall formation ion implanted layer;
(6) epitaxial growth for the second time makes second epitaxial loayer fill said groove, removes etching barrier layer afterwards;
(7) said ion implanted layer is connected to form an electrode of voltage control variodenser through metal, second epitaxial loayer also is connected to form another electrode of voltage control variodenser through metal, second epitaxial loayer and substrate are electrically connected.
PN junction voltage control variodenser of the present invention has wherein designed serpentine configuration, makes the junction area of PN junction become big, and depletion region broadens when adding reverse biased, makes capacity valve regulating range become big.The design of second epitaxial loayer makes the depletion region of PN junction become big, further strengthens the adjustable range of capacitance.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the structural representation of PN junction voltage control variodenser of the present invention;
Fig. 2 is the sketch map of ion injection for the first time;
Fig. 3 is the structural representation after ion injects for the first time;
Fig. 4 forms the structural representation behind the groove for etching;
Fig. 5 is the sketch map of ion injection for the second time;
Fig. 6 is the structural representation after ion injects for the second time;
Fig. 7 is the structural representation after the epitaxial growth for the second time;
Fig. 8 is the structural representation of PN junction voltage control variodenser of the present invention;
Fig. 9 is a preparation flow sketch map of the present invention.
Embodiment
PN junction voltage control variodenser of the present invention; Concrete structure is a (see figure 1): first epitaxial loayer that on substrate, has the identical conduction type; Comprise at least one groove in first epitaxial loayer; The inwall of groove and the first epitaxial loayer upper surface are coated with the conduction type ion implanted layer opposite with epitaxial loayer, and second epitaxial loayer is filled in the groove, and second epitaxial loayer is identical with the conduction type of first epitaxial loayer.The heavy doping ion implanted layer is connected to form an electrode of voltage control variodenser through front metal, and second epitaxial loayer also is connected to form another electrode of voltage control variodenser through front metal, and above-mentioned two electrodes through photoetching, etching separately.At substrate back deposit back metal, when Chip Packaging, back metal is connected with the electrode that is connected second layer extension.The doping content of ion implanted layer is usually greater than the doping content of first epitaxial loayer and second epitaxial loayer.
In the said structure, the doping content of substrate can be 10 14-10 16Individual atom/cm 2, the doping content of first epitaxial loayer is 10 12-10 14Individual atom/cm 2, the doping content of second epitaxial loayer is 10 12-10 14Individual atom/cm 2, the thickness of ion implanted layer is the 0.1-1 micron, the doping content of ion implanted layer is: 10 14-10 16Individual atom/cm 2The concentration of first epitaxial loayer and second epitaxial loayer can be set to identical.The width of the groove in the epitaxial loayer is the 0.1-100 micron, and the degree of depth is the 0.1-50 micron.The number of groove can be provided with according to concrete capacity valve regulating range, and groove is many more, and effectively the PN junction junction area is big more, and the capacitance adjustment scope is big more.
The preparation method of PN junction voltage control variodenser of the present invention comprises the steps (see figure 9):
(1) first epitaxial loayer that growth and substrate have the identical conduction type on substrate;
(2) adopt ion implantation technology, form ion implanted layer, the conduction type of ion implanted layer and first epitaxial loayer opposite (seeing Fig. 2 and Fig. 3) in first epi-layer surface;
(3) deposit etching barrier layer (can be silicon oxide layer) on said first epitaxial loayer;
(4) adopt photoetching process to define groove, then this etching barrier layer of etching and first epitaxial loayer form the groove (see figure 4);
(5) utilize said etching barrier layer, adopt ion implantation technology to inject ion at said trench wall, it injects the identical of energy and concentration and step (2), at said trench wall formation ion implanted layer.In this time injection process, implant angle can be made as the inclination of 7-80 degree and inject (seeing Fig. 5 and Fig. 6).
(6) epitaxial growth for the second time makes the second epitaxial loayer filling groove, removes etching barrier layer afterwards; Because the existence of etching barrier layer, epitaxial growth are only carried out at channel bottom and inwall, promptly realize the selective epitaxial growth (see figure 7).
(7) ion implanted layer is connected to form an electrode of voltage control variodenser through front metal, second epitaxial loayer also is connected to form another electrode of voltage control variodenser through front metal, second epitaxial loayer and substrate are electrically connected.Above-mentioned two electrodes separate (seeing Fig. 8 and Fig. 1) through photoetching, etching.
Wherein the formation of electrode specifically can be:
1) at film between illuvium on first epitaxial loayer, then the said interlayer film of etching forms contact hole respectively on the ion implanted layer and second epitaxial loayer;
2) the depositing metal filling contact hole forms contacting metal, removes the metal on the interlayer film surface through doing quarter or cmp;
3) deposit front metal forms the metal wire of second epitaxial loayer and the metal wire of ion implanted layer respectively through photoetching and etching technics, as two electrodes.These two electrodes can form through front metal figure separately;
4) with the substrate back attenuate, deposit back metal afterwards;
5) when Chip Packaging, the electrode of back metal with second epitaxial loayer is electrically connected.
In the said method, the doping content of substrate can be 10 14-10 16Individual atom/cm 2, the doping content of first epitaxial loayer can be 10 12-10 14Individual atom/cm 2, the doping content of second epitaxial loayer can be 10 12-10 14Individual atom/cm 2, the doping content of ion implanted layer can be: 10 14-10 16Individual atom/cm 2The width of groove can be the 0.1-100 micron, and the degree of depth can be the 0.1-50 micron, and the thickness of ion implanted layer can be the 0.1-1 micron.

Claims (7)

1. PN junction voltage control variodenser; It is characterized in that: first epitaxial loayer that on substrate, has the identical conduction type; Comprise at least one groove in said first epitaxial loayer; The inwall of said groove and the said first epitaxial loayer upper surface are coated with the conduction type ion implanted layer opposite with epitaxial loayer; Second epitaxial loayer is filled in the said groove, and said ion implanted layer is connected to form an electrode of voltage control variodenser through metal, and said second epitaxial loayer also is connected to form another electrode of voltage control variodenser through metal; Said second epitaxial loayer is connected through metal with said substrate simultaneously, and the doping content of said ion implanted layer is greater than the doping content of said first epitaxial loayer and second epitaxial loayer.
2. PN junction voltage control variodenser as claimed in claim 1 is characterized in that: the doping content of said substrate is 10 14-10 16Individual atom/cm 2, the doping content of said first epitaxial loayer is 10 12-10 14Individual atom/cm 2, the doping content of said second epitaxial loayer is 10 12-10 14Individual atom/cm 2, the thickness of said ion implanted layer is the 0.1-1 micron, the doping content of ion implanted layer is: 10 14-10 16Individual atom/cm 2
3. PN junction voltage control variodenser as claimed in claim 1 is characterized in that: the width of said groove is the 0.1-100 micron, and the degree of depth is the 0.1-50 micron.
4. the preparation method of a PN junction voltage control variodenser is characterized in that, comprises the steps:
(1) first epitaxial loayer that growth and substrate have the identical conduction type on substrate;
(2) adopt ion implantation technology, form ion implanted layer in said first epi-layer surface, the conduction type of said ion implanted layer is opposite with said first epitaxial loayer;
(3) deposit etching barrier layer on said first epitaxial loayer;
(4) adopt photoetching process to define groove, then said etching barrier layer of etching and said first epitaxial loayer form groove;
(5) utilize said etching barrier layer, adopt ion implantation technology to inject ion at said trench wall, it injects the identical of energy and implantation concentration and step (2), and the inclination angle of ion beam is made as the 7-80 degree, at said trench wall formation ion implanted layer;
(6) epitaxial growth for the second time makes second epitaxial loayer fill said groove, removes etching barrier layer afterwards;
(7) said ion implanted layer is connected to form an electrode of voltage control variodenser through metal, second epitaxial loayer also is connected to form another electrode of voltage control variodenser through metal, second epitaxial loayer and substrate are electrically connected.
5. preparation method as claimed in claim 4 is characterized in that: said step (7) specifically can be:
1) at film between illuvium on said first epitaxial loayer, then the said interlayer film of etching forms contact hole respectively on the ion implanted layer and second epitaxial loayer;
2) depositing metal is filled said contact hole and is formed contacting metal;
3) deposit front metal forms the electrode of second epitaxial loayer and the electrode of ion implanted layer respectively through photoetching and etching technics;
4) with the substrate back attenuate, deposit back metal afterwards;
5) when Chip Packaging, the electrode of back metal with said second epitaxial loayer is electrically connected.
6. like claim 4 or 5 described preparation methods, it is characterized in that: the doping content of said substrate is 10 14-10 16Individual atom/cm 2, the doping content of said first epitaxial loayer is 10 12-10 14Individual atom/cm 2, the doping content of said second epitaxial loayer is 10 1-10 14Individual atom/cm 2, the doping content of said ion implanted layer is: 10 14-10 16Individual atom/cm 2
7. like claim 4 or 5 described preparation methods, it is characterized in that: the width of said groove is the 0.1-100 micron, and the degree of depth is the 0.1-50 micron, and the thickness of said ion implanted layer is the 0.1-1 micron.
CN201010598359.5A 2010-12-21 2010-12-21 PN junction voltage-controlled varactor and preparation method thereof Active CN102569426B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299902A (en) * 2014-08-20 2015-01-21 上海华虹宏力半导体制造有限公司 Structure of MIS capacitor with capacitance being variable and manufacturing method thereof
CN112864097A (en) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
CN112993083A (en) * 2021-02-04 2021-06-18 华虹半导体(无锡)有限公司 Method for manufacturing ultra-deep photodiode
US12127389B2 (en) 2021-01-14 2024-10-22 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350111A (en) * 1993-06-10 1994-12-22 Nec Corp Varactor diode
US6153921A (en) * 1998-11-05 2000-11-28 Toko Kabushiki Kaisha Diode device
JP2001102599A (en) * 1999-09-29 2001-04-13 Sanyo Electric Co Ltd Variable capacitance semiconductor device
CN1707809A (en) * 2004-06-08 2005-12-14 Nec化合物半导体器件株式会社 Semiconductor device
US20060030114A1 (en) * 2004-08-04 2006-02-09 Ta-Hsun Yeh Method for forming junction varactor and apparatus thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350111A (en) * 1993-06-10 1994-12-22 Nec Corp Varactor diode
US6153921A (en) * 1998-11-05 2000-11-28 Toko Kabushiki Kaisha Diode device
JP2001102599A (en) * 1999-09-29 2001-04-13 Sanyo Electric Co Ltd Variable capacitance semiconductor device
CN1707809A (en) * 2004-06-08 2005-12-14 Nec化合物半导体器件株式会社 Semiconductor device
US20060030114A1 (en) * 2004-08-04 2006-02-09 Ta-Hsun Yeh Method for forming junction varactor and apparatus thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104299902A (en) * 2014-08-20 2015-01-21 上海华虹宏力半导体制造有限公司 Structure of MIS capacitor with capacitance being variable and manufacturing method thereof
CN104299902B (en) * 2014-08-20 2017-03-29 上海华虹宏力半导体制造有限公司 The structure and preparation method of the variable MIS electric capacity of capacitance
CN112864097A (en) * 2021-01-14 2021-05-28 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
CN112864097B (en) * 2021-01-14 2022-06-24 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
US12127389B2 (en) 2021-01-14 2024-10-22 Changxin Memory Technologies, Inc. Semiconductor structure and manufacturing method thereof
CN112993083A (en) * 2021-02-04 2021-06-18 华虹半导体(无锡)有限公司 Method for manufacturing ultra-deep photodiode

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