CN102569232A - Wafer-level chip size package stress buffering structure - Google Patents

Abstract

The invention relates to a wafer-level chip size package stress buffering structure, which is applied to the wafer-level chip size package technical field, and comprises a chip main body (1), a groove (2) which is arranged in the front surface of a silicon substrate of the chip main body (1) and a stress buffering medium (3) which is filled inside the groove, wherein a solder ball (4) is produced on the stress buffering medium. The wafer-level chip size package stress buffering structure is characterized in that: the stress buffering medium (3) is filled inside the groove (2). The wafer-level chip size package stress buffering structure has characteristics that: the position of the buffering medium of a traditional stress buffering layer is changed, and the buffering medium is arranged inside a silicon substrate chip to play a role in buffering the stress, so the thickness of a package structure is not increased.

Description

Stress Buffer Structure for Wafer Level Chip Scale Package

technical field

The invention relates to a wafer-level stress buffer structure, which is applied in the technical field of wafer-level chip size packaging.

Background technique

In recent years, electronic devices have developed towards multi-function and miniaturization. In order to meet this requirement, wafer-level chip size packaging has been developed. It can meet these needs while reducing production costs, and has the potential to become the next generation of packaging technology. mainstream.

A technical feature of wafer-level chip-scale packaging is that it does not use underfill. Not using underfill rubber can reduce production costs and reduce the difficulty of reprocessing in the production process. At the same time, the problem is that without underfill, the thermal mismatch between the board-level chip and the substrate will be released, and the stress will be completely borne by the solder balls, which will reduce the reliability of the solder balls.

Some researchers have developed a stress buffer layer to release stress and improve the reliability of solder balls, such as the stress buffer layer mentioned in the document 3-D structure design and reliability analysis of wafer level package with stress buffer mechanism. However, the stress buffer layer is prepared by coating the stress buffer medium on the surface of the chip, and solder balls are implanted on the stress buffer layer. This layer of stress buffering layer has a certain thickness, usually, the thicker the stress buffering layer, the better the buffering effect. However, the thickness of the stress buffer layer is limited by the processing process; at the same time, since the stress buffer layer on the chip will increase the thickness of the entire package structure, it is not conducive to the development of the package structure in the direction of miniaturization.

Contents of the invention

The object of the present invention is to provide a wafer-level chip size package stress buffering structure to overcome the above-mentioned shortcomings, and provide a wafer-level chip size package stress buffering structure with better stress buffering effect and without increasing chip thickness.

The object of the present invention is achieved like this: a kind of wafer-level chip size package stress buffering structure, comprises chip body, the groove that is made on the front side of chip body silicon base, the stress buffering medium that fills in the groove, does not increase The thickness of the package structure.

There are two types of grooves in the stress buffering structure of the wafer level chip size package of the present invention: hollow cone shape and corrugated shape. The hollow tapered groove refers to a separate groove under each solder ball, and the corrugated groove means that the grooves under the same row of solder balls are connected to form a line. In practical applications, the appropriate groove shape can be selected according to the conditional constraints.

The grooves in the wafer-level chip size packaging stress buffering structure of the present invention include making grooves under all solder balls, and each solder ball corresponds to a stress buffer layer.

The grooves in the wafer-level chip size packaging stress buffering structure of the present invention include grooves corresponding to all solder balls on the silicon chip, and grooves corresponding to key solder balls on the silicon chip. The key solder balls, such as the solder balls on the outermost edge of the chip, are prone to failure, so only grooves are made for the solder balls here, and the stress buffer layer is further made. This structure of only making grooves on the critical solder ball silicon wafer can be used in the situation that it is not suitable to make a stress buffer layer under some solder balls.

The feature of the present invention is to change the position of the buffer medium of the traditional stress buffer layer, and make the buffer medium into the groove on the chip, so as to play the role of buffer stress without increasing the thickness of the chip.

Description of drawings

Figure 1 is a schematic diagram of the initial state of the silicon base in the chip body.

FIG. 2 is a schematic diagram after grooves are made on the front side of the silicon base of the chip body.

FIG. 3 is a schematic diagram of a stress buffering structure completed by filling the stress buffering medium in the silicon-based groove of the chip body.

FIG. 4 is a schematic diagram after solder balls are formed on the stress buffer structure of the wafer-level chip size package.

Detailed ways

Fig. 4 is a wafer-level stress buffering structure provided by the present invention, which mainly consists of a chip body 1, a groove 2 made on the front side of the silicon-based material (silicon chip) of the chip body 1, and a stress buffering medium 3 filled in the groove , 4 solder balls.

The silicon-based groove of the chip body is made by wet etching. The commonly used wet etching solution is KOH//IPA (Potassium hydroxide/Isopropyl alcohol). This etching solution is carried out at 50°C, and the corrosion rate ratio of the <100> plane and the <111> plane can reach 400, forming an included angle of 54.7 degrees. The shape of the groove can be controlled by the etching time. Commonly used mask materials are SiO ₂ and Si ₃ N ₄ .

The stress-buffering medium in the groove of the chip includes a material with a small Young's modulus including PI. The common Young's modulus of PI (polyimide) and other materials is about ≤3GPa. In theory, materials with a Young's modulus equivalent to this can be used as stress buffering media.

The grooves include grooves corresponding to all solder balls on the silicon chip or corresponding to key solder balls on the silicon chip, such as the outermost solder balls on the silicon chip. Make grooves in both cases.

The material of the solder balls may be currently common Sn-Ag-Cu or the like. The manufacturing method includes laser ball planting, electroplating reflow and other methods. The maximum reflow temperature should be 10-20 degrees Celsius higher than the melting point of the solder ball material, such as about 250 degrees Celsius.

The specific manufacturing method of the described wafer-level buffer structure is in the packaging process, on the silicon substrate (as shown in Figure 1) on the front side of the chip body; Groove, as shown in Figure 2; fill the stress buffer medium, and finally, as shown in Figure 4, make solder balls on the stress buffer medium.

Claims (6)

1. A wafer-level chip size packaging stress buffering structure, comprising a chip body (1), a groove (2) made on the front side of the silicon substrate of the chip body (1), and a stress buffering medium (3) filled in the groove , making solder balls (4) on the stress buffer medium. 2. The structure according to claim 1, characterized in that the grooves are hollow conical and corrugated. 3. The structure according to claim 2, characterized in that the hollow tapered groove is a separate groove under each solder ball; the corrugated groove is that the grooves under the same row of solder balls are connected to form a line. 4. The structure according to claim 1 or 2, characterized in that the grooves include grooves corresponding to all solder balls on the silicon chip or grooves corresponding to the solder balls on the outermost edge of the silicon chip on the silicon chip. groove. 5. The structure according to claims 1-3, characterized in that said stress buffering medium comprises a material with Young's modulus including PI and small. 6. The structure according to claim 3, characterized in that the Young's modulus of said material is ≤ 3GPa.

Images