CN102566976B - Register renaming system and method for managing and renaming registers - Google Patents
Register renaming system and method for managing and renaming registers Download PDFInfo
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- CN102566976B CN102566976B CN201010607221.7A CN201010607221A CN102566976B CN 102566976 B CN102566976 B CN 102566976B CN 201010607221 A CN201010607221 A CN 201010607221A CN 102566976 B CN102566976 B CN 102566976B
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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Abstract
The invention relates to a register renaming system and method for managing and renaming registers. The invention specifically provides the register renaming system for managing and renaming the registers by adopting multiple renamed register queues, and the system comprises a physical register group, a register alias table (RAT), an architecture register mapping table (ARMT), a select finger of the renamed register queues, a decoder, a logic register renaming device, an RAT modifying device and an updating device of the renamed register queues. In addition, the invention further provides the method for managing and renaming the registers by adopting the multiple renamed register queues. According to the technical scheme provided by the invention, renaming operation can be simultaneously performed on the multiple registers within a same period, the implementation method is simple, the time cost is small, and the register renaming system and method are suitable for superscalar microprocessors with higher transmission width.
Description
Technical field
The present invention relates to micro-processor architecture technical field, particularly a kind of register rename system and method that adopts a plurality of rename register queues.
Background technology
Modern micro-processor architecture, has adopted superscale (Super Scale) technology mostly,, in one-period, has many streamlines in many instructions of executed in parallel.Register renaming (Register Renaming) technology is one of gordian technique of superscalar microprocessor, it is by being mapped to same logic register the mode of a plurality of physical registers, the operating writeafterread of the program that solved (WAR), with to write (WAW) data relevant, has improved the executed in parallel ability of instruction greatly.
Wherein a kind of implementation of register renaming operation is for one group of physical register, adopt architecture register mapping table (Architecture Register Mapping Table, referred to as ARMT) to preserve the corresponding relation of physical register and logic register.Described logic register, refer to instruction register used when programming, in adopting the microprocessor of register renaming technology, the same register address of different instruction is the corresponding same register physically existing not necessarily, therefore the concept of introducing logic register is carried out presentation directives's register used, and is different from the register physically existing truly.Described physical register, is in esse register circuit physically in microprocessor, processor operation not in the same time, can be corresponding from different logic registers.When processor moves, the corresponding a plurality of physical registers of same logic register possibility, but what only have a physical register preservation is the result of having confirmed, described confirmation result, it is the execution result that resequencing buffer ROB submits instruction after instruction in order to, no matter how the inner structure of microprocessor realizes, the content of this physical register be all with the programming model of carrying out in order in logic register be unified, claim that in this article these physical registers of preserving the results of confirmations are architecture register.Architecture register mapping table is preserved is exactly to be used as architecture register now and to preserve those physical registers of the confirmation result of corresponding logic register.
Rename engine replaces the logic register address in instruction with physical register address, and performance element is obtained operand or operand is write back in physical register according to this physical register address from physical register.Those physical registers that are not taken as architecture register use are called rename register, if instruction has destination register, when rename, will find so a rename register not used, with the physical register address of this rename register, replace the destination register logical address of instruction.That is to say, if instruction has destination register, will find a rename register not used and its destination register for instruction (logic register) is mapped.
Lifting along with superscalar microprocessor transmitting width, require rename engine in one-period, can carry out repeatedly rename operation, this just requires can search the rename register of a plurality of free time in one-period, and larger transmitting width has also required more physical register can be used to register renaming operation, increased the workload that rename engine carries out idle register search, made rename engine become the bottleneck that affects microprocessor frequency upgrading.
Search for idle register, traditional search way will be searched for next idle register after finding an idle register again, the search of different idle registers is the relation of serial in sequential, be similar to the carry chain of totalizer, therefore when physical register number to be selected much and in the situation of a plurality of Search Results of requirement acquisition can produce very large time delay, affect the lifting of operation frequency of microprocessor.
In order to improve the seek rate to idle physical register, there are some existing achievements in research, such as register piecemeal and adopt bidirectional research, referring to Chinese Patent Application No. 200910004886.6, patent name < < is used register rename system and the method > > thereof of polylith physical register mapping table.But physical register is divided into a plurality of, and the physical register of different masses can not exchange, will guarantee that the idle register number of each piece equates to avoid the physical register because of a certain all used and block rename operation and carry out substantially; And whether bidirectional research also needs that each block of registers is done to idle register number and whether is more than or equal to 2 judgement can be overlapping with the result of checking bidirectional research, this,, with regard to needing a complicated logic to judge the idle physical register number of each piece, has increased the time delay in sequential.
Summary of the invention
The object of the invention is to overcome the bottleneck of prior art, improves the speed of a large amount of physical registers being carried out repeatedly to register renaming operation.
In order to achieve the above object, according to an aspect of the present invention, provide a kind of register rename system that adopts a plurality of rename register queue management rename registers, described system comprises:
Physical register set, be included in microprocessor when operation by be dynamically mapped as for preserve the instruction of having submitted to result architecture register and for preserve submit to before the rename register of instruction results, described rename register is divided into described a plurality of rename register queue, each rename register queue comprises multinomial, and every comprises again register free time/use sign, physical register address and uses the fundamental block numbering at the instruction place of this physical register;
Register alias table RAT, described RAT preserves up-to-date logic register and the mapping relations between physical register, and the source operand register of preparing to carry out the instruction of rename is usingd the content of register alias table as the foundation of rename;
Architecture register mapping table ARMT, indication which physical register under current state is to be taken as architecture register to use, the logic register that also preservation has been identified and the mapping relations of physical register;
Rename register queue select finger, is used to indicate the current physical register that is used to rename operation from which the rename register queue in described a plurality of rename register queues;
Code translator, for providing the one or more logic registers address that need to carry out rename operation;
Register renaming device, for carrying out rename operation to described one or more logic registers;
RAT modifier, for the results modification RAT operating according to rename;
Rename register queue updating device, for rename register queue is upgraded to operation, and
ARMT updating device, for upgrading operation to AMRT.
According to the present invention, described register free time/use indicates and represents that this physical register is for rename, operate or do not used, and when microprocessor resets, free time/use sign of all items is all expressed as the free time, described physical register address is this current corresponding physical register address, and at any time, the physical register address of storing in all rename register queues can not repeated, described fundamental block numbering is when this corresponding physical register in physical register address is used, use the numbering of the residing fundamental block of instruction of this physical register, in there is no the microprocessor of Tapped Delay groove, fundamental block is a branch instruction and the set of arriving all instructions before of its last branch instruction, in having the microprocessor of Tapped Delay groove, this set also will add the instruction postponing in groove, when idle/use is denoted as the free time, fundamental block numbering is nonsensical, when use is denoted as use, whether fundamental block numbering will be cancelled for decision instruction when branch prediction is failed, the rename register that the instruction being cancelled is used will be released, this register free time/use sign of corresponding item in rename register queue is become the free time by use.
According to system of the present invention, wherein said register renaming device carries out rename operation by following operation to described one or more logic registers:
(i) a plurality of rename register queues described in parallel search, find out the physical register address of an idle physical register from each queue;
(ii) according to rename register queue select finger, the idle physical register address of finding is assigned to first logic register that need to do rename operation from the specified rename register queue of this pointer;
(iii) free time/use sign of the physical register for rename is made as to use, and
(iv) the physical register for rename is made as to the fundamental block numbering under the instruction that equals to use this physical register in the fundamental block numbering of rename register queue,
(v) if there are a plurality of logic registers need to carry out rename operation, register queue select finger is added to 1, and repeating step (i)-operation (iv).
According to system of the present invention, the destination register physical address of the instruction that described rename register queue updating device will be submitted to according to ROB searches out the item that needs renewal in rename register queue, and with the physical address that uses this destination register logical address to read from ARMT, the item searching is upgraded to operation.Particularly, described rename register queue updating device upgrades operation by following steps to rename register queue:
(i) the physical register address corresponding with this destination register logical address that the destination register logical address of the instruction that will submit to according to ROB finds in ARMT;
(ii) the destination register physical address of the instruction that will submit to according to ROB finds the item of preserving this destination register physical address in each rename register queue;
(iii) change the physical register address of preserving the item of described destination register physical address in rename register queue into find physical register address from ARMT; And
(iv) change free time/use sign of preserving the item of described destination register physical address in rename register queue into the free time, and
(v) if there is a plurality of item to need to upgrade in rename register queue, repeating step (i)-operation (iv).
According to system of the present invention, the destination register physical address of wherein said ARMT updating device by the instruction that the corresponding physical register of destination register logical address that find and described instruction address replaced with to ROB will submit in ARMT completes the renewal of AMRT operated.
According to system of the present invention, wherein said register renaming device is from the queue of rename register queue select finger appointment, the order increasing progressively according to numbering is searched successively and will be assigned to the idle physical register of the logic register that need to do rename operation from each rename register queue, after queue numbering is increased to maximum, can backrush carry out to minimum numbering.
According to system of the present invention, wherein said physical register set comprises M+N physical register, wherein M is for be dynamically mapped as the number of the physical register of architecture register when microprocessor moves, and N is the number that is mapped as the outer physical register for rename operation of physical register of architecture register.
According to system of the present invention, the item number of wherein said register alias table RAT and architecture register mapping table ARMT is all M, and each corresponds respectively to a logic register.
According to system of the present invention, the content of wherein said rename register queue select finger is exactly the numbering that will be used to the rename register queue under the physical register of logic register rename operation, every pair of logic register is done rename operation and rename register queue select finger will be added to 1, to select next rename register queue.
According to system of the present invention, the number of wherein said a plurality of rename register queues is more than or equal to the number of times of the rename operation that can carry out at most within a clock period of microprocessor.
According to system of the present invention, the physical register address of preserving in each in wherein said a plurality of rename register queues is variable when microprocessor moves.
According to system of the present invention, wherein, for described a plurality of rename register queues, the item number of each queue can equate.
According to system of the present invention, wherein said a plurality of rename register queue, the item number of each queue can be unequal, but this situation only should appear under the condition that can not be divided exactly by rename register queue number for the physical register number of rename operation.
According to system of the present invention, wherein in the situation that can not be divided exactly by rename register queue number for the physical register number of rename operation, the direction that remaining register after dividing exactly is increased according to rename register queue select finger is distributed to from numbering the zero rename register queue starting, until distribute successively by one of every queue.
According to system of the present invention, wherein the content in architecture register mapping table can not change because of the abnormal or branch prediction mistake except resetting.
In addition, a kind of method that adopts a plurality of rename register queue management rename registers is also provided, described rename register is divided into described a plurality of rename register queue, each rename register queue comprises multinomial, every comprises again register free time/use sign, physical register address and uses the fundamental block numbering at the instruction place of this physical register, and described method comprises:
Use code translator that the one or more logic registers address that need to carry out rename operation is provided;
Described one or more logic registers are carried out to rename operation;
According to the results modification register alias table RAT of rename operation, wherein said RAT preserves up-to-date logic register and the mapping relations between physical register, and the source operand register of preparing to carry out the instruction of rename is usingd the content of register alias table as the foundation of rename;
When instruction is submitted to, destination register logical address and the physical address of the instruction that will submit to according to resequencing buffer ROB upgrade operation to rename register queue, and
When instruction is submitted to, destination register logical address and the physical address of the instruction that will submit to according to ROB upgrade operation to architecture register mapping table AMRT.
The method according to this invention, wherein by described one or more logic registers being carried out to rename operation to finish drilling:
(i) a plurality of rename register queues described in parallel search, find out the physical register address of an idle physical register from each queue;
(ii) according to rename register queue select finger, the idle physical register address of finding from the specified rename register queue of this pointer is assigned to first logic register that need to do rename operation, wherein said rename register queue select finger is used to indicate the current physical register that is used to rename operation from which the rename register queue in described a plurality of rename register queues;
(iii) free time/use sign of the physical register for rename is made as to use, and
(iv) the physical register for rename is made as to the fundamental block numbering under the instruction that equals to use this physical register in the fundamental block numbering of rename register queue, and
(v) if there are a plurality of architecture registers need to carry out rename operation, register queue select finger is added to 1, and repeating step (i)-operation (iv).
Wherein, when architecture register is carried out to rename, if the selected rename register queue of rename register queue select finger does not find idle physical register, microprocessor can stop carrying out rename operation, will treat that the instruction of rename and instruction below thereof maintain until there is new idle physical register found.
The method according to this invention, the destination register physical address of the instruction that wherein will submit to according to ROB searches out the item that needs renewal in rename register queue, and with the physical address that uses this destination register logical address to read from ARMT, the item searching is upgraded to operation.Particularly, by following steps, rename register queue is upgraded to operation:
(i) the destination register logical address of the instruction that will submit to according to ROB finds the physical register address corresponding with this destination register logical address in ARMT, the architecture register that wherein said ARMT preservation has been identified and the mapping relations of physical register;
(ii) the destination register physical address of the instruction that will submit to according to ROB finds the item of preserving this destination register physical address in each rename register queue;
(iii) change the physical register address of preserving the item of described destination register physical address in rename register queue into find physical register address from ARMT; And
(iv) change free time/use sign of preserving the item of described destination register physical address in rename register queue into the free time, and
(v) if there is a plurality of item to need to upgrade in rename register queue, repeating step (i)-operation (iv).
The method according to this invention, further comprises by the corresponding physical register of destination register logical address that find and described instruction address is replaced with to the destination register physical address of the instruction that ROB will submit in ARMT and completes the renewal of AMRT is operated.
The method according to this invention, further comprise from the queue of rename register queue select finger appointment, the order increasing progressively according to numbering is searched successively and will be assigned to the idle physical register of the logic register that need to do rename operation from each rename register queue, after queue numbering is increased to maximum, can backrush carry out to minimum numbering.
The method according to this invention, wherein said physical register set comprises M+N physical register, wherein M is for be dynamically mapped as the number of the physical register of architecture register when microprocessor moves, and N is the number that is mapped as the outer physical register for rename operation of physical register of architecture register.
The method according to this invention, the item number of wherein said register alias table RAT and architecture register mapping table ARMT is all M, each corresponds respectively to a logic register.
The method according to this invention, the content of wherein said rename register queue select finger is exactly the numbering that will be used to the rename register queue under the physical register of logic register rename operation, every pair of logic register is done rename operation and rename register queue select finger will be added to 1, to select next rename register queue.Owing to can carry out repeatedly rename operation within a clock period, the number of times that after the clock period, the added value of rename register queue select finger operates for the rename of carrying out within this cycle.
The method according to this invention, the number of wherein said a plurality of rename register queues is more than or equal to the number of times of the rename operation that can carry out at most within a clock period of microprocessor.When the number of rename register queue is greater than the number of times of the rename operation that can carry out at most in the clock period at microprocessor, situation for same physical register number can make the length of each rename register queue shorter, thereby reduces the search time of queue.
The method according to this invention, the physical register address of preserving in each in wherein said a plurality of rename register queues is variable when microprocessor moves.
The method according to this invention, wherein, for described a plurality of rename register queues, the item number of each queue can equate.
The method according to this invention, wherein said a plurality of rename register queue, the item number of each queue can be unequal, but this situation only should appear under the condition that can not be divided exactly by rename register queue number for the physical register number of rename operation.
The method according to this invention, wherein in the situation that can not be divided exactly by rename register queue number for the physical register number of rename operation, the direction that remaining register after dividing exactly is increased according to rename register queue select finger is distributed to from numbering the zero rename register queue starting, until distribute successively by one of every queue.
The method according to this invention, wherein the content in architecture register mapping table ARMT can not change because of the abnormal or branch prediction mistake except resetting.
In addition, according to the present invention, register alias table RAT has recovery logic, for when extremely producing or while there is branch prediction mistake, cancel all or part of instruction of carrying out and cancel being cancelled the register renaming operation of instruction simultaneously, register alias table is returned to the instruction rename state before that is cancelled.
According to the present invention, described rename register queue select finger has recovery logic, and it returns to by rename register queue select finger the instruction rename state before that is cancelled when abnormal generation or branch prediction mistake.
As mentioned above, physical register set comprises all physical registers, comprise and be mapped as the physical register of architecture register and the physical register operating for rename, and the physical register comprising in rename register queue can change when operation, all physical registers all may appear in any one rename register queue, the physical register that may not belong to any one queue is originally placed in one of them queue, also may be placed in another queue by original physical register in a queue, but the physical register in different queue is all nonoverlapping at any time, and item number in all rename register queues is added up, be exactly the physical register quantity that can be used to rename operation in microprocessor, comprise idle and used.
Further, as mentioned above, rename register queue is from the queue of rename register queue select finger appointment, the order increasing progressively according to numbering is successively to the destination register in requisition for carrying out rename operation, numbering is increased to and can be wound up into minimum numbering after maximum and carries out, such as hypothesis has 4 queues, do rename operation will to four registers, current rename register multi-columns selecting pointer is 1, need to make the registers that rename operates for these four, according to the order of affiliated instruction, use and be numbered 1 respectively from front to back, 2, 3, the lookup result of 0 rename register queue carries out rename operation.
What further, when register renaming, each rename register queue was always used successively according to the order of numbering.。
Further, when having instruction to be cancelled because of abnormal or branch prediction mistake, be RAT, all rename register queues and rename register queue select finger return to does rename operation state before to these instructions.The recovery of RAT and rename register queue select finger can be adopted as the form that each fundamental block retains a copy, when occurring when instruction is cancelled to cover currency with copy.The restoration methods of rename register queue is that the fundamental block numbering in each in queue is compared with fundamental block cancelling signal.The cancellation of instruction be take fundamental block and is carried out as unit, fundamental block cancelling signal indicates the instruction in which fundamental block to be cancelled, if the fundamental block numbering to a certain in row is to belong to the fundamental block that will be cancelled, this free time/use sign will be reset as the free time, thereby realize the rename register release that is cancelled instruction.As for this fundamental block numbering, due to physical register during in idle condition fundamental block numbering be nonsensical, so do not need to recover.
Further, when the physical register being used is submitted in the instruction of using it, the position of the physical register that before can carrying out with this instruction, the corresponding physical register replacement of its target architecture register is used by the rename of this instruction operation in rename register queue.Such as the 3rd physical register of the rename register queue of numbering 2 used in this instruction, its physical register address is PR11, the target logic register of this instruction is R8, the physical register that R8 is corresponding in architecture register mapping table is PR19, when this instruction is submitted to, logic register R8 is remapped to PR11, and the 3rd physical register of the rename register queue of numbering 2 becomes PR19 from PR11, be that PR19 is deleted the 3rd (position at former PR11 place) in the rename register queue that moves into numbering 2 from architecture register mapping table, and PR11 is moved in architecture register mapping table.
The present invention has following advantages:
The present invention uses the rename register queue of a plurality of non-overlapping copies to carry out idle register to a same physical register set simultaneously and searches, physical register contained in each queue does not have address range limit, by rename register queue select finger, can determine very easily the idle physical register selected and the corresponding relation of waiting for the logic register of rename from physical register set, and not need to know in each group, to also have how many idle physical registers.
In same period, need a plurality of registers to carry out the number of rename operation or physical register when a lot, the present invention is not by adopting bidirectional research algorithm to improve search speed, but by increasing number of queues, reduce the workload that each queue searches and reduce the queue search time.Because the rename register queue Search Results that carries out according to rename register queue pointer is selected and the idle physical register search of rename register queue inside is to carry out simultaneously, deviser can determine the number of number of queues and the length of queue according to actual conditions, reach selection and the balance in time of the search in queue of Search Results between queue, thereby improve the processing speed of rename engine.
Accompanying drawing explanation
Fig. 1 is general structure schematic diagram of the present invention.
Fig. 2 shows according to the state separately before rename register queue and architecture register mapping table are upgraded of the present invention.
Fig. 3 shows according to the state separately after rename register queue and architecture register mapping table are upgraded of the present invention.
Fig. 4 shows rename register queue according to the present invention at the state occurring before fundamental block is cancelled.
Fig. 5 shows rename register queue according to the present invention at the state occurring after fundamental block is cancelled.
Fig. 6 is for showing according to the process flow diagram of the method for being invented.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
In the present embodiment, physical register set comprises 64 physical registers, wherein there are 32 physical registers to be mapped as architecture register, described architecture register, be the physical register of preserving the logic register content of confirming, corresponding one by one with logic register, 32 physical registers are in addition rename register, described rename register is for the data of eliminating between instruction are correlated with and the physical register of the execution result of holding instruction temporarily when microprocessor moves.Especially, physical register in the present invention is not limited to 64, in general, described physical register set can comprise M+N physical register, wherein M is for be dynamically mapped as the number of the physical register of architecture register when microprocessor moves, and N is the number that is mapped as the outer physical register for rename operation of physical register of architecture register.In this case, the item number of register alias table RAT and architecture register mapping table ARMT is all M, and each corresponds respectively to a logic register.
Each cycle of rename engine can be carried out at most 4 renames operation 101,102,103 and 104, and each cycle of ROB also can be submitted at most 4 instructions to.
In the present embodiment, have 4 rename register queues 105,106,107 and 108, each queue comprises 8 physical registers.According to the present invention, it is variable that the number of a plurality of rename register queues is more than or equal to the physical register address of preserving in the number of times of the rename operation that can carry out at most within a clock period of microprocessor and each in described a plurality of rename register queue when microprocessor moves.When the number of rename register queue is greater than the number of times of the rename operation that can carry out at most in the clock period at microprocessor, situation for same physical register number can make the length of each rename register queue shorter, thereby reduces the search time of queue.Although please note and represented that each rename register team comprises equal physical register quantity (that is, having equal item number) above, the present invention is not limited to this.In a plurality of rename register queues, the item number of each queue can be unequal.This is in the situation that can not be divided exactly and there will be by rename register queue number for the physical register number of rename operation.In this case, the direction that the remaining register after dividing exactly can be increased according to rename register queue select finger is distributed to from numbering the zero rename register queue starting, until distribute successively by one of every queue.Continuation is with reference to Fig. 1, four rename register queues are searched idle register separately simultaneously, and which in four renames operations 101,102,103 and 104 that are used to be as shown in Figure 1 the result of searching determined by four multi-selection devices 109,110,111 and 112 values according to rename register queue select finger.According to the present invention, use code translator that the address that need to carry out the logic register of rename operation is also provided, for clarity sake, code translator not shown in Figure 1.Although provide with code translator the address that need to carry out the logic register of rename operation in the present invention, those skilled in the art can expect providing the alternate manner of the address of the logic register that need to carry out rename operation.
Illustrate below and how logic register is carried out to rename operation.First, as mentioned above, four rename register queues are searched idle register separately simultaneously, find out the physical register address of an idle physical register from each queue; After this, according to rename register queue select finger, the idle physical register address of finding is assigned to first logic register (that is, carrying out the first rename operation) that need to do rename operation from the specified rename register queue of this pointer; After this free time/use sign of this physical register for rename is made as to the fundamental block numbering of using and this physical register for rename being made as in the fundamental block numbering of rename register queue under the instruction that equals to use this physical register.If also have a plurality of logic registers need to carry out rename operation, register queue select finger is added to 1, and repeat aforesaid operations (that is, carrying out the second rename operation until quadruple naming operation).
Note, in Fig. 1, first three rename operates 101,102, and to be sent to source operand register renaming logic relevant for solving within this cycle the data between instruction with 103 rename result.If exist write-then-read data relevant between the instruction etc. pending rename, so concerning the target architecture register that uses instruction above as the instruction of source operand register, the physical address of source operand register is by no longer from register alias table but from 109,110 or 111 rename result.
All 4 rename results all will be sent in register alias table for upgrading register alias table.
When ROB submits instruction to, from architecture register mapping table, find the corresponding physical register of the destination register logical address address of submitting instruction to, the item at the destination register physical address place of the instruction that search is submitted in rename register queue, be used in the physical register address of reading in architecture register mapping table and substitute original value, and also replace the physical register address of submitted instruction the physical register address of original storage in architecture register mapping table.
Specifically describe the process of rename register queue and architecture register mapping table of upgrading below when instruction is submitted to.
Fig. 2 and Fig. 3 shown respectively the state before rename register queue and architecture register mapping table upgrade and upgrade after state.In Fig. 2, left side is 4 ROB items to be submitted to, and the order of submission is from the bottom to top.Wherein upgrading relevant three with rename register queue is respectively the item 201,202,203 and 204 of preserving destination register significance bit, preserves the item 205,206,207 and 208 and the item 209,210,211 and 212 of preserving destination register physical address of destination register logical address.
First judge the destination register significance bit in first submitted ROB item, as shown in the figure, the content in 201 is 1, and this represents that this submitted instruction used destination register.According to the destination register logical address R2 being kept in 205, in architecture register mapping table ARMT, find the item 217 of preserving the physical register address PR13 corresponding with R2, after this according to the destination register physical address PR19 that is kept at the instruction in 209, in rename register queue 2, find item 213, the physical register address PR19 preserving in item 213 is consistent with the destination register physical address PR19 preserving in 209, wherein 213 the left side is physical register address, the right is idle/use sign, be 1 at present, represent that this physical register has been used to rename operation, so 213 fundamental block numbering because do not use and draw in renewal.Now, the content PR13 of item 217 is deposited in 213, and use sign to be made as 0(free time of 213 to represent the free time), and 209 content PR19 is deposited in 217, complete register renaming queue and the architecture register mapping table renewal work of first submitted ROB item. simultaneously
Judge the destination register significance bit of second submitted ROB item, as shown in the figure, the content in 202 is 1 again, represents that this submitted instruction used destination register.According to the destination register logical address R9 being kept in 206, in architecture register mapping table ARMT, find the item 218 of preserving the physical register address PR4 corresponding with R9, after this according to the destination register physical address PR19 that is kept at the instruction in 210, find item 214 in rename register queue 3, the physical register address PR3 preserving in item 214 is consistent with the destination register physical address PR3 preserving in 210.Now, the content PR4 of item 218 is deposited in 214, and use sign to be made as 0(free time of 214 to represent the free time), and 210 content PR3 is deposited in 218, complete register renaming queue and the architecture register mapping table renewal work of second submitted ROB item. simultaneously
Then judge the 3rd submitted destination register significance bit, as shown in the figure, the content in 203 is 0, represents that this instruction do not used destination register, therefore does not also need to upgrade operation.
Finally judge the 4th submitted destination register significance bit, as described in Figure, the content in 204 is 1, represents that this submitted instruction used destination register.According to the destination register logical address R8 being kept in 206, in architecture register mapping table ARMT, find the item 219 of preserving the physical register address PR16 corresponding with R8, after this according to the destination register physical address PR12 that is kept at the instruction in 212, find item 215 in rename register queue 0, the physical register address PR12 preserving in item 215 is consistent with the destination register physical address PR12 preserving in 212.215 form is the same with 213 and 214.Now, the content of item 219 is deposited in 215, and use sign to be made as 0(free time of 215 to represent the free time), and 212 content PR12 is deposited in 219, complete register renaming queue and the architecture register mapping table renewal work of the 4th submitted item. simultaneously
Rename register queue after renewal completes architecture register mapping table state as shown in Figure 3.
With reference to Fig. 4 and Fig. 5, show respectively the state of rename register queue according to the present invention before instruction is cancelled.
Fig. 5 has expressed the state of rename register queue according to the present invention before instruction generation fundamental block is cancelled and after cancelling.
Suppose to have branch prediction mistake to occur, the part fundamental block moving in microprocessor will be cancelled, Fig. 4 represents that rename register queue is at the state occurring before fundamental block is cancelled, now rename register queue select finger points to rename register queue 1, and effectively fundamental block has the 1st, 2,3,4,5 five.As known in the field, described fundamental block represents in the instruction stream of the actual execution of microprocessor, to the content between a upper branch instruction, in having the microprocessor of Tapped Delay groove, also comprise the instruction in the delay groove of this branch instruction before branch instruction and this branch instruction.That is to say, what each fundamental block comprised is the program segment that an inside does not have branch, the base unit that while being also branch prediction mistake, instruction is cancelled, and the meaning of cancelling a certain fundamental block is exactly that all instructions in this fundamental block all will be cancelled.Suppose the branch instruction predictions mistake in fundamental block 2, will cancel the 3rd, 4,5 three instructions in fundamental block, and regain the rename operation that they are carried out.Each of rename register all comprises its corresponding fundamental block numbering, when recovering rename register queue, to see whether the corresponding fundamental block of this numbering will be cancelled, in this example, fundamental block is numbered 3,4,5 will be cancelled, and free time/uses that is about to them identifies and be made as the free time.
Fig. 5 is the state after recovering, and rename register queue select finger also will be resumed, and can retain a copy by the rename register queue select finger when finishing for each fundamental block, calls this copy and realize when recovery.
Finally it should be noted that: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only, although the present invention is had been described in detail with reference to above-described embodiment, those of ordinary skill in the art is to be understood that: still can modify or be equal to replacement the present invention, and not departing from any modification or partial replacement of the spirit and scope of the present invention, it all should be encompassed in the middle of claim scope of the present invention.
Claims (4)
1. a register rename system that adopts a plurality of rename register queue management rename registers, described system comprises:
Physical register set, be included in microprocessor when operation by be dynamically mapped as for preserve the instruction of having submitted to result architecture register and for preserve submit to before the rename register of instruction results, described rename register is divided into described a plurality of rename register queue, each rename register queue comprises multinomial, and every comprises again register free time/use sign, physical register address and uses the fundamental block numbering at the instruction place of this physical register;
Register alias table RAT, described RAT preserves up-to-date logic register and the mapping relations between physical register, and the source operand register of preparing to carry out the instruction of rename is usingd the content of register alias table as the foundation of rename;
Architecture register mapping table ARMT, indication which physical register under current state is to be taken as architecture register to use, the logic register that also preservation has been identified and the mapping relations of physical register;
Rename register queue select finger, is used to indicate the current physical register that is used to rename operation from which the rename register queue in described a plurality of rename register queues;
Code translator, for providing the one or more logic registers address that need to carry out rename operation;
Register renaming device, for carrying out rename operation to described one or more logic registers;
RAT modifier, for the results modification RAT operating according to rename;
Rename register queue updating device, for rename register queue is upgraded to operation, and
Architecture register mapping table ARMT upgrades pointer, for architecture register mapping table ARMT is upgraded to operation;
Wherein said register renaming device carries out rename operation by following operation to described one or more logic registers:
(i) a plurality of rename register queues described in parallel search, find out the physical register address of an idle physical register from each queue;
(ii) according to rename register queue select finger, the idle physical register address of finding is assigned to first logic register that need to do rename operation from the specified rename register queue of this pointer;
(iii) free time/use sign of the physical register for rename is made as to use, and
(iv) the physical register for rename is made as to the fundamental block numbering under the instruction that equals to use this physical register in the fundamental block numbering of rename register queue,
(v) if there are a plurality of logic registers need to carry out rename operation, register queue select finger is added to 1, and repeating step (i)-operation (iv);
Wherein said rename register queue updating device upgrades operation by following steps to rename register queue:
(a) the physical register address corresponding with this destination register logical address that the destination register logical address of the instruction that will submit to according to resequencing buffer ROB finds in architecture register mapping table ARMT;
(b) the destination register physical address of the instruction that will submit to according to resequencing buffer ROB finds the item of preserving this destination register physical address in each rename register queue;
(c) change the physical register address of preserving the item of described destination register physical address in rename register queue into find physical register address from architecture register mapping table ARMT;
(d) change free time/use sign of preserving the item of described destination register physical address in rename register queue into the free time, and
(e) if there is a plurality of item to need to upgrade in rename register queue, the operation of repeating step (a)-(d);
Wherein said architecture register mapping table ARMT upgrades the destination register physical address of pointer by the instruction that find and the corresponding physical register of the destination register logical address described instruction that will submit to according to resequencing buffer ROB address replaced with to resequencing buffer ROB will submit in architecture register mapping table ARMT to be completed the renewal of ARMT is operated.
2. according to the system of claim 1, the content of wherein said rename register queue select finger is exactly the numbering that will be used to the rename register queue under the physical register of logic register rename operation, every pair of logic register is done rename operation and rename register queue select finger will be added to 1, to select next rename register queue.
3. a method that adopts a plurality of rename register queues management rename registers, described rename register is divided into described a plurality of rename register queue, each rename register queue comprises multinomial, every comprises again register free time/use sign, physical register address and uses the fundamental block numbering at the instruction place of this physical register, and described method comprises:
Use code translator that the one or more logic registers address that need to carry out rename operation is provided;
Described one or more logic registers are carried out to rename operation;
According to the results modification register alias table RAT of rename operation, wherein said RAT preserves up-to-date logic register and the mapping relations between physical register, and the source operand register of preparing to carry out the instruction of rename is usingd the content of register alias table as the foundation of rename;
When instruction is submitted to, destination register logical address and the physical address of the instruction that will submit to according to resequencing buffer ROB upgrade operation to rename register queue, and
When instruction is submitted to, destination register logical address and the physical address of the instruction that will submit to according to resequencing buffer ROB upgrade operation to architecture register mapping table ARMT;
Wherein by described one or more logic registers being carried out to rename operation to finish drilling:
(i) a plurality of rename register queues described in parallel search, find out the physical register address of an idle physical register from each queue;
(ii) according to rename register queue select finger, the idle physical register address of finding from the specified rename register queue of this pointer is assigned to first logic register that need to do rename operation, wherein said rename register queue select finger is used to indicate the current physical register that is used to rename operation from which the rename register queue in described a plurality of rename register queues;
(iii) free time/use sign of the physical register for rename is made as to use, and
(iv) the physical register for rename is made as to the fundamental block numbering under the instruction that equals to use this physical register in the fundamental block numbering of rename register queue, and
(v) if there are a plurality of architecture registers need to carry out rename operation, register queue select finger is added to 1, and repeating step (i)-operation (iv);
Wherein by following steps, rename register queue is upgraded to operation:
(a) the destination register logical address of the instruction that will submit to according to resequencing buffer ROB finds the physical register address corresponding with this destination register logical address in architecture register mapping table ARMT, the architecture register that wherein said architecture register mapping table ARMT preservation has been identified and the mapping relations of physical register;
(b) the destination register physical address of the instruction that will submit to according to resequencing buffer ROB finds the item of preserving this destination register physical address in each rename register queue;
(c) change the physical register address of preserving the item of described destination register physical address in rename register queue into find physical register address from architecture register mapping table ARMT; And
(d) change free time/use sign of preserving the item of described destination register physical address in rename register queue into the free time, and
(e) if there is a plurality of item to need to upgrade in rename register queue, the operation of repeating step (a)-(d);
Wherein by that find and the corresponding physical register of the destination register logical address described instruction that will submit to according to resequencing buffer ROB address are replaced with to the destination register physical address of the instruction that resequencing buffer ROB will submit in architecture register mapping table ARMT, complete the renewal of ARMT is operated.
4. according to the method for claim 3, further comprise from the queue of rename register queue select finger appointment, the order increasing progressively according to numbering is searched successively and will be assigned to the idle physical register of the logic register that need to do rename operation from each rename register queue, after queue numbering is increased to maximum, can backrush carry out to minimum numbering.
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| GB2502857B (en) | 2013-03-05 | 2015-01-21 | Imagination Tech Ltd | Migration of data to register file cache |
| CN104516726B (en) * | 2013-09-27 | 2018-08-07 | 联想(北京)有限公司 | A kind of method and device of instruction processing |
| CN105278915B (en) * | 2015-01-15 | 2018-03-06 | 北京国睿中数科技股份有限公司 | The superscalar processor that operation is checked out based on decoupling instructs distributor |
| US9946549B2 (en) * | 2015-03-04 | 2018-04-17 | Qualcomm Incorporated | Register renaming in block-based instruction set architecture |
| US10108417B2 (en) * | 2015-08-14 | 2018-10-23 | Qualcomm Incorporated | Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor |
| CN107688544B (en) * | 2016-12-23 | 2020-02-11 | 北京国睿中数科技股份有限公司 | Method for recovering alias table of register |
| CN110647361B (en) * | 2019-09-09 | 2021-08-27 | 中国人民解放军国防科技大学 | Method and device for acquiring idle physical register |
| CN111221575A (en) * | 2019-12-30 | 2020-06-02 | 核芯互联科技(青岛)有限公司 | Register renaming method and system for out-of-order high-performance processor |
| CN111506347B (en) * | 2020-03-27 | 2023-05-26 | 上海赛昉科技有限公司 | Renaming method based on instruction read-after-write related hypothesis |
| WO2022199035A1 (en) * | 2021-03-22 | 2022-09-29 | 广东赛昉科技有限公司 | Renaming method and system for fixed-constant-related instruction |
| CN113254079B (en) * | 2021-06-28 | 2021-10-01 | 广东省新一代通信与网络创新研究院 | A method and system for implementing self-incrementing instructions |
| CN116339830B (en) * | 2023-05-26 | 2023-08-15 | 北京开源芯片研究院 | Register management method and device, electronic equipment and readable storage medium |
| CN117492844B (en) * | 2023-12-29 | 2024-03-29 | 北京微核芯科技有限公司 | Register renaming method, device and storage medium |
| CN117931293B (en) * | 2024-03-22 | 2024-06-28 | 芯来智融半导体科技(上海)有限公司 | Instruction processing method, device, equipment and storage medium |
| CN118656229B (en) * | 2024-08-22 | 2024-12-20 | 此芯科技(北京)有限公司 | A method, device, storage medium and electronic device for implementing synchronous multithreading |
| CN119003004B (en) * | 2024-10-18 | 2025-01-24 | 北京微核芯科技有限公司 | Register renaming method, device, system, equipment and medium |
| CN119336393B (en) * | 2024-12-16 | 2025-03-28 | 北京微核芯科技有限公司 | Processor for superscalar processing and method of operation thereof |
| CN121029241A (en) * | 2025-10-31 | 2025-11-28 | 北京微核芯科技有限公司 | Register allocation and instruction issuance methods, apparatus, and electronic equipment |
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