CN102566459A - Digital NIM (Nuclear Instrument Module) data acquisition system - Google Patents

Abstract

The invention relates to a digital NIM data acquisition system, which includes a controller plug-in, an analog-to-digital signal converter (ADC) plug-in and a self-defined bus. A custom bus connects the controller card to the analog-to-digital converter (ADC) card; housed in the NIM chassis. The present invention has been tested by physical experiments, the maximum data transmission rate can reach 66MB/s, the system resolution: 0.0735%; the maximum event rate can be obtained with 1/2us: 400KSPS; the minimum dead time of the acquisition card: 2.0us.

Description

Digital NIM data acquisition system

technical field

The invention belongs to a data acquisition system and is directly applied to nuclear physics experiments or high-energy physics experiments.

Background technique

Lanzhou Heavy Ion Accelerator Cooling Storage Ring (HIRFL-CSR, referred to as CSR) is an expansion project of Lanzhou Heavy Ion Accelerator HIRFL, which is a major national scientific engineering project. CSR is a multi-functional experimental device integrating acceleration, accumulation, cooling, storage, cancer treatment terminal, internal target experiment, external target experiment and high-resolution measurement. It is a double storage ring system consisting of CSRm (main ring) and CSRe (experimental ring) constitutes. The Institute of Modern Physics of the Chinese Academy of Sciences can conduct many high-precision and high-density nuclear physics experiments relying on this large scientific device.

The NIM (Nuclear Instrument Module, nuclear instrument plug-in) electronics system is the basic platform for front-end electronics in the field of nuclear technology. A large number of nuclear physics experiments require the support of the NIM electronics system. However, the traditional NIM electronics system has no digital standard, and data acquisition requires the support of CAMAC (Computer Automatic Measurement and Control1, computer automatic measurement and control) or VME (Versa Module Euro card) system. The data transmission rate of the CAMAC data acquisition system can only reach 3MB/s at the highest, while the maximum data transmission rate of the data acquisition system based on the VME system can reach 47.5MB/s. However, the cost of VME and CAMAC systems is too high to be popularized and applied in other fields of data acquisition.

Contents of the invention

In view of the above, the object of the present invention is to develop a digital NIM data acquisition system ((CCNS)). Using the excellent characteristics of the NIM power supply, combined with modern computer and digital technology, the digital function of the NIM system is realized, thereby providing a new data acquisition platform for nuclear physics experiments and high-energy physics experiments, and improving the efficiency of data acquisition.

The present invention is achieved through the following technical solutions:

A digital NIM data acquisition system ((CCNS)), including a controller plug-in (1), an analog-to-digital signal converter (ADC) plug-in (2), and a custom bus (3); wherein: the controller plug-in is divided into controllers Front panel, rear panel of the controller, and inside the controller; the analog-to-digital converter (ADC) plug-in is divided into an analog-to-digital converter (ADC) front panel, an analog-to-digital converter (ADC) rear panel, and an analog-to-digital converter (ADC) inside; the custom bus connects the controller plug-in and the analog-to-digital signal converter (ADC) plug-in; it is loaded into the NIM chassis (4);

The front panel of the controller plug-in is equipped with program control indicator light, parallel hard disk indicator light, serial hard disk indicator light, power indicator light, trigger signal interface, RS232 serial port interface, keyboard and mouse interface, three USB2.0 interfaces, and 100M network interface , reset button, display interface;

There are two plugs on the back panel (Back Panel) of the controller plug-in, which are custom interactive bus plugs and NIM power plugs;

The internal circuit board of the controller plug-in is connected with: SM800 series embedded computer, ACEX1K50 series FPGA chip, SN75976 series single-end to differential chip, parallel hard disk, CF card, low dropout linear power supply chip and driver chip; the controller plug-in The interface on the front panel of the controller is welded on one side of the controller circuit board, and the socket on the rear panel of the controller plug-in is welded on the other side of the controller circuit board;

The front panel (Front Panel) of the analog-to-digital converter (ADC) plug-in has 8 analog input signal interfaces, 1 trigger signal interface and 1 reset button;

There are two plugs on the back panel (Back Panel) of the analog-to-digital converter (ADC) plug-in, which are custom interactive bus plugs and NIM power plugs;

The internal circuit board of the analog-to-digital signal converter (ADC) plug-in is connected with a peak stretcher plug-in, 16 amplifier chips, 8 ADC chips, 2 digital-to-analog converter chips, 1 CYCLONEIII series FPGA chip, and FPGA chip Program configuration chip, SN75976 series single-ended to differential chip, 3V-5V level conversion chip, signal matching board interface, low dropout linear power supply chip and driver chip. The interface on the front panel of the analog-to-digital converter (ADC) module is soldered to one side of the analog-to-digital converter circuit board, and the socket on the rear panel of the analog-to-digital converter (ADC) module is soldered to the analog-to-digital converter circuit board. the other side of the circuit board;

Custom bus connection controller plug-ins and analog-to-digital signal converter plug-ins.

Advantage of the present invention and the beneficial effect that produce:

The present invention has been tested by physical experiments, and the maximum data transmission rate can reach 66MB/s, and the data transmission rate is 33MB/s when the system is in normal operation, which is 10 times the data rate of the traditional CAMAC system. The invention has high cost performance and flexible system construction. The advantages are as follows:

1. The invention realizes a new and complete data acquisition system;

2. Realized an intelligent controller and multi-channel ADC module;

3. Realized the custom 64-core backplane bus specification and protocol based on FPGA technology, and obtained a data transmission rate of 33MB/s;

4. ADC plug-in indicators laboratory test indicators are as follows:

System Resolution: 0.0735%;

Maximum transmission speed: 33MB/s;

Maximum event rate: 400KSPS;

Acquisition card minimum dead time: 2.0us

Minimum DNL: 3LSB

Description of drawings

Fig. 1 is the schematic diagram that this data acquisition system is inserted into the NIM chassis;

Figure 2 is a connection diagram of the controller plug-in, ADC plug-in and custom bus of the system;

Figure 3 is the Co60 radioactive source gamma spectrum obtained experimentally with the support of the system;

Figure 4 is the waveform when the oscilloscope tests the transmission speed of the custom bus;

Fig. 5 is the waveform of oscilloscope test peak stretcher;

Detailed ways

The NIM chassis power supply used in the invention has six power supply levels of +-6V, +-12V, and +-24V.

The present invention adds an embedded computer controller and a 64-core backplane bus to the original NIM system that only has mechanical structure standards and electrical specifications, and through the backplane bus protocol, more NIM plug-ins can work together to realize small and medium-scale data Acquired functions to complete more complex physics experiments.

In the present invention, controller plug-in 1 and analog-to-digital signal converter (ADC) plug-in 2 have been designed, and the detailed introduction of these two kinds of plug-ins is as follows:

controller

Controller plug-in 1 is a standard single-width NIM plug-in, which is divided into the front panel of the controller, the rear panel of the controller and the inside of the controller; this plug-in implements a complete computer system, and can pass through a custom backplane bus Connect the ADC module to realize simple data acquisition function.

The front panel of the controller (Front Panel) has the following interfaces from top to bottom: three program control indicators, parallel hard disk indicator, serial hard disk indicator, power indicator, trigger signal interface, RS232 serial interface, keyboard and mouse interface , Three USB2.0 ports, 100M network port, reset button, display port. The program control indicator is connected to the programmable chip FPGA inside the controller, which can realize user-defined functions; the hard disk indicator shows whether the current hard disk is reading and writing; the power indicator indicates whether the power supply is normal and whether the controller has been connected. Power on; the trigger signal interface is compatible with TTL standard and NIM standard signals, using LEMO high-frequency socket, while the RS232 serial port uses 9-pin D-type female socket; Wiring, expand a PS2 port to a PS2 keyboard port and a PS2 mouse port; the three USB2.0 ports are standard ports, which can be connected to external mobile hard disk, USB flash drive or USB keyboard and mouse; the 100M network port is a standard port ; The reset button can reset the firmware program of the programmable chip inside the controller, and at the same time can reset the embedded computer inside; the display interface is a VGA15-pin socket, which can be connected to a common display.

There are two plugs on the back panel of the controller plug-in, which are the custom interactive bus plug and the NIM power plug. Among them, the custom interactive bus plug is a double-row 64-pin plug (32 pins per row), and the distance between the pins is 2.0mm; the power plug is a standard NIM plug-in power plug, and only +6V and +6V are used in this design. +12V two kinds of power supply.

The main internal components of the controller are: SM800 series embedded computer, ACEX1K50 series FPGA chip, SN75976 series single-end to differential chip, parallel hard disk, CF card, low dropout linear power supply chip and some driver chips. Among them, the SM800 series embedded computer realizes the basic computer functions, and is the supporting device of the man-machine interface of the controller. It is responsible for running the WINDOWS XP or LINUX operating system, providing FPGA-simulated PCI card driver and application program, and data acquisition system. Software support and data storage, etc.; the main function of ACEX1K50 series FPGA chips in this controller is the bridging function between the embedded computer PCI bus and the custom backplane bus and some data processing functions. These functions are all implemented in VHDL language. Internally implemented, these VHDL programs mainly include PCI slave device interface, custom bus interface, dual-port RAM, trigger signal processing, precise timing control, state machine and some test programs. The core part of the controller is composed of embedded computer, FPGA chip and the software and hardware programs inside these two components. Other devices such as conversion chips, hard disks, power supply parts, etc. are the supporting components of the core part.

Analog to Digital Signal Converter (ADC)

Analog-to-digital converter (ADC) plug-in 2 is also a standard single-width NIM plug-in, divided into analog-to-digital signal converter (ADC) front panel, analog-to-digital signal converter (ADC) rear panel and analog-to-digital signal converter (ADC) Internally; the plug-in realizes the conversion from analog signal to digital signal, and can pass the converted digital signal to the controller mentioned above through the custom backplane bus, so as to realize simple data acquisition function. At the same time, the ADC module can also receive commands from the controller through the custom backplane bus to realize corresponding actions.

The front panel (Front Panel) of the ADC module has the following interfaces: 8 analog input signal interfaces, 1 trigger signal interface and 1 reset button. Among them, the 8 analog input signal interfaces (1st to 8th from top to bottom) are all LEMO high-frequency sockets, which receive the energy signal output from the main amplifier of the front-end electronics of the detector; 1 trigger signal can be used as The trigger signal input during the self-debugging process of the module can also receive the synchronization signal from the output of the trigger signal fan-out device in the data acquisition experiment; the reset button realizes the synchronous reset function of the associated chip inside the module.

The shape of the back panel (Back Panel) of the ADC module is exactly the same as that of the controller, and there are custom interactive bus plugs and NIM power plugs from top to bottom. Among them, the custom interactive bus plug is a double-row 64-pin plug (32 pins per row), and the distance between the pins is 2.0mm; the power plug is a standard NIM plug-in power plug, which is different from the controller. Only two power supplies of +6V and -6V are used.

The main internal components of the ADC module are: 8 peak stretcher plug-ins, 16 amplifier chips, 8 ADC chips, 2 digital-to-analog converter chips, 1 CYCLONEIII series FPGA chip, FPGA chip program configuration chip, SN75976 series single-ended to differential chip, 3V-5V level conversion chip, signal matching board interface, low dropout linear power supply chip and some driver chips. It can realize pulse width stretching in the amplitude range of 50mV-5V, the rising edge is 10ns, and the stretching time can be controlled in 500ns-20us, and the minimum time resolution is 2.5ns.

The 16 amplifier chips provide differential input signals for the 8 ADC chips behind them, and the 8 ADC chips realize the digital conversion of the analog signal after peak broadening, and then transmit the data to the FPGA chip through the common parallel bus; the 2 DAC chips follow the The control of the program provides the upper and lower thresholds for the front-end peak stretcher; the FPGA chip is the control core of the module, providing the timing control signals of all the chips in the module, coordinating the cooperation between various components, and completing the conversion from analog signals to data signals. For conversion and transmission, the FPGA chip is also responsible for data storage and processing, and the acquired data is packaged and uploaded to the controller through the custom backplane bus. These functions of the FPGA chip are implemented internally by VHDL language. These VHDL programs mainly include custom bus interface, dual-port RAM, ADC and DAC working sequence control, interrupt signal generation, state machine and some test programs, etc. The SN75976 series single-ended to differential chip, 3V-5V level conversion chip, and signal matching board interface are all designed to realize the correct transmission of signals. The low-dropout linear power supply chip provides extremely low ripple power for the entire module, ensuring the normal operation of all components on the module.

custom bus

In order to realize the information interaction between the two designed plug-ins, the present invention designs a complete set of self-defined bus specifications, and the controller plug-in 1 and the analog-to-digital signal converter plug-in 2 must support basic write operations, read operations, and interrupt processing. Bus function, but also to achieve a certain data transmission speed, to meet the basic needs of physical experiments.

The custom bus 3 connects the controller plug-in 1 and the analog-to-digital signal converter plug-in 2;

Data Acquisition Experimental Procedures

1. Insert the controller plug-in into the NIM chassis, and ensure that the power socket of the plug-in is firmly connected with the power socket of the chassis;

2. The keyboard and mouse interface on the front panel of the controller is externally connected to an adapter cable, which is converted into two PS2 ports, which are respectively connected to the PS2 keyboard and PS2 mouse;

3. Use the LEM0 line to connect the trigger signal provided by the front-end electronics part of the detector to the trigger signal interface on the front panel of the controller;

4. The display interface on the front panel of the controller is connected to the VGA display;

5. Connect the 100M network cable to the network interface on the front panel of the controller;

6. The custom bus interface on the rear panel of the controller is connected to the self-made 64-core flat cable; so far, the connection of the controller is completed.

7. Insert the ADC module into the NIM chassis, and ensure that the power socket of the plug-in is firmly connected with the power socket of the chassis;

8. Use the LEMO line to connect the energy signal provided by the front-end electronics part of the detector to the 8-way analog signal input interface on the front panel of the ADC module;

9. The custom bus interface on the rear panel of the ADC module is connected to a self-made 64-core flat cable connected to the controller;

At this point, the connection of the ADC module is completed.

After completing the above 9 steps, turn on the power switch of the NIM chassis, and the controller and ADC module will start to work.

10. After the controller is powered on, there is a process of starting the operating system, which takes about 1-2 minutes;

11. After the operating system is started, the operating system will automatically search for the PCI driver of the FPGA and monitor and control the device according to the previous settings;

12. Open the data acquisition program interface, run the program, and the entire data acquisition process begins.

The signal from the detector is processed by the front-end electronic components to form a trigger signal and an energy signal. The trigger signal is processed and fanned out by the controller plug-in in the system, and provided to the ADC module plug-in in the system. Under the control of the control program of the controller and the trigger signal, the ADC module performs analog-to-digital conversion on the input signal, and temporarily stores the converted value in the internal FPGA memory of the ADC module, and waits for the temporarily stored data to reach 1KB-3KB The ADC module sends an interrupt request through the backplane bus. After the controller receives the mid-end request from the ADC module, it sends a handshake signal through the backplane bus to interact with the ADC module. The data is sent to the controller module. The controller temporarily stores the received data in the internal memory space of the FPGA, and then uploads them to the memory of the embedded computer of the controller through the PCI bus. The data in the embedded computer memory is under the control of the data acquisition program to draw a spectrogram, or transmit it to the host computer through the network for spectrogram display and data online analysis. At the same time, all the data are saved for later off-line analysis of the experimental data.

Figure 3 shows a Co60 radioactive source gamma spectrum test experiment done with the support of this system. It can be seen from the figure that the system can accurately measure the two peaks in the Co60 gamma spectrum, and by analyzing the narrowest peak, dividing its full width at half maximum by the maximum value of the peak can get 0.0735% Resolution; It illustrates the function realization of the digital NIM data acquisition system, and can realize basic physical experiments.

Figure 4 is the waveform when the oscilloscope tests the transmission speed of the custom bus. The first signal is the clock of the custom bus, the clock period is 60ns, and the frequency is 16.5MHz. The second way is the waveform on the lowest data bit AD00 on the custom bus. From the figure, we can find the waveform of AD00 changing from high level to low level or from low level to high level within two clock cycles, which proves that the minimum interval of data bit change is one clock cycle, that is, the data line The data on it also works at the frequency of the clock signal. Because the data line is 16 bits, therefore, the data transmission speed is 16.5×16÷8=33MB/s.

Figure 5 is the waveform of the oscilloscope testing the peak stretcher. It can be analyzed from this waveform that the width of the following waveform is 200ns×10=2us, and it can be concluded that the minimum dead time of the acquisition card is 2.0us. The maximum event rate can be obtained with 1/2us: 400KSPS.

Claims (1)

1. A digital NIM data acquisition system, comprising a controller plug-in (1), an analog-to-digital signal converter plug-in (2), and a custom bus (3); wherein: the front panel of the controller plug-in (1) sub-controller, The rear panel of the controller and the inside of the controller; the analog-to-digital signal converter plug-in (2) is divided into the front panel of the analog-to-digital signal converter, the rear panel of the analog-to-digital signal converter and the interior of the analog-to-digital signal converter: the custom bus (3) will The controller plug-in (1) is connected with the analog-to-digital signal converter plug-in (2); it is loaded into the NIM chassis (4); The front panel of the controller plug-in is equipped with program control indicator light, parallel hard disk indicator light, serial hard disk indicator light, power indicator light, trigger signal interface, RS232 serial port interface, keyboard and mouse interface, three USB2.0 interfaces, and 100M network interface , reset button, display interface; There are two plugs on the rear panel of the controller plug-in, which are the custom interactive bus plug and the NIM power plug; The internal circuit board of the controller plug-in is connected with: embedded computer, FPGA chip, SN75976 series single-end to differential chip, parallel hard disk, CF card, low dropout linear power supply chip and driver chip; the front panel of the controller plug-in The interface is welded on one side of the controller circuit board, and the socket on the rear panel of the controller plug-in is welded on the other side of the controller circuit board; The front panel of the analog-to-digital signal converter plug-in has 8 analog input signal interfaces, 1 trigger signal interface and 1 reset button; There are two plugs on the rear panel of the analog-to-digital signal converter plug-in, which are custom interactive bus plugs and NIM power plugs; The internal circuit board of the analog-to-digital signal converter plug-in is connected with a peak stretcher plug-in, 16 amplifier chips, 8 ADC chips, 2 digital-to-analog converter chips, 1 FPGA chip, FPGA chip program configuration chip, SN75976 series The single-end to differential chip, 3V-5V level conversion chip, signal matching board interface, low-dropout linear power supply chip and driver chip; the interface on the front panel of the analog-to-digital signal converter plug-in is soldered to the analog-to-digital signal converter circuit board On one side of the analog-to-digital signal converter plug-in, the socket on the rear panel is soldered to the other side of the analog-to-digital signal converter circuit board; The custom bus (3) connects the controller plug-in (1) and the analog-to-digital signal converter plug-in (2).

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