CN102566339A - Global alignment mark and global alignment method - Google Patents
Global alignment mark and global alignment method Download PDFInfo
- Publication number
- CN102566339A CN102566339A CN2011103420627A CN201110342062A CN102566339A CN 102566339 A CN102566339 A CN 102566339A CN 2011103420627 A CN2011103420627 A CN 2011103420627A CN 201110342062 A CN201110342062 A CN 201110342062A CN 102566339 A CN102566339 A CN 102566339A
- Authority
- CN
- China
- Prior art keywords
- alignment mark
- global alignment
- side wall
- signal sources
- global
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 7
- 238000007789 sealing Methods 0.000 abstract 1
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 210000000349 chromosome Anatomy 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a global alignment mark and a global alignment method. According to the invention, the global alignment mark comprises a single alignment mark arranged between a sealed first side wall and a sealed second side wall, wherein the first side wall and the second side wall are used as alignment marks; and the first side wall, the single alignment mark and the second side wall are used as three signal sources required by the global alignment mark. According to the invention, the first side wall and the second side wall replaces two signal sources in the prior art to be used as two of the three signal sources which are commonly required by the global alignment mark, so that the transverse size occupied by the global alignment mark can be reduced and the size of a scribe line can be reduced. Moreover, according to the invention, original first signal source and third signal source are replaced with sealing rings to ensure to only apply three signal sources, so that the error identification is avoided.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of global alignment mark and global alignment method.
Background technology
Global alignment mark (Global alignment mark) is mainly used in the coarse alignment of Nikon exposure bench, helps the position of the required mark of location fine alignment.Fig. 1 schematically shows the global alignment mark according to prior art.
The global alignment mark needs three signal sources usually, and these signals are all produced by three chromosome shapes (alignment mark) of design.Therefore, as shown in Figure 1, in the prior art, in O-ring seal, arranged three linear alignment marks 1,2,3.O-ring seal mainly is positioned at the circuit layout outer ring, is a kind of groove that digs down, and is used to stop that steam gets into electric circuit, thus the protection device.Label A among Fig. 1 and B show two sidewalls of O-ring seal, for example are called the first side wall A and the second sidewall B.
And Fig. 2 schematically shows the partial enlarged drawing according to the global alignment mark of prior art.As shown in Figure 2, arranged three linear alignment marks that are parallel to each other 1,2,3 between the first side wall A of O-ring seal and the second sidewall B.Wherein, the distance between alignment mark 1 and the first side wall A is a, and the distance between alignment mark 1 and the alignment mark 2 is b, and the distance between alignment mark 2 and the alignment mark 3 is b, and the distance between alignment mark 4 and the first side wall B is d.For example, a=5um, b=19um, c=13um, d=5um.
Therefore, shown in Figure 1 is at least a+b+c+d according to the shared lateral dimension of the global alignment mark of prior art, and more particularly, the lateral dimension shared according to the global alignment mark of prior art generally is not less than 50um.This lateral dimension is bigger, can take bigger Cutting Road area, thereby has reduced actual obtainable effective number of chips in the wafer.
Summary of the invention
Technical matters to be solved by this invention is to have above-mentioned defective in the prior art, and a kind of global alignment mark and global alignment method that can reduce the Cutting Road size is provided.
According to a first aspect of the invention; A kind of global alignment mark is provided; It comprises: be arranged in the first side wall of O-ring seal and the single alignment mark between second sidewall; Wherein said the first side wall and said second sidewall are as alignment mark, and said the first side wall, said single alignment mark and said second sidewall are used as three required signal sources of global alignment mark.
According to a second aspect of the invention; A kind of global alignment method is provided; It comprises: between the first side wall of O-ring seal and second sidewall, arrange single alignment mark; And said the first side wall and said second sidewall are used as alignment mark, and said the first side wall, said single alignment mark and said second sidewall are used as three required signal sources of global alignment mark.
According to the present invention; Utilize the first side wall and second sidewall to replace two signal sources (alignment mark) of prior art to be used as two in three required usually signal sources of global alignment mark; Thereby can reduce the shared lateral dimension of global alignment mark, can reduce the Cutting Road size.And, can reduce wrong signal according to global alignment mark of the present invention, this is because common O-ring seal or circuit periphery also can produce signal, thereby can cause normal 3 signal sources to become 5 signal sources.Original first signal source, the 3rd signal source are replaced then having guaranteed to have only 3 signal sources with O-ring seal, thereby avoid mistake identification.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the global alignment mark according to prior art.
Fig. 2 schematically shows the partial enlarged drawing according to the global alignment mark of prior art.
Fig. 3 schematically shows the global alignment mark according to the embodiment of the invention.
Fig. 4 schematically shows the partial enlarged drawing according to the global alignment mark of the embodiment of the invention.
Fig. 5 schematically shows the signal simulation figure according to the global alignment mark of the embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
Fig. 3 schematically shows the global alignment mark according to the embodiment of the invention.As shown in Figure 3, only between the first side wall A of O-ring seal and the second sidewall B, arrange single alignment mark 4 according to the global alignment mark of the embodiment of the invention.In the present embodiment; The first side wall A and the second sidewall B are also as alignment mark; The first side wall A and the second sidewall B are used as two in three required usually signal sources of global alignment mark, and promptly the first side wall A, single alignment mark 4 and the second sidewall B are used as three required signal sources of global alignment mark.
Fig. 4 schematically shows the partial enlarged drawing according to the global alignment mark of the embodiment of the invention.As shown in Figure 4, in the global alignment mark of the embodiment of the invention, originally the shared total lateral dimension " a+b+c+d " of global alignment mark only becomes and has only " b+c ".
Like this, for the concrete example of " a=5um, b=19um; c=13um; d=5um ", originally the shared total lateral dimension " a+b+c+d=42um " of global alignment mark only becomes and has only " b+c=32um ", has reduced the shared total lateral dimension of global alignment mark greatly.
Utilize the first side wall A and the second sidewall B replace illustrated in figures 1 and 2 about two signal sources (alignment mark 1,3) come as two in required usually three signal sources of global alignment mark; Thereby can reduce the shared lateral dimension of global alignment mark, can reduce the Cutting Road size.
And, can reduce wrong signal according to the global alignment mark of the embodiment of the invention, this is because common O-ring seal or circuit periphery also can produce signal, thereby can cause normal 3 signal sources to become 5 signal sources.Original first signal, the 3rd signal are replaced then having guaranteed to have only 3 signal sources with O-ring seal, thereby avoid mistake identification.Fig. 5 schematically shows the signal simulation figure according to the global alignment mark of the embodiment of the invention.As can beappreciated from fig. 5, three signals among the figure are very clear.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (2)
1. global alignment mark; It is characterized in that comprising: be arranged in the first side wall of O-ring seal and the single alignment mark between second sidewall; Wherein said the first side wall and said second sidewall are as alignment mark, and said the first side wall, said single alignment mark and said second sidewall are used as three required signal sources of global alignment mark.
2. global alignment method; It is characterized in that comprising: between the first side wall of O-ring seal and second sidewall, arrange single alignment mark; And said the first side wall and said second sidewall are used as alignment mark, and said the first side wall, said single alignment mark and said second sidewall are used as three required signal sources of global alignment mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103420627A CN102566339A (en) | 2011-11-02 | 2011-11-02 | Global alignment mark and global alignment method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103420627A CN102566339A (en) | 2011-11-02 | 2011-11-02 | Global alignment mark and global alignment method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102566339A true CN102566339A (en) | 2012-07-11 |
Family
ID=46412046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103420627A Pending CN102566339A (en) | 2011-11-02 | 2011-11-02 | Global alignment mark and global alignment method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102566339A (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035776A (en) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | Semiconductor device manufacturing method and reticle |
| JP2001267215A (en) * | 2000-03-16 | 2001-09-28 | Nikon Corp | Position information measuring device and exposure device |
| US20030003677A1 (en) * | 2001-06-27 | 2003-01-02 | Canon Kabushiki Kaisha | Alignment method, exposure apparatus and device fabrication method |
| CN1963679A (en) * | 2006-11-24 | 2007-05-16 | 上海微电子装备有限公司 | Alignment mark structure for aligning wafer |
| US20090096116A1 (en) * | 2007-10-16 | 2009-04-16 | Macronix International Co., Ltd. | Alignment mark and mehtod for forming the same |
| CN101446766A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Exposure and alignment mark on silicon chip |
| CN101515116A (en) * | 2008-02-21 | 2009-08-26 | Asml荷兰有限公司 | Mark structure for coarse wafer alignment and method for manufacturing such a mark structure |
| CN101750899A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Lithography layout and method for measuring lithography deformation thereof |
| US20110089581A1 (en) * | 2009-10-19 | 2011-04-21 | Victor Pol | Semiconductor wafer having scribe lane alignment marks for reducing crack propagation |
| CN102044538A (en) * | 2009-10-02 | 2011-05-04 | 富晶电子股份有限公司 | Semiconductor chip, seal ring structure and manufacturing method thereof |
-
2011
- 2011-11-02 CN CN2011103420627A patent/CN102566339A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001035776A (en) * | 1999-07-22 | 2001-02-09 | Seiko Epson Corp | Semiconductor device manufacturing method and reticle |
| JP2001267215A (en) * | 2000-03-16 | 2001-09-28 | Nikon Corp | Position information measuring device and exposure device |
| US20030003677A1 (en) * | 2001-06-27 | 2003-01-02 | Canon Kabushiki Kaisha | Alignment method, exposure apparatus and device fabrication method |
| CN1963679A (en) * | 2006-11-24 | 2007-05-16 | 上海微电子装备有限公司 | Alignment mark structure for aligning wafer |
| US20090096116A1 (en) * | 2007-10-16 | 2009-04-16 | Macronix International Co., Ltd. | Alignment mark and mehtod for forming the same |
| CN101446766A (en) * | 2007-11-27 | 2009-06-03 | 上海华虹Nec电子有限公司 | Exposure and alignment mark on silicon chip |
| CN101515116A (en) * | 2008-02-21 | 2009-08-26 | Asml荷兰有限公司 | Mark structure for coarse wafer alignment and method for manufacturing such a mark structure |
| CN101750899A (en) * | 2008-12-04 | 2010-06-23 | 上海华虹Nec电子有限公司 | Lithography layout and method for measuring lithography deformation thereof |
| CN102044538A (en) * | 2009-10-02 | 2011-05-04 | 富晶电子股份有限公司 | Semiconductor chip, seal ring structure and manufacturing method thereof |
| US20110089581A1 (en) * | 2009-10-19 | 2011-04-21 | Victor Pol | Semiconductor wafer having scribe lane alignment marks for reducing crack propagation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105895570B (en) | Improved seals for electrostatically cling sidewalls | |
| US20140327115A1 (en) | Multiple seal-ring structure for the design, fabrication, and packaging of integrated circuits | |
| US10770331B2 (en) | Semiconductor wafer device and manufacturing method thereof | |
| US9224694B2 (en) | Traceable integrated circuits and production method thereof | |
| CN103529658B (en) | Method for aligning square wafer in primary photolithography technique | |
| CN103178206A (en) | Etching method for triaxial magnetic sensor | |
| CN103367324A (en) | Cutting channel for semiconductor chip | |
| CN102566339A (en) | Global alignment mark and global alignment method | |
| CN104979223A (en) | Wafer bonding process | |
| CN105740540A (en) | Method for searching characteristic graphs of layouts in mask design | |
| JP2018014488A (en) | Photovoltaic cell and associated layout | |
| CN102436151B (en) | Forming method of photoetching layout | |
| CN203117634U (en) | Compatible mask reference design layout | |
| CN103050490B (en) | Automatic design method of scribing slot frame | |
| CN203894283U (en) | Probe card and probe device having the above probe card | |
| CN101692425B (en) | Novel design method for ESD protection | |
| CN201945799U (en) | Photomask | |
| ITUB20155696A1 (en) | SEMICONDUCTOR DEVICE, CORRESPONDING PRODUCTION PROCEDURES AND USE AND CORRESPONDING EQUIPMENT | |
| CN113075857B (en) | Photomask pattern processing method, processing device and photomask plate | |
| CN105467746A (en) | Layout processing method in early OPC | |
| CN105183969A (en) | Layout contact hole pitch amplification method | |
| CN102445865A (en) | Photo-etching graphic alignment marking method capable of reducing alignment bias of photo-etching machine | |
| CN104992927A (en) | Sawing method for making wafer contain dies of a variety of different sizes | |
| US20140339714A1 (en) | Semiconductor device | |
| CN102723322B (en) | Testing structure for monitoring communication between emitter and base due to contact hole in germanium-silicon process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
|
| C10 | Entry into substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120711 |