CN102520903B - Length-configurable vector maximum/minimum network supporting reconfigurable fixed floating points - Google Patents

Abstract

The invention discloses a reconfigurable length-configurable vector maximum/minimum network supporting fixed-floating points, including: a parallel floating-point data preprocessing unit for analyzing the format of the received 512-bit vector data A, And according to different data formats, process them separately, output the floating-point data obtained after processing to the reconfigurable comparator network, and output various flag bits obtained after processing to the result selection unit; the Mask register is used to control the maximum participation /minimum value data; a reconfigurable comparator network is used to take the floating-point data received from the parallel floating-point data preprocessing unit and the value received from the Mask register as input, compare the vector data in turn, and obtain the maximum The /value result is output to the result selection unit; and the result selection unit is used to receive the output of the reconfigurable comparator network, and obtain the final vector maximum/minimum value according to the output of various flag bits received from the parallel floating-point data preprocessing unit result.

Description

Support fixed-floating point reconfigurable length configurable vector max/min network

technical field

The invention relates to the technical field of high-performance digital signal processors, in particular to a reconfigurable length-configurable vector maximum/minimum network supporting fixed-floating points.

Background technique

With the rapid development of computer and information science, digital signal processor (DSP) technology came into being. In the past 40 years, DSP has been developed by leaps and bounds. In DSP, no matter how complicated the operation is, it is finally implemented by the operation unit. Therefore, the operation unit is the core component of the entire DSP. In recent years, with the continuous development of the field of digital signal processing, the application of DSP has promoted the development of DSP, and the DSP for specific fields and specific needs is the direction of its continuous development.

There are a large number of maximum/minimum value operations in the field of digital signal processing, such as median filtering, extraction of maximum/minimum pixels, Viterbi decoding, threshold detection, and precision detection. In traditional DSP processors, the maximum/minimum value operations are to reuse the existing fixed and floating-point arithmetic unit (ALU). Although this can save chip area, it has the following limitations:

1) Low efficiency. General DSP maximum/minimum value instructions can only compare the size of two data, when it is necessary to obtain the maximum/minimum value from a large amount of data, multiple instructions are required.

2) The supported data granularity is small, generally only one fixed-point format or floating-point format is supported. Taking the ADITS20XS series DSP as an example, although a 32-bit fixed-point data can be configured as 1/2/4 32/16/8-bit fixed-point data, and supports 8/16/32-bit fixed-point data format, it is in the 8/16-bit In the mode, the maximum/minimum value can only be taken from the corresponding two data in turn, instead of taking from 8/4 8/16 bits (2 32-bit fixed points can be configured as 8 8-bit, 4 16-bit) Maximum/minimum value.

3) The number of data cannot be configured. It can only take the maximum/minimum value from two data, and cannot flexibly configure the number of data, and cannot allow multiple data to participate in the maximum/minimum value operation.

In modern radar signal processing, spaceborne satellite image processing, image compression, high-definition video and other fields, there are a large number of variable-size, high-density calculations, which pose increasingly high challenges to the computing unit. The maximum/minimum Operation will become a major bottleneck of the operation unit. Some existing patents and literature have optimized the maximum/minimum value operations, but they are only limited to the level of scalar processor multiplexed ALU, and the fixed and floating-point maximum/minimum value operations are completely separated, and there is no further research Max/min networks specific to vector processors.

Therefore, analyze the similarity of fixed-point and floating-point data at the arithmetic level, use reconfigurable technology to achieve fixed-point data comparison at different granularities, add additional control circuits in the fixed-point data path to achieve data comparison in floating-point data format, and use special register configuration The number of data participating in the maximum/minimum value operation uses a set of proprietary configurable resources to perform vector maximum/minimum value operations. It is an urgent problem to be solved in the present invention to provide a vector maximum/minimum value network that supports different granularities, different data formats, and different data numbers to meet the needs of intensive vector maximum/minimum value calculations in specific fields.

It should be noted that the "/" in "maximum/minimum, 1/2/4, 32/16/8, and 8/16/32" in this article all means "or", which will not be repeated below.

Contents of the invention

(1) Technical problems to be solved

In view of this, the main purpose of the present invention is to provide a vector maximum/minimum value network with reconfigurable fixed-floating point length and configurable length, which supports 8/16/32 bits with/unsigned fixed-point data, 32-bit IEEE754 standard Simple simple-precision floating-point data operations, flexible configuration of the number of data participating in the maximum/minimum value of the vector through registers, and the execution of maximum/minimum value operations on vectors, speed up the execution speed of maximum/minimum operations on large amounts of data to meet the needs of dense vectors in specific fields /Minimum calculation requirements.

(2) Technical solution

In order to achieve the above object, the present invention provides a reconfigurable fixed-floating-point vector maximum/minimum value network, including: a parallel floating-point data preprocessing unit 100 for processing the received 512-bit vector data The format of A is analyzed, and different data formats are processed respectively, and the floating-point data obtained after processing is output to the reconfigurable comparator network 300, and various flag bits obtained after processing are output to the result selection unit 400; Mask register 200 is a 64-bit configurable Mask register used to control the data participating in the maximum/minimum value; the reconfigurable comparator network 300 is used to receive the floating point data from the parallel floating point data preprocessing unit 100 and The value received from the Mask register 200 is used as input, and the vector data is compared in turn according to the Opcode operation code, FBS option data format, U option, M option and the value of the Mask register, and the obtained maximum/minimum value results are output to the result selection Unit 400 ; and a result selection unit 400 , configured to receive the output of the reconfigurable comparator network 300 , and output the final vector maximum/minimum value result obtained according to various flag bits received from the parallel floating point data preprocessing unit 100 .

In the above scheme, the parallel floating-point data preprocessing unit 100 analyzes the format of the received 512-bit vector data A, and processes different data formats respectively, including: the parallel floating-point data preprocessing unit 100 processes the received The format of the 512-bit vector data A is analyzed. When the 512-bit vector data A is in the floating-point data format, the special value analysis is performed on these floating-point data, and the abnormal floating-point data flag NaNFlag, positive infinity flag PosInfFlag and Negative infinity flag NegInfFlag, and negate the negative floating-point data; when the 512-bit vector data A is in the fixed-point data format, the fixed-point data is directly output.

In the above scheme, the Mask register 200 controls the data participating in the maximum/minimum value, including: the Mask register 200 is a 64-bit configurable register, directly controls the 512-bit vector data A, and each bit of the Mask register 200 controls the 512 bits respectively. One byte of bit vector data A; when the M option is valid, only the unit indicated by the corresponding bit of the Mask register as 1 participates in the maximum/minimum value operation; when the M option does not exist, the maximum/minimum value operation is not affected by the Mask register , the 512-bit vector data A all participate in the maximum/minimum value operation.

In the above solution, the reconfigurable comparator network 300 is composed of 8/16/32-bit comparators cascaded, and each comparator obtains a corresponding maximum/minimum value according to an input operation code.

In the above scheme, the reconfigurable comparator network 300 is composed of multiple 32-bit comparators, one 16-bit comparator and one 8-bit comparator. In addition to the corresponding data input, the input of each comparator is also There are control signals U, M, FBS; when working in 32-bit single-precision floating-point or 32-bit fixed-point mode, 512-bit vector data passes through a 4-layer 32-bit comparator network to obtain a 32-bit maximum/minimum value; when working in 16-bit In half-word fixed-point mode, the output of the 32-bit comparator in the fourth layer enters a 16-bit comparator to obtain a 16-bit maximum/minimum value; when working in 8-bit byte mode, the output of the 16-bit comparator in the fifth layer The output enters an 8-bit comparator to obtain an 8-bit maximum/minimum value; the comparator resources required by the 8-bit fixed-point data format are added with corresponding control signals to achieve 16/32-bit fixed-point and 32-bit IEEE754 standards Reconfigurable simple-precision floating-point multiple data formats.

In the above scheme, in the result selection unit 400, the 4-1 selector MUX3614 is controlled by the FBS option. When FBS=2'b00, the network works in 32-bit fixed-point mode, and the MUX3614 directly outputs the reconfigurable comparator The 32-bit result of 300; when FBS=2'b10, the network works in 8-bit fixed-point mode, and MUX3 614 directly outputs the 8-bit result of reconfigurable comparator 300; when FBS=2'b11, the network works in 16-bit fixed-point mode In this mode, MUX3 614 directly outputs the 16-bit result of the reconfigurable comparator 300; when FBS=2'b01, the network works in the 32-bit simple-precision floating-point data format, and selects and outputs the final result according to various floating-point flag signals The maximum/minimum value of the vector; if NaNFlag=1, it means that there are NaN floating-point data in the 16 floating-point data, and the maximum/minimum value network will finally output 32'hFFFF_FFFF; if PosInfFlag=1 and Opcode=1, it means that there are positive floating-point data in the floating-point data Infinity data, and work in the maximum value Max mode, the maximum/minimum value network outputs positive infinity 32'h7F80_0000; if NegInfFlag=1 and Opcode=0, it means that there is negative infinity in the floating point data, and work in the minimum value Min mode, the maximum The /min network outputs negative infinity 32'hFF80_0000; in other cases, outputs the 32-bit floating point data of the reconfigurable comparator network 300.

(3) Beneficial effects

The reconfigurable length-configurable vector maximum/minimum network that supports fixed-floating points provided by the present invention adopts reconfigurable technology to realize fixed-point data comparison of different granularities, and adds an additional control logic unit in the fixed-point data path to realize Floating-point data comparison, using registers to flexibly configure the number of vector data participating in the maximum/minimum value operation, and performing vector maximum/minimum value operations, can support 8/16/32-bit signed/unsigned fixed-point data, 32-bit IEEE754 standard is simple Precision floating-point data operations, while the length of vector data is configured by the Mask register, which speeds up the execution speed of intensive vector maximum/minimum value operations for specific fields, simplifies software programming complexity, increases code density, and improves processor execution. /Minimum worth computing efficiency and flexibility.

Description of drawings

Fig. 1 is a schematic diagram of a vector maximum/minimum value network supporting fixed-floating-point reconfigurable and configurable data length according to an embodiment of the present invention.

FIG. 2 is an internal structure diagram of the parallel floating-point data preprocessing unit 100 according to an embodiment of the present invention.

FIG. 3 is an internal structure diagram of a reconfigurable comparator network 300 according to an embodiment of the present invention.

Fig. 4 is an internal structure diagram of an 8-bit comparator supporting different data formats according to an embodiment of the present invention.

Fig. 5 is an internal structure diagram of a reconfigurable 32-bit comparator supporting different data formats according to an embodiment of the present invention.

FIG. 6 is an internal structure diagram of the result selection unit 400 according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The main features of the invention are: the data format can be reconfigured and the data length can be configured. The following description symbols are agreed during the description process: the maximum/minimum value network instruction is described as B=Max/MinA{(M)}{(U)}{(FBS)}; B is 32-bit scalar data, and A is 512-bit vector data ;Opcode refers to the operation code, expressed in 1-bit binary, 0 represents the minimum value Min, 1 represents the maximum value Max; Mask is a 64-bit configurable register, each bit controls the 8-bit byte of the vector register A; M represents the maximum/minimum The value operation is affected by the Mask register. When the M option does not exist, it means that the Mask register has no effect on the maximum/minimum value operation; U indicates an unsigned option; FBS indicates the data format, expressed in 2-bit binary. "00" stands for 32-bit fixed point, "01" stands for 32-bit compact simple-precision floating point, "10" stands for 8-bit byte, and "11" stands for 16-bit halfword. OpaValid/OpbValid indicates that the operand Opa/Opb is valid, and is affected by the M option. When the M option is valid, OpaValid/OpbValid is 1, indicating that the operand Opa/Opb is valid; when the M option does not exist, OpaValid/OpbValid is invalid, and the operand Opa/Opb is always valid.

In the embodiment of the present invention, it is assumed that A is 512-bit vector data, but the present invention is applicable to any occasion where A is a multiple of 32 bits, and the relationship between the width of the Mask register and the length of the vector A is LengthMask=LengthA/8.

As shown in FIG. 1 , FIG. 1 is a schematic diagram of a fixed-floating-point reconfigurable and configurable vector maximum/minimum network according to an embodiment of the present invention, and the network includes parallel floating-point data preprocessing units 100 connected in sequence. , Mask register 200, reconfigurable comparator network 300 and result selection unit 400, wherein:

The parallel floating-point data preprocessing unit 100 is used to analyze the format of the received 512-bit vector data A, and when the 512-bit vector data A is in a floating-point data format (FBS=2'b01), these floating-point data Perform special value analysis to obtain special flag bits such as abnormal floating-point data flag (NaNFlag), positive infinity flag (PosInfFlag), negative infinity flag (NegInfFlag), and perform negation operation on negative floating-point data; when the When the 512-bit vector data A is in a fixed-point data format, the parallel floating-point data preprocessing unit 100 directly outputs the fixed-point data; the parallel floating-point data preprocessing unit 100 outputs the processed floating-point data to the reconfigurable comparator network 300, and Output various special flag bits to the result selection unit 400 .

The Mask register 200 is a configurable 64-bit register used to control the data involved in the maximum/minimum value. The 64-bit Mask register directly controls the 512-bit vector data A, and each bit of the Mask register 200 controls one byte of the vector data A respectively. When the M option is valid, only the unit indicated by the corresponding bit of the Mask register as 1 participates in the maximum/minimum value operation; when the M option does not exist, the maximum/minimum value operation is not affected by the Mask register, and all 512-bit vector data participate in the maximum/minimum value operation. Minimum operation.

The reconfigurable comparator network 300 is used to receive the data processed by the parallel floating-point data preprocessing unit 100 and the value of the Mask register as input, according to the Opcode operation code, FBS option data format, U option, M option and Mask register The vector data is compared in turn to obtain the maximum/minimum value, and the maximum/value result is output to the result selection unit 400 .

The result selection unit 400 is used to receive the output of the reconfigurable comparator network 300, and output the final vector maximum/minimum value result obtained according to the flag bits such as NaNFlag, PosInfFlag, NegInfFlag received from the parallel floating-point data preprocessing unit 100.

The maximum/minimum value network supporting fixed-floating point reconfigurability and configurable data length provided by the present invention will be described in detail below with reference to FIG. 2 to FIG. 6 . In terms of specific implementation, the present invention includes parallel, reconfigurable, and configurable designs, wherein the parallel floating-point data preprocessing unit 100 realizes parallelism through 16 identical hardware structures, and four 8-bit comparators can be reconfigured into 1/2 /4 32/16/8-bit comparators, the value of the Mask register realizes the flexible configuration of the vector length.

As shown in Figure 2, Figure 2 is an internal structure diagram of a parallel floating-point preprocessing unit according to an embodiment of the present invention, which includes a sequentially connected vector decomposition unit 110 and 16 identical floating-point flags A bit generation unit 120 , and a vector floating point result flag bit generation unit 140 .

The vector decomposition unit 110 is used to decompose the input 512-bit vector data A into 16 pieces of 32-bit scalar floating-point data A_0-A_15, and send them to 16 identical floating-point flag generating units 120 in sequence.

The floating-point flag generation unit 120 is used to analyze each 32-bit single-precision floating-point data, judge whether it is a special case such as NaN, infinity, and perform a negation operation on negative floating-point data. In the floating-point flag generating unit 120, the sign bit, the exponent, and the mantissa separation unit 121 separate the sign bit, the exponent, and the mantissa of the 32-bit floating-point data, and wherein the exponent is sent to the exponent comparator 122 for exponent comparison. output Exp_0=1, when the exponent is 255, output Exp_255=1, and when the exponent is other values, both Exp_0 and Exp_255 are 0. The mantissa comparator 123 receives the 23-bit mantissa (floating-point mantissa without implicit 1 extension) output by the sign bit, the exponent, and the mantissa separation unit 121. When the 23-bit mantissa is 0, Manti_0=1, and Manti_0=0 during other mantissas . Simultaneously, after the 31-bit exponent and the mantissa are extended into 32 bits by high-order 0, they enter the inversion circuit 124 and the MUX0 selector 128 through another channel, and the control signal of the MUX0 selector 128 comes from the sign bit of the floating point. When the sign bit is 1 MUX0 chooses to output the exponent and mantissa after inversion, otherwise it outputs the exponent and mantissa before inversion. MUX1 selector 129 receives the output of MUX0 selector 128 and 0 as its input, and its control signal is from the output Exp_0 of exponent comparator 123, when Exp_0=1, the floating-point data is regarded as 0, MUX1 selector 129 outputs 0, In other cases, the normal 32-bit non-zero data is output, and the MUX1 selector 129 obtains the preprocessed 32-bit floating point data DisFloat_0. Signal Exp_255 and Mant_0 enter NaN decision logic unit 130 and infinite decision logic unit 126, when Exp_255=1, Mant_0=0, NaN decision logic unit 130 outputs NaN_0=1, represents that floating-point data is NaN; When Exp_255=1, Mant_0 =1, the output of the infinity decision logic unit 126 is 1, indicating that the floating point data is infinite. The positive infinity decision logic unit 131 and the negative infinity decision logic unit 132 receive the output of the infinity decision logic unit 126 and the floating point sign bit as input, and further generate a positive infinity flag PosInf_0 and a negative infinity flag NegInf_0. So far, the special symbol flag bit of each floating point data is generated and the preprocessed floating point data is obtained.

The vector floating-point result flag generation unit 140 obtains the entire vector floating-point flag and the vector floating-point data according to the flags of each floating-point data and the processed data of each floating point. The vector NaN flag generating unit 141 is a 16-input OR gate, which receives each floating-point flag NaN_0-NaN_15, and outputs a vector NaN flag as NaNFlag. The vector positive infinity flag generation unit 142 and the vector negative infinity flag generation unit 143 are 16-input OR gates, which respectively receive PosInf_0-PosInf_15 and NegInf_0-NegInf-15 as inputs to obtain the vector positive infinity flag PosInfFlag and the vector negative infinity flag Bit NegInfFlag. The vector combination unit 144 combines the pre-processed floating point data DisFloat_0-DisFloat_15 to obtain 512-bit vector data.

So far, the preprocessing of the floating point vector is completed, and the flag bit of the floating point vector and the preprocessed floating point data are obtained. When working in the fixed-point mode, the floating-point data preprocessing unit directly obtains the fixed-point vector data without any preprocessing through another channel, and enters the next unit.

The Mask register 200 is a 64-bit user-configurable Mask register. Each bit of the 64-bit Mask register indicates the 8-bit byte of 512 vector data respectively. When the Mask register is valid (that is, the M option exists), only the vector data whose corresponding bit of the Mask register is 1 participates in the maximum/minimum value operation; otherwise All vector data participate in max/min operations.

As shown in FIG. 3 , FIG. 3 is an internal structure diagram of a reconfigurable comparator network 300 according to an embodiment of the present invention. The reconfigurable comparator network 300 is composed of cascaded 8/16/32-bit comparators, and each comparator obtains a corresponding maximum/minimum value according to an input operation code (maximum/minimum value). A 32-bit maximum/minimum value can be obtained through a 4-stage 32-bit comparator, a 16-bit maximum/minimum value can be obtained by adding a 16-bit comparator to the fifth stage, and an 8-bit maximum/minimum value can be obtained by adding an 8-bit comparator to the sixth stage . Through a set of comparator resources, the comparison of 8/16/32-bit signed/unsigned fixed-point and 32-bit simple-precision floating-point data can be realized, and the final maximum/minimum value can be obtained.

The comparator network 300 is composed of multiple 32-bit comparators, one 16-bit comparator and one 8-bit comparator. In addition to the corresponding data input, the input of each comparator also has control signals such as U, M, and FBS. . When working in 32-bit single-precision floating-point or 32-bit fixed-point mode, 512-bit vector data passes through a 4-layer 32-bit comparator network to obtain a 32-bit maximum/minimum value; when working in 16-bit half-word fixed-point mode, the fourth The output of the 32-bit comparator of the layer enters a 16-bit comparator to obtain a 16-bit maximum/minimum value; when working in 8-bit byte mode, the output of the 16-bit comparator of the fifth layer enters an 8-bit comparator, Get 8 bit max/min values. By adding corresponding control signals to the comparator resources required for the 8-bit fixed-point data format, the reconfigurability of multiple data formats such as 16/32-bit fixed-point and 32-bit IEEE754 standard simple-precision floating-point is realized.

The 16/32-bit comparator is composed of basic 8-bit comparators cascaded and combined, as shown in FIG. 4 , which is an internal structure diagram of an 8-bit comparator supporting different data formats according to an embodiment of the present invention. Adder 412 calculates the difference between the inputs Opa and Opb The first logic circuit 413 receives the output of the adder and has/unsigned data option U to generate Opa and Opb difference result flags: carry flag (CF), overflow flag (OF), negative number flag (NF). The second logic circuit 414 receives flags such as CF, OF, and NF, and control signals such as U, M, Opcode, OpaValid, and OpbValid, and generates a result selection signal Sel[1:0]; Sel[1:0] occupies 2 binary bits , "00" indicates that the output is invalid, "01" indicates that Opa should be selected as output, "10" indicates that Opb should be selected for output, and "11" indicates that the two data are equal, and Opa is still output here. Sel[0] enters MUX selector (417) as the output of control signal selection comparator; Simultaneously OpaValid, OpbValid and M option enter comparator result effective generation unit (416) to produce comparator result effective control signal ResultValid through another path ,in $\mathrm{Re\; sultValid}=\mathrm{OpaValid}\left|\mathrm{OpbValid}\right|\stackrel{\‾}{m}.$

The second logic circuit 144 generates the result selection signal Sel through some combinatorial logic, and the generation of Sel satisfies the following truth table:

Table 1 8-bit comparator Sel generates a truth table

Note: Opcode 0 means the minimum value, 1 means the maximum value; X means any value can be taken

As shown in Figure 5, Figure 5 is a reconfigurable internal structure diagram of a 32-bit comparator that supports different data formats according to an embodiment of the present invention. The 32-bit comparator is composed of four basic 8-bit comparators shown in Figure 4 and some control logic. Four basic 8-bit comparators (511, 512, 513, 514) work in parallel, and the ResultValid signals (ResultValid0-ResultValid3) of the four 8-bit comparators are spliced into 32-bit result valid signals ResultValid[3: 0], where ResultValid[3:0]={ResultValid3, ResultValid2, ResultValid1, ResultValid0}. The third logic circuit 515 receives the Sel signals (Sel0-Sel3) of 4 basic 8-bit comparators and the selection signal Sel[3:0] of the 32-bit comparator generated by the FBS option, and each bit of Sel[3:0] is respectively Indicates that each byte of the 32-bit comparator comes from Opa or Opb, Opa is selected for 1, and Opb is selected for 0. The generation of Sel[3:0] satisfies the following truth table:

Table 2 32-bit comparator Sel generates a logic table

As shown in FIG. 6 , FIG. 6 is an internal structure diagram of the result selection unit 400 according to an embodiment of the present invention. The result selection unit 400 obtains the final vector maximum/minimum value result according to the sign bits NaNFlag, PosInfFlag, NegInfFlag of the floating-point special case and the 8/16/32-bit maximum/minimum value result of the reconfigurable comparator network. Referring to Fig. 1, the result selection unit 400 selects according to the output 8/16/32 bit result of the reconfigurable comparator 300 and various floating-point flag signals (NaNFlag, PosInfFlag, NegInfFlag) output by the parallel floating-point data preprocessing unit 100 Output the final vector max/min. 4-1 Selector MUX3 614 is controlled by the FBS option, when FBS=2'b00, the network works in 32-bit fixed-point mode, MUX3 614 directly outputs the 32-bit result of reconfigurable comparator 300; when FBS=2' b10, the network works in 8-bit fixed-point mode, MUX3 614 directly outputs the 8-bit result of the reconfigurable comparator 300; when FBS=2'b11, the network works in 16-bit fixed-point mode, MUX3 614 directly outputs the reconfigurable comparator The 16-bit result of the device 300; when FBS=2'b01, the network works in the 32-bit IEEE754b standard refined simple-precision floating-point data format, and selects the final vector maximum output according to various floating-point flag signals (NaNFlag, PosInfFlag, NegInfFlag) /min. If NaNFlag=1, it means that there are NaN floating-point data in the 16 floating-point data, and the maximum/minimum value network will finally output 32'hFFFF_FFFF; if PosInfFlag=1 and Opcode=1, it means that there are positive infinite data in the floating-point data, and work in In the maximum value (Max) mode, the maximum/minimum value network outputs positive infinity 32'h7F80_0000; if NegInfFlag=1 and Opcode=0, it means that there is negative infinity 32'hFF80_0000 in the floating point data, and it works in the minimum value (Min) mode, The max/min network outputs negative infinity; otherwise, the 32-bit floating point data of the reconfigurable comparator 300 is output.

Based on the above-mentioned vector maximum/minimum network that supports fixed-floating point reconfigurable and vector length configurable shown in Figures 1 to 6, the present invention also provides a fixed-point reconfigurable and data length-configurable comparison method, It is characterized in that, comprising the following steps:

8/16/32-bit fixed-point data can be reconfigured, 8-bit fixed-point data is the basic unit; two 8-bit fixed-point data and corresponding control logic units are reorganized into 16-bit fixed-point data; four 8-bit fixed-point data and corresponding control logic Cell reorganization into 32-bit fixed-point data;

Fixed-floating point can be reconfigured, and the floating-point data determines whether to complete the negation operation according to the sign bit; when the sign bit is 1, the floating-point exponent and mantissa are negated respectively, and the sign bit remains 1. The floating-point sign bit, exponent, The mantissa forms the new 32-bit data; when the sign bit is 0, the floating point remains unchanged. After the floating point is processed by the sign bit, the fixed-point data path can be multiplexed;

The data length is configurable and implemented through the Mask register; each bit of the Mask register controls a certain bit field of the data, and the data length involved in the operation is configured by configuring the value of the Mask register.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (12)

1. support the configurable vector maximum/minimum value of the reconfigurable length of a fixed and floating network, it is characterized in that, comprising:

Parallel floating point data pretreatment unit (100), for the form of the 512 bit vector data A that receive is analyzed, and process respectively for different data layouts, the floating data obtaining after processing is exported to restructural comparator network (300), the various zone bits that obtain after processing are exported to result selected cell (400);

Mask register (200) is 64 configurable Mask registers, for the data of control and participate in maximum/minimum value comparison;

Restructural comparator network (300), the value that is used for being received from the floating data of parallel floating point data pretreatment unit (100) and be received from Mask register (200) is as input, according to the value of Opcode operational code, FBS option data form, U option, M option and Mask register, vector data is compared successively, the maximum obtaining/little value result is exported to result selected cell (400); And

Result selected cell (400), be used for receiving the output of restructural comparator network (300), according to the various zone bits that are received from parallel floating point data pretreatment unit (100), output obtains final vector maximum/minimum value result.

2. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 1 network, it is characterized in that, described parallel floating point data pretreatment unit (100) is analyzed the form of the 512 bit vector data A that receive, and process respectively for different data layouts, comprising:

Parallel floating point data pretreatment unit (100) is analyzed the form of the 512 bit vector data A that receive, in the time that these 512 bit vector data A is floating point data format, these floating datas are carried out to particular value analysis, obtain improper floating data zone bit NaNFlag, just infinite zone bit PosInfFlag and negative infinite zone bit NegInfFlag, and negative floating data is carried out to complementary operation; In the time that these 512 bit vector data A is fixed-point data form, directly export fixed-point data.

3. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 2 network, it is characterized in that, described parallel floating point data pretreatment unit (100) comprises the vectorial resolving cell (110), 16 identical floating-point zone bit generation units (120) and the vectorial floating point result zone bit generation unit (140) that connect successively, wherein:

Vector resolving cell (110), for these 512 bit vector data A of input is resolved into 16 32 scalar floating data A_0-A_15, and delivers to 16 identical floating-point zone bit generation units (120) successively;

Floating-point zone bit generation unit (120), for each 32 single-precision floating-point datas are analyzed, judges whether it is NaN or infinity, and negative floating data is carried out to complementary operation;

Vector floating point result zone bit generation unit (140), for obtaining whole vectorial floating-point zone bit and vector floating-point data according to the zone bit of each floating data and each floating-point data after treatment.

4. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 3 network, it is characterized in that, in described floating-point zone bit generation unit (120), 32 floating datas are carried out sign bit, index, mantissa's separation by sign bit, index, mantissa's separative element (121), its Exponential is delivered to index comparator (122) and is carried out index comparison, in the time that being 0, exports index Exp_0=1, in the time that being 255, exports index Exp_255=1, when index is worth for other, Exp_0 and Exp_255 are 0; 23 mantissa of mantissa's comparer (123) receiving symbol position, index, mantissa's separative element (121) output, in the time that 23 mantissa are 0, Manti_0=1, Manti_0=0 when other mantissa; 31 indexes, mantissa are extended to after 32 through high-order 0 simultaneously, enter negate circuit (124) and MUX0 selector switch (128) by other passage, the control signal of MUX0 selector switch (128) is from the sign bit of floating-point, in the time that sign bit is 1, MUX0 selects index, the mantissa after output negate, otherwise exports index, the mantissa before negate; MUX1 selector switch (129) receives the output and 0 of MUX0 selector switch (128) as its input, its control signal is from the output Exp_0 of index comparator (123), in the time of Exp_0=1, regard floating data as 0, MUX1 selector switch (129) output 0, in other situations, export normal 32 non-zero, MUX1 selector switch (129) obtains pretreated 32 floating data DisFloat_0; Signal Exp_255 and Mant_0 enter NaN decision logic unit (130) and infinite decision logic unit (126), work as Exp_255=1, when Mant_0=0, NaN decision logic unit (130) output NaN_0=1, expression floating data is NaN; Work as Exp_255=1, when Mant_0=1, infinite decision logic unit (126) is output as 1, represents that floating data is infinite; Just infinite decision logic unit (131) and negative infinite decision logic unit (132) receive the output of infinite decision logic unit (126) and floating-point-sign position as input, further generate just infinite zone bit PosInf_0, and negative infinite zone bit NegInf_0; So far, the special symbol zone bit of each floating data all generates and obtains pretreated floating data; .

5. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 3 network, it is characterized in that, in described vectorial floating point result zone bit generation unit (140), vector NaN zone bit generation unit (141) is 16 inputs or door, receive each floating-point zone bit NaN_0-NaN_15, output vector NaN is masked as NaNFlag; The negative infinite zone bit generation unit (143) of the just infinite zone bit generation unit of vector (142) and vector is 16 inputs or door, receive respectively PosInf_0-PosInf_15 and NegInf_0-NegInf-15 as input, obtain the negative infinite mark NegInfFlag of the just infinite zone bit PosInfFlag of vector and vector; The floating data DisFloat_0-DisFloat_15 that vector combining unit (144) obtains pre-service carries out combination, obtains 512 bit vector data.

6. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 1 network, is characterized in that, the data of described Mask register (200) control and participate in maximum/minimum value, comprising:

Mask register (200) is 64 configurable registers, directly controls these 512 bit vector data A, and each of Mask register (200) is controlled respectively a byte of these 512 bit vector data A; In the time that M option is effective, only having Mask register corresponding positions is that the unit of 1 instruction just participates in the operation of maximum/minimum value; In the time that M option does not exist, the operation of maximum/minimum value is not affected by Mask register, and these 512 bit vector data A all participates in the operation of maximum/minimum value.

7. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 1 network, it is characterized in that, described restructural comparator network (300) is made up of 8/16/32 bit comparator cascade, and each comparer obtains corresponding maximum/minimum value according to input operation code.

8. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 7 network, it is characterized in that, in described restructural comparator network (300), obtain 32 maximum/minimum value by 4 grade of 32 bit comparator, 16 bit comparators of the 5th grade of increase can obtain 16 maximum/minimum value, and the 6th grade increases by 8 bit comparators and can obtain 8 maximum/minimum value.

9. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 7 network, it is characterized in that, in described restructural comparator network (300), can realize 8/16/32 by a comparer resource simplifies the comparison of single-precision floating-point data, and obtains final maximum/minimum value with/without symbol fixed point, 32 IEEE7544 standards.

10. the configurable vector maximum/minimum value of the reconfigurable length of support fixed and floating according to claim 1 network, it is characterized in that, described restructural comparator network (300) is made up of multiple 32 bit comparators and 1 16 bit comparator and 18 bit comparator, except corresponding data input, the input of each comparer also has control signal U, M, FBS; In the time being operated in 32 single-precision floating points or 32 fixed point modes, 512 bit vector data, by 4 layer of 32 bit comparator network, obtain 32 maximum/minimum value; In the time being operated in 16 half-word fixed point modes, the output of the 4th layer of 32 bit comparator enters 1 16 bit comparator, obtains 16 maximum/minimum value; In the time being operated in octet pattern, the output of the 5th layer of 16 bit comparator enters 18 bit comparator, obtains 8 maximum/minimum value; Comparer resource required during by 8 fixed-point data forms is adding corresponding control signal, realizes 16/32 fixed point, and 32 IEEE754 standards are simplified the restructural of single-precision floating point several data form.

Configurable vector maximum/the minimum value of the 11. reconfigurable length of support fixed and floating according to claim 10 network, it is characterized in that, described 16/32 bit comparator is formed by 8 bit comparator cascadings, and totalizer (412) is calculated the difference of input Opa and Opb the first logical circuit (413) receives the output of totalizer and generates Opa and Opb difference result zone bit with/without symbol data option U: carry flag CF, overflow indicator OF, negative mark NF; The second logical circuit (414) receiving flag position CF, OF, NF, and control signal U, M, Opcode, OpaValid, OpbValid, bear results and select signal Sel[1:0]; Sel[1:0] take 2 scale-of-two, " 00 " represents that output is invalid, and " 01 " represents should select to export Opa, and " 10 " expression output should be selected Opb, and " 11 " represent that two data equate, still export Opa at this; Sel[0] enter MUX selector switch (417) and select the output of comparer as control signal; OpaValid, OpbValid and M option, by an other path, enter the effective generation unit of comparator results (416) and produce the effective control signal ResultValid of comparator results, wherein simultaneously

Configurable vector maximum/the minimum value of the 12. reconfigurable length of support fixed and floating according to claim 1 network, it is characterized in that, in described result selected cell (400), 4-1 selector switch MUX3 (614) is subject to the control of FBS option, in the time of FBS=2 ' b00, network is operated under 32 fixed point modes, and MUX3 (614) directly exports 32 results of restructural comparer (300); Work as FBS=2 ' b10, network is operated under 8 fixed point modes, and MUX3 (614) directly exports 8 results of restructural comparer (300); Work as FBS=2 ' b11, network is operated under 16 fixed point modes, and MUX3 (614) directly exports 16 results of restructural comparer (300); Work as FBS=2 ' b01, network is operated in 32 and simplifies single-precision floating-point data form, selects the final vector maximum/minimum value of output according to various floating-point zone bit signals; If NaNFlag=1, illustrates in 16 floating datas and has NaN floating data, the final output of maximum/minimum value network 32 ' hFFFF_FFFF; If PosInfFlag=1 and Opcode=1 represent the just infinite data of existence in floating data, and are operated in maximal value Max pattern, the just infinite 32 ' h7F80_0000 of maximum/minimum value network output; If it is negative infinite that NegInfFlag=1 and Opcode=0 represent to exist in floating data, and be operated under minimum M in pattern, the negative infinite 32 ' hFF80_0000 of maximum/minimum value network output; In other cases, 32 floating datas of output restructural comparator network (300).