CN102495816A - A fast interrupt hierarchical processing device and method - Google Patents

Abstract

The invention provides a rapid interrupt grading processing device and a method, comprising: the interrupt event storage device is used for storing interrupt events generated by the interrupt sources; the interrupt generating device is used for converting the interrupt event of the same interrupt source into an interrupt mark of 1 bit; interrupt flag storage means for storing all interrupt flags generated; the interrupt convergence device is used for carrying out hierarchical compression and storage on the interrupt mark and delivering the interrupt mark to the CPU for processing; the interruption convergence device is formed by N stages of cascade connection, each stage of interruption convergence device has the same structure,

n is the CPU read-write data bit width, and S is the total number of interrupt sources in the circuit system. By adopting the device and the method, after the CPU receives the interrupt request, only the interrupt mark needs to be searched reversely so as to search the corresponding interrupt event, so that the interrupt source can be positioned quickly, the processing time is shortened, and the CPU occupancy rate is saved.

Description

A fast interrupt hierarchical processing device and method

technical field

The invention relates to the technical field of data communication, in particular to an interrupt processing device and method.

Background technique

Interruption refers to the CPU's response to a certain event that occurs in the system. The processor will temporarily stop a task that is currently being executed and temporarily save the task. Go to execute the corresponding handler for this event. After processing, return to the previously saved task to continue processing.

Interrupt processing generally includes an interrupt request and an interrupt processing process. The CPU receives an interrupt request and responds to it. Events that may cause an interrupt request are called interrupt sources. After the CPU gets the interrupt request, it needs to find the corresponding interrupt source to perform corresponding processing, and the system needs to notify the CPU of the interrupt event as soon as possible to process the interrupt source.

Usually, as shown in Figure 1, the system generates several interrupt sources. After receiving an interrupt request, the CPU scans multiple interrupt sources to check which interrupt source the request comes from, and then processes it.

Now, with the development of technology level, the complexity of system design is getting higher and higher, and the number and reasons of interruption are also increasing. For example, in the OAM processing function of PTN equipment, the number of entries that OAM needs to support is 32768 Even reaching 65536 entries, each entry needs to generate various events independently and need to be reported to the CPU for processing.

Most of the interruptions in these OAM processes will involve the connectivity of data services. Therefore, these interruptions must be processed and cannot be lost. Moreover, the interruption of OAM connectivity will involve the operation of protection switching of services. The speed of CPU response has time requirements.

According to the method shown in Figure 1, after the CPU receives the interrupt request, it needs to find the unit that actually generates the interrupt among the 65536 interrupt sources, so that the overhead of the software increases, the CPU usage increases, and it takes too much time.

Contents of the invention

The technical problem to be solved by the present invention is to provide a fast interrupt hierarchical processing device and method, so that the CPU can quickly locate the interrupt source, speed up the processing time, and save the CPU usage rate.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a fast interrupt hierarchical processing device, characterized in that it includes:

The interrupt event storage device is used to store the interrupt event generated by the interrupt source;

An interrupt generating device is used to convert the interrupt event of the same interrupt source into a 1-bit interrupt flag;

interrupt flag storage means for storing all interrupt flags generated; and

The interrupt aggregation device is used to compress and store the interrupt flags hierarchically, and hand them over to the CPU for processing;

n为CPU读写数据位宽，S为电路系统中中断源的总数；The interrupt aggregation device is formed by cascading N levels, and the structure of each level of interrupt aggregation device is the same.

n is the CPU read and write data bit width, S is the total number of interrupt sources in the circuit system;

The interrupt source is a collection of all units in the circuit system that have the need to generate interrupt events, and is encoded according to certain characteristics; the interrupt event is generated by the interrupt source and consists of multiple bits, where a specific bit is set to 1 to represent a defined Interrupt events should be reported.

According to the above solution, it also includes an interrupt event mask bit device, including all interrupt events other than the terminal event that should be reported, for comparing with all interrupt events in the interrupt event storage device, and only passing the interrupt event that should be reported to the interrupt generating device.

According to the above scheme, the interrupt generating device includes: an interrupt generating scanner for uninterrupted scanning of the interrupt event storage device; and a shift register for controlling n bit interrupt flags generated once per scanning n interrupt sources .

According to the above solution, the bit width of the interrupt flag storage device is n, and the address depth is greater than or equal to S/n.

According to the above scheme, the interrupt aggregation device of each level includes: a convergence scanner for uninterrupted scanning of the interrupt signs generated by the upper level; an interrupt compression device; and an interrupt compression memory for storing the compressed interrupt flag of the current level and providing it to the CPU as a basis for hierarchically querying interrupt sources.

A fast interrupt classification processing method is characterized in that: it comprises the following steps:

1) Store interrupt events generated by all interrupt sources;

2) Convert the interrupt event of the same interrupt source into a 1-bit interrupt flag;

3) Store all interrupt flags generated;

4) The interrupt flags are compressed and stored in stages, and handed over to the CPU for processing; the process of compressing and storing at each stage is the same, and the number of stages n is the CPU read and write data bit width, S is the total number of interrupt sources in the circuit system;

The interrupt source is a collection of all units in the circuit system that have the need to generate interrupt events, and is encoded according to certain characteristics; the interrupt event is generated by the interrupt source and consists of multiple bits, where a specific bit is set to 1 to represent a defined Interrupt events should be reported.

It also stores all interrupt events other than the terminal events that should be reported, and is used for comparison with all the stored interrupt events, and masks the interrupt events other than the interrupt events that should be reported.

Said step 2) uninterruptedly scans the interrupt event storage device, and generates an n bit interrupt flag every scan of n interrupt sources.

The process of each stage of compression storage includes: uninterrupted scanning of the interrupt flags generated by the previous stage; n: 1 compression of the interrupt flags scanned by this stage; storage of the compressed interrupt flags of this stage, and providing to The CPU is used as the basis for hierarchically querying interrupt sources.

The beneficial effects of the present invention are:

1. By adopting the device and method, after the CPU receives the interrupt request, it only needs to reversely search for the interrupt flag and then search for the corresponding interrupt event, which can quickly locate the interrupt source, speed up the processing time, and save the CPU usage.

2. By adding an interrupt event masking bit device, only interrupt events that should be reported can be generated as interrupt flags, further saving CPU usage.

Description of drawings

Figure 1 shows the traditional interrupt processing method.

Fig. 2 is an overall structural diagram of an embodiment of the present invention.

Fig. 3 is a storage method of the interrupt event storage device.

Figure 4 is a structural diagram of the interrupt generator.

Figure 5 is a structural diagram of adding interrupt event mask bits.

FIG. 6 is a schematic diagram of interrupt flag storage.

FIG. 7 is a structural diagram of an interrupt aggregation device.

Figure 8 shows the CPU query interrupt event flow.

Detailed ways

The present invention will be further elaborated below according to the drawings and specific embodiments.

Fig. 2 is the overall structural diagram of the embodiment of the present invention, and it comprises: interrupt event storage device, is used for storing the interrupt event that interrupt source produces; Interrupt generating device, is used for the interrupt event conversion of same interrupt source to the interrupt sign of 1bit; The interrupt flag storage device is used for storing all generated interrupt flags; and the interrupt aggregation device is used for compressing and storing the interrupt flags hierarchically and handing them over to the CPU for processing.

The interrupt aggregation device is composed of N levels of cascading, and the structure of each level of interrupt aggregation device is the same. Considering the bit width of CPU read and write data, all interrupts will eventually converge into a matching CPU through a certain number of interrupt aggregation devices. Read and write the final compressed data with data bit width, and get the final interrupt information by bitwise ANDing the data, so n is the CPU read and write data bit width, and S is the total number of interrupt sources in the circuit system. Taking the CPU data bit width of 16 bits in this embodiment as an example, the total interrupt source is S, and the number of interrupt aggregation stages N can be obtained by the following formula:

In this embodiment, n is 16, the total interrupt sources are 64K, and the interrupt convergence device is cascaded in three levels.

The interrupt source is a collection of all units in the circuit system that have the need to generate interrupt events, and is encoded according to certain characteristics; the interrupt event is generated by the interrupt source and consists of multiple bits, where a specific bit is set to 1 to represent a defined Interrupt events should be reported.

FIG. 3 shows the storage method of the interrupt event storage device. The number of rows is the total number of interrupt sources, and each row stores all interrupt events generated by the same interrupt source.

Fig. 4 is a structural diagram of the interrupt generating device, including an interrupt generating scanner for uninterrupted scanning of the interrupt event storage device, and a shift register for controlling each scan of 16 interrupt sources to generate a 16-bit interrupt flag. As shown in Figure 5, an interrupt event mask bit device can also be added, including all interrupt events other than the terminal event that should be reported, for comparison with all interrupt events in the interrupt event storage device, and only the interrupt event that should be reported is passed to the interrupt generator The device is used to control whether various interrupt events need to be reported to the CPU for processing.

The interrupt flag storage device is used to store the interrupt flags of each interrupt source. The bit width of this RAM is 16bit, and the address depth is S/16. The storage sequence is as shown in Figure 6. Any 1bit of any address in the RAM is determined by RAM (addr, d[n]) indicates that an interrupt event has occurred in the interrupt source addr×16+n.

The function of the interrupt converging device is to extract all interrupt flags and compress and store them according to the compression ratio of 16:1. As shown in Figure 7, there are multiple converging devices in the whole system. The following will introduce the first-level interrupt converging device as an example. It includes an interrupt scanning device, an interrupt compressing device, and an interrupt compressing storage device.

The interrupt scanning device is driven by a counter to continuously scan the interrupt flag. Considering the operation of the CPU to obtain the interrupt, this system adopts the design of scanning an address in 2 clock cycles. The address space is S/16, where S is the total number of interrupt sources in the circuit system, and the scanning period of the first-level interrupt convergence module is (S/16)×2f _clk , where f _clk is the clock frequency. The scan cycle of the Nth-level interrupt aggregation module is (S/16 ^N )×2f _clk , calculated based on the design of the third-level interrupt aggregation module in this design, the total time of interrupt scanning at all levels is $\underset{N=0}{\overset{3}{\mathrm{\Σ}}}(S/{16}^N)\×{2f}_{\mathrm{clk}}.$

The interrupt compression device is composed of a shift register, which continuously receives the scanned interrupt flags. Since an address is 16 bits in the interrupt flag storage of the upper level, it is compressed into a 1-bit interrupt information through logical AND operation, and It is sent to the shift register, and every time 16 addresses are scanned, a 16-bit compressed data is formed.

The interrupt compression storage device stores the compressed interrupt flags and provides them to the CPU as a basis for hierarchically querying interrupt sources. The data bit width of each level of interrupt compression storage is 16bit, and the address depth is S/16 ^N+1 . For this storage device The value of any bit in RAM (addr, d[n]) is 1, representing the interval [(addr×16+n)×16 ^N , (addr×16+n+1)×16 ^N ] of the corresponding interrupt source There is an interrupt flag in the middle, where N is the number of stages of the current interrupt aggregation device. Taking this embodiment as an example, the address depths of the first stage, second stage, and third stage interrupt compression storage are 256, 16, and 1 respectively.

In the interrupt aggregation system cascaded in this way, when the CPU queries, it starts from the interrupt compression storage closest to the CPU side, and each level of interrupt compression storage can be used as the basis for the CPU to search for the upper level of interrupt compression storage. Finally, the final interrupt source can be obtained through N+1 level query. to get the interrupt event. In this embodiment, the CPU can locate the interrupt source through four queries.

Next, the operating mode of the CPU will be described, as shown in Figure 8, to help understand the advantages of this design for improving the processing speed of the CPU. Take the three-level interrupt aggregation as an example.

After the CPU obtains the interrupt request, it first checks the interrupt compressed storage 3, and the a-th bit is 1, and then the address of the interrupt compressed storage 2 is a;

Further, look at the address b in the interrupt compressed storage 2, and find that the xth bit in the address a is 1, then get the address b=a×16+x of the interrupt compressed storage 1 according to the formula;

Further, check the address b in the interrupt compression storage 1, and find that the yth bit in the address b is 1, and then the address c=b×16+y of the interrupt flag storage can be obtained;

Further, check the address c in the storage of the interrupt flag, and find that the zth bit in the address c is 1, and then the number of the interrupt source can be obtained as s=c×16+z.

Through the above analysis, it can be seen that no matter which one of the 65536 interrupt sources generates an interrupt event, the CPU can find the exact location of the actual interrupt source through 4 steps, thereby improving the processing efficiency of the CPU.

Claims (9)

1. A fast interrupt hierarchical processing device, characterized in that: it comprises: The interrupt event storage device is used to store the interrupt event generated by the interrupt source; An interrupt generating device is used to convert the interrupt event of the same interrupt source into a 1-bit interrupt flag; interrupt flag storage means for storing all interrupt flags generated; and The interrupt aggregation device is used to compress and store the interrupt flags hierarchically, and hand them over to the CPU for processing; The interrupt aggregation device is formed by cascading N levels, and the structure of each level of interrupt aggregation device is the same.

, n is the CPU read and write data bit width, S is the total number of interrupt sources in the circuit system; The interrupt source is a collection of all units in the circuit system that have the need to generate interrupt events, and is encoded according to certain characteristics; the interrupt event is generated by the interrupt source and consists of multiple bits, where a specific bit is set to 1 to represent a defined Interrupt events should be reported. 2. The fast interrupt hierarchical processing device according to claim 1, characterized in that: it also includes an interrupt event mask bit device, including all interrupt events that should be reported outside the terminal event, for use with all interrupt events in the interrupt event storage device Event comparison, only the interrupt event that should be reported is delivered to the interrupt generating device. 3. The fast interrupt hierarchical processing device according to claim 1 or 2, characterized in that: said interrupt generating device comprises: an interrupt generation scanner for uninterrupted scanning of the interrupt event storage device; and for controlling A shift register that generates an n-bit interrupt flag every scan of n interrupt sources. 4. The fast interrupt hierarchical processing device according to claim 3, characterized in that: the bit width of the interrupt flag storage device is n, and the address depth is greater than or equal to

. 5. The fast interrupt hierarchical processing device according to claim 3, characterized in that: said each level of interrupt convergence device comprises: a convergence scanner for uninterrupted scanning of the interrupt flags produced by the upper level; An interrupt compression device for compressing the interrupt flags scanned by the current stage by n:1; and an interrupt compression memory for storing the compressed interrupt flags of the current stage and providing them to the CPU as a basis for hierarchically querying interrupt sources. 6. A fast interrupt hierarchical processing method, characterized in that: it comprises the following steps: 1) Store interrupt events generated by all interrupt sources; 2) Convert the interrupt event of the same interrupt source into a 1-bit interrupt flag; 3) Store all interrupt flags generated; 4) The interrupt flags are compressed and stored in stages, and handed over to the CPU for processing; the process of compressing and storing each level is the same, and the number of stages

, n is the CPU read and write data bit width, S is the total number of interrupt sources in the circuit system; The interrupt source is a collection of all units in the circuit system that have the need to generate interrupt events, and is encoded according to certain characteristics; the interrupt event is generated by the interrupt source and consists of multiple bits, where a specific bit is set to 1 to represent a defined Interrupt events should be reported. 7. The fast interrupt hierarchical processing method according to claim 6, characterized in that: it also stores all interrupt events other than the terminal event that should be reported, and is used to compare all interrupt events stored, and compare the interrupt events other than the interrupt event that should be reported Event masking. 8. The fast interrupt hierarchical processing method according to claim 6 or 7, characterized in that: said step 2) performs uninterrupted scanning on the interrupt event storage device, and generates an n-bit interrupt flag every time n interrupt sources are scanned. 9. The fast interrupt hierarchical processing method according to claim 8, characterized in that: the process of compressing and storing each stage includes: uninterrupted scanning of the interrupt flags generated by the previous stage; flag and perform n:1 compression; store the compressed interrupt flag of the current level, and provide it to the CPU as a basis for hierarchically querying the interrupt source.

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