CN102479817B - Structure of vertical double-diffused metal oxide semiconductor field effect transistor - Google Patents

Abstract

The vertical double-diffused metal oxide semiconductor field effect transistor structure includes: a drain, a first conductivity type semiconductor substrate and an epitaxial layer; the first conductivity type semiconductor epitaxial layer includes a separated second conductivity type semiconductor first well region, The second well region of the second conductivity type semiconductor; the first source region of the first conductivity type semiconductor is arranged inside the first well region of the second conductivity type semiconductor, and the first source region of the first conductivity type semiconductor is arranged inside the second well region of the second conductivity type semiconductor Two source regions; the first source region of the first conductivity type semiconductor, the first well region of the second conductivity type semiconductor is partially covered with the first source region, the second source region of the first conductivity type semiconductor, the second source region of the second conductivity type semiconductor The well region is partially covered with a second source region; a gate oxide layer is provided between the first and second source regions; a gate is provided on the top of the gate oxide layer; a field oxide layer is intermittently provided between the gate oxide layer and the epitaxial layer . The structural device can increase the switching speed of the device and reduce the on-state resistance of the device.

Description

A Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor Structure

technical field

The invention belongs to the field of semiconductor power devices, in particular to a vertical double-diffused metal oxide semiconductor field effect transistor (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor, VDMOSFET) structure.

Background technique

Usually, when designing an electronic circuit, it is considered to have a high operating speed, and when the electronic circuit contains a MOSFET (Metal Oxide Semiconductor Field Effect Transistor, Metal Oxide Semiconductor Field Effect Transistor) device, the key to improving the operating speed is to make the MOSFET Able to respond quickly to input signals. When the MOSFET device is switched, it is necessary to charge and discharge the gate capacitance to make the gate electrode reach a specific voltage; the biggest obstacle to improving the switching speed of the MOSFET device is to overcome the delay caused by the parasitic gate capacitance during charging and discharging.

Figure 1 shows a cross-sectional view of a typical VDMOSFET device, marking the main parasitic capacitance of the VDMOSFET device. The main parasitic capacitances include: gate-source parasitic capacitance Cgs, gate-drain parasitic capacitance Cgd and drain- Source parasitic capacitance Cds.

When the N-channel MOSFET works normally, a positive voltage Vdd is applied to the drain terminal drain, and the n-type source region 30 and the P-type well region 34 are short-circuited through the source source and connected to a low potential. When applied to the gate gate and the source source When the potential Vgs between exceeds the threshold voltage Vt of the MOSFET device, the p-type well region 34 under the gate begins to form an inversion channel, the n-type source region 30 and the n-type drain region 40 are turned on through the inversion channel, and the source source A current starts to form between the drain and the drain; when the MOSFET is turned off, the p-type well region 34 begins to expand to the N-type drain region 40, and the dotted line 44 in the figure is the expansion of the depletion layer.

Figure 2 and Figure 3 show the potential changes between the electrodes when the device works dynamically when the gate-source parasitic capacitance Cgs and gate-drain parasitic capacitance Cgd of a typical MOSFET device is charged with a fixed current Ig. When the device is in the state of the first region Region1 in Figure 3, the current Ig starts to charge the gate-source parasitic capacitance Cgs, but the voltage Vgs between the gate and source is less than the threshold voltage Vt of the device, and the device is not turned on; when the device is in In the state of the second region region2, when the input current Ig charges the gate-source parasitic capacitance Cgs, the voltage Vgs between the gate and the source is greater than the threshold voltage Vt, the MOSFET device starts to turn on, and the voltage Vds between the source and the drain starts The input current Ig will start to charge the gate-source parasitic capacitance Cgs and the gate-drain parasitic capacitance Cgd respectively. As the charging progresses, the charging current Icgd distributed to the gate-drain parasitic capacitance Cgd will gradually increases, and the charging current Icgs allocated to the gate-source parasitic capacitance Cgs will gradually decrease, so the voltage Vgs between the gate and source gradually increases but the rate of growth gradually decreases; with the increase of the voltage Vgs between the gate and source , the voltage change rate between the source and drain increases until Vgs no longer increases, and the charging current Icgd of the capacitance between the gate and drain increases to equal the input current Ig, that is, the input current Ig is completely distributed to the charging current between the gate and drain Icgd; when the voltage Vgs between the gate and source no longer increases, charging continues, the device is in the state of the third region region3, and the voltage between the source and drain continues to decrease.

For the change of the gate-drain parasitic capacitance Cgd, when the device is not turned on, the potential difference between the source and drain is the largest so that the depletion layer expands greatly, as shown in Figure 1. 44, and when the device is turned on, the drain of the device The potential difference between the source and the source decreases, and the thickness of the depletion layer will gradually decrease, which is equivalent to reducing the distance between the gate and the drain, and the gate-drain parasitic capacitance Cgd increases; the increase of this capacitance makes the source The tendency of the potential between the electrode and the drain to decrease becomes slower. Only after the capacitance between the source and drain is stable, the MOSFET device is fully turned on, and the capacitance Cgd will not cause further turn-on delay.

Similarly, when the MOSFET device is turned off, the discharge of the capacitor will be delayed as well as the charge, thereby affecting the turn-off speed of the device. When MOSFET devices are used in linear applications, for example, the response speed of RF power amplifiers depends largely on the high-end limit frequency determined by the input capacitance of MOSFET devices.

The input capacitance Cin of the device can be expressed by the following formula: Cin=Cgs+Cgd (1-dVds/dVgs); in the formula, Cin is the input capacitance, Cgs is the gate-source parasitic capacitance, and Cgd is the gate-drain parasitic capacitance , Vgs gate-source voltage, Vgd is gate-drain voltage.

It is worth mentioning that the value of the input capacitance Cin of the device is at least three times larger than the gate-source parasitic capacitance Cgs, so reducing the value of the capacitance Cgd can effectively reduce the input capacitance of the device, thereby improving the switching speed of the device .

The formula for calculating capacitance is C=A*K*ε ₀ /t, in the formula: ε ₀ refers to the dielectric constant of vacuum, K refers to the relative dielectric constant, K _sio2 =3.9, K _si =11.7, A refers to capacitance The facing area of the two plates, the distance between the t capacitor plates, so the capacitance can be reduced by reducing the facing area of the two plates of the capacitor, or the relative dielectric constant, or increasing the distance between the capacitor plates, Since the material of the power device is fixed, a common solution to reduce the gate-source parasitic capacitance of the power device is to reduce the facing area between the capacitor plates or increase the thickness of the dielectric layer between the capacitor plates.

FIG. 4 is a schematic structural diagram of a strip-shaped cellular power device with a conventional structure. The gate-drain parasitic capacitance Cgd is not reduced, and the switching speed of the power device with this structure is low.

For the conventional power device structure as shown in FIG. 1 , this structure usually adopts n-type JFET implantation between the underside of the gate polysilicon material and the p-type well region, so as to reduce the on-resistance of the device. However, when the n-type JFET injection reaches a certain dose, it will affect the breakdown voltage of the device. The p-well under the region shown by CDE in Figure 5 belongs to the spherical junction, while the region shown by DEFG in the figure belongs to the cylindrical junction. According to the breakdown theory of semiconductor pn junctions, the breakdown voltage of spherical junctions is lower than that of cylindrical junctions. The implant dose of the JFET of the device will be limited by the spherical p-well of the CDE region.

An existing scheme is to reduce the capacitance by increasing the thickness of the dielectric layer between the capacitor plates, as shown in Figure 6, by increasing the thickness 60 of the dielectric layer between the gate 64 and the drain 62 to reduce the gate - The drain parasitic capacitance Cgd, the thickness of the dielectric layer between the gate 64 and the N-type source region 66 remains unchanged, ensuring that the threshold of the device is normal and the gate-source parasitic capacitance Cgs remains basically unchanged.

The power device structure in Figure 6 uses a thicker oxide layer under the gate to reduce the capacitance of the device. This structure can effectively reduce the capacitance of the device and increase the switching speed, but because the thicker oxide layer will block the injection of some JFETs , as shown in Figure 7, the entire N well is filled with a field oxygen structure, and the on-resistance of the device will increase. Although we can increase the JFET implant dose to adjust, there is another defect, as shown in Figure 8, When the gate length of the device minus the length of the channel regions on both sides is only 2~3um, it is necessary to set a thicker oxide layer under the gate and implant the JFET without increasing the number of mask layers. You can't have both. If the n-type JFET implantation step is advanced before field oxygen generation, the entire chip surface will be implanted with n-type impurities due to the lack of a mask, which will inevitably reduce the breakdown voltage of the terminal area, and adding a layer of photomask will inevitably increase the cost. .

Another existing solution is to reduce the capacitance by reducing the facing area between the two plates of the capacitor. As shown in FIG. The gate plate is equivalent to reducing the facing area between the two plates of the capacitor, and the gate-drain parasitic capacitance Cgd will also be reduced.

Figure 10 is a schematic diagram of the strip cell structure corresponding to the power device in Figure 9, and Figure 11 is a schematic diagram of the hexagonal cell structure of the power device in Figure 9, and the gate-drain parasitic capacitance of the power device is reduced by reducing the area of the gate polysilicon Cgd. Since the implantation of the p-type well region uses the gate material polysilicon as a mask, at the same time, self-alignment of the gate is formed to avoid differences in the turn-on characteristics of the device and the gate-source parasitic capacitance Cgs. However, the device structure removes the gate polysilicon in the middle part, and it is necessary to add a layer of photomask to prevent the p-well from being implanted under the gate and between the two p-wells, which inevitably increases the cost.

Contents of the invention

The present invention solves the technical problem that reducing VDMOSFET gate-drain parasitic capacitance will increase process steps in the prior art, and provides a VDMOSFET with low gate-drain capacitance. The VDMOSFET has low gate-drain capacitance and high switching speed. In addition, the manufacturing process steps are simple and the cost is low.

A vertical double-diffused metal-oxide-semiconductor field-effect transistor structure, comprising from bottom to top: a drain, a first conductivity type semiconductor substrate, and a first conductivity type semiconductor epitaxial layer; inside the first conductivity type semiconductor epitaxial layer Comprising a separated second conductive type semiconductor first well region and a second conductive type semiconductor second well region;

A first source region of a semiconductor of the first conductivity type is arranged inside the first well region of the semiconductor of the second conductivity type, and a second source region of the semiconductor of the first conductivity type is arranged inside the second well region of the semiconductor of the second conductivity type;

The first source region of the semiconductor of the first conductivity type and the first well region of the semiconductor of the second conductivity type are partially covered with the first source region, the second source region of the semiconductor of the first conductivity type and the second well region of the semiconductor of the second conductivity type partially covered with a second source region;

A gate oxide layer is provided between the first source region and the second source region;

A gate is arranged on the top of the gate oxide layer; a field oxide layer is intermittently arranged between the gate oxide layer and the epitaxial layer.

In the vertical double-diffused metal oxide semiconductor field effect transistor of the present invention, a field oxide layer is intermittently provided between the gate oxide layer and the epitaxial layer, and the area where the field oxide layer is provided between the gate oxide layer and the epitaxial layer can effectively reduce the The gate-drain parasitic capacitance of the vertical double-diffused metal oxide semiconductor field effect transistor is small, and the switching speed of the device is improved. In addition, the region without the field oxide layer between the gate oxide layer and the epitaxial layer is convenient for device JFET implantation, and can effectively reduce the on-state resistance of the device.

Description of drawings

FIG. 1 is a schematic structural diagram of a vertical double-diffused metal-oxide-semiconductor field effect transistor provided in the prior art.

FIG. 2 is a circuit diagram for charging the gate-source parasitic capacitance and the gate-drain parasitic capacitance of a MOSFET device with a current provided in the prior art.

FIG. 3 is a schematic diagram of voltage changes at both ends of the parasitic capacitor when the parasitic capacitor of the MOSFET device is charged in the prior art.

FIG. 4 is a schematic diagram of the strip-shaped cell structure of the vertical double-diffused MOSFET provided by the solution 1 of the prior art.

FIG. 5 is a schematic diagram of a hexagonal cell structure of a vertical double-diffused MOSFET provided by Solution 1 of the prior art.

FIG. 6 is a schematic structural diagram of a vertical double-diffused metal-oxide-semiconductor field-effect transistor provided by Solution 2 of the prior art.

FIG. 7 is a schematic diagram of the strip-shaped cell structure of the vertical double-diffused MOSFET provided by the solution 2 of the prior art.

FIG. 8 is a schematic diagram of a hexagonal cell structure of a vertical double-diffused MOSFET provided by Solution 2 of the prior art.

FIG. 9 is a schematic structural diagram of a vertical double-diffused metal-oxide-semiconductor field effect transistor provided by solution 3 of the prior art.

FIG. 10 is a schematic diagram of the strip-shaped cell structure of the vertical double-diffused MOSFET provided by the solution 3 of the prior art.

FIG. 11 is a schematic diagram of a hexagonal cell structure of a vertical double-diffused MOSFET provided by Solution 3 of the prior art.

FIG. 12 is a schematic diagram of the strip cell structure of the vertical double-diffused MOSFET provided by Embodiment 1 of the present invention.

FIG. 13 is a schematic diagram of the hexagonal cell structure of the vertical double-diffused MOSFET provided by Embodiment 1 of the present invention.

Fig. 14 is a schematic diagram of the strip-shaped cell structure of the vertical double-diffused MOSFET provided by Embodiment 2 of the present invention.

FIG. 15 is a schematic diagram of the hexagonal cell structure of the vertical double-diffused MOSFET provided by Embodiment 2 of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In order to reduce the gate-drain parasitic capacitance of the vertical double diffused metal oxide semiconductor field effect transistor without affecting the JFET injection of the device, the vertical double diffused metal oxide semiconductor field effect transistor structure of the present invention is provided.

A vertical double-diffused metal-oxide-semiconductor field-effect transistor structure, comprising from bottom to top: a drain, a first conductivity type semiconductor substrate, and a first conductivity type semiconductor epitaxial layer; inside the first conductivity type semiconductor epitaxial layer Comprising a separated second conductive type semiconductor first well region and a second conductive type semiconductor second well region;

A first source region of a semiconductor of the first conductivity type is arranged inside the first well region of the semiconductor of the second conductivity type, and a second source region of the semiconductor of the first conductivity type is arranged inside the second well region of the semiconductor of the second conductivity type;

The first source region of the semiconductor of the first conductivity type and the first well region of the semiconductor of the second conductivity type are partially covered with the first source region, the second source region of the semiconductor of the first conductivity type and the second well region of the semiconductor of the second conductivity type partially covered with a second source region;

A gate oxide layer is provided between the first source region and the second source region;

A gate is arranged on the top of the gate oxide layer; a field oxide layer is intermittently arranged between the gate oxide layer and the epitaxial layer.

As a preferred solution, the vertical double-diffused metal-oxide-semiconductor field-effect transistor of the present invention is an N-channel vertical double-diffused metal-oxide-semiconductor field-effect transistor, then the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor It is a P-type semiconductor.

The gate is a polysilicon layer, the source and the drain are metal electrodes, and both the field oxide layer and the gate oxide layer are insulating layers.

As Embodiment 1 of the present invention, as shown in FIG. 12 , it is a schematic diagram of a strip-shaped cell structure of an N-channel vertical double-diffused MOSFET. A thickened oxide layer, that is, a field oxide layer, is arranged in a rectangular region such as CDEF as shown in FIG. 12 to reduce gate-drain parasitic capacitance. Usually, the field oxide layer in the entire cell area of the device is completely etched away during the process of the device, but in the present invention, the field oxide layer in the cell area is partially etched according to the area preset by the device layout. Etching is performed to keep the field oxide layer in the CDEF area, and other parts are etched and removed. In this way, the field oxide layer can be thickened in a local area of the device without increasing the number of layout layers, and no thick field oxide layer is formed in other areas. JFET implantation can be performed in the field-free oxide layer region, which can effectively improve the on-resistance of the device. The structure of the present invention is to optimize the layout of the power device to achieve the purpose of reducing the redundant parasitic capacitance.

The cross-sectional structure of the device corresponding to the dotted line A-B in Figure 12 is: the thick field oxide layer is removed, and the cross-sectional structure of the JFET implantation is not blocked by the thick field oxide layer. The resistance of the JFET is reduced, and the crowding of the current channel of the device is relieved, so that the resistance of the JFET is reduced, and the on-state resistance of the device is reduced overall.

The cross-sectional structure of the device corresponding to the dotted line AA-BB in Fig. 12 is: a thick field oxide layer is partially reserved, and JFET injection is blocked by the thick field oxide layer. Reserving a thick field oxide layer locally will reduce the parasitic capacitance of the device; at the same time, no JEFT implantation is performed in the local area, so that the withstand voltage of the device will not be greatly affected by the JEFT implantation.

In summary, the entire vertical double-diffused MOSFET structure not only has a field oxide layer that reduces gate-drain parasitic capacitance, but also has only a thinner gate oxide layer area, which is convenient for JFET injection and reduces On-state resistance of small devices.

13 is a schematic diagram of the hexagonal cell structure of the N-channel vertical double-diffused MOSFET in Embodiment 1 of the present invention. A thickened oxide layer, that is, a field oxide layer, is used in a triangular region such as CDE as shown in Figure 13 to reduce the device gate-drain parasitic capacitance, while the quadrilateral DEFG region still only has a thinner gate oxide layer, Devices can be JFET implanted. This approach leaves the breakdown-prone CDE region free of JFET implants, while the DEFG region can accommodate higher dose implants to optimize on-resistance. It is worth mentioning that the DF and EG on both sides of the quadrilateral DEFG region are the channel regions through which the current passes, which contributes the most to reducing the resistance, while the CDE region has no effective channel. It can be considered that this region has a limited contribution to reducing the resistance. , but this region still generates gate-drain parasitic capacitance, which affects the switching speed of the device. The structure of the invention is to optimize the layout of the power device to reduce the redundant parasitic capacitance. The important point is to ensure that there is JFET injection under the gate of the effective channel, and at the P well where the spherical junction is formed at the corner of the cell, the capacitance is reduced by setting a thicker field oxygen.

The device structure corresponding to the dotted line A-B in Figure 13 is: the thick field oxide layer is removed, and the cross-sectional structure of the JFET implantation is not blocked, that is, the surface of this area is implanted with the same type of impurity as the epitaxy, which not only reduces the resistance of the surface epitaxy , and the crowding of the current channel of the device is alleviated, so the JFET resistance decreases, which reduces the on-state resistance of the device as a whole.

The device structure corresponding to the dotted line AA-BB in FIG. 13 is: a thick field oxide layer is partially reserved, and JFET injection is blocked by the thick field oxide layer. A thick field oxide layer is locally reserved, so as to achieve the purpose of reducing the gate-drain parasitic capacitance of the device. At the same time, JEFT implantation is not performed in a local area, so that the withstand voltage of the device is less affected by the JEFT implantation.

In summary, the device cross-sectional structure corresponding to the dotted line A-B does not have a thickened field oxide layer, and the device cross-sectional structure corresponding to the dotted line AA-BB has a thickened field oxide layer. The two structures are in the same vertical double-diffused metal oxide semiconductor Exist in field effect tubes. The power device with this structure not only reduces the gate-drain parasitic capacitance, but also facilitates JEFT injection of the device, thereby reducing the on-state resistance of the device.

The structure of the present invention is not limited to the shape of the field oxide layer set in the triangular CDE region, and various schemes such as hexagonal, square, and circular can be used, and the invention is not limited to the hexagonal element as shown in Figure 13 The layout of cells can also be applied to the design of square cells, strip cells, etc.

As Embodiment 2 of the present invention, the region corresponding to the gate oxide layer and the field oxide layer is provided with a groove communicating with the gate oxide layer. This structure can reduce the facing area between the two plates of the gate-drain parasitic capacitance, thereby achieving the purpose of reducing the gate-drain parasitic capacitance.

As shown in FIG. 14 , it is a schematic diagram of the structure of an N-channel vertical double-diffused MOSFET strip cell according to Embodiment 2 of the present invention. The difference from FIG. 12 is that the gate polysilicon corresponding to the field oxide layer is removed, so as to further reduce the gate-drain parasitic capacitance. Figure 14 Set a thickened oxide layer, that is, a field oxide layer, in a rectangular area such as CDEF to reduce the device gate-drain parasitic capacitance, and remove the gate polysilicon material above the field oxide layer set in a rectangular area such as CDEF , to further reduce the gate-drain parasitic capacitance of the device. Since the field oxide layer is thicker, it can block the injection of the p-well, and there will be no cost problem caused by the need to add a layer of photomask.

The device structure corresponding to the dotted line A-B in Figure 14 is: the thick field oxide layer is removed, and the cross-sectional structure of the JFET implantation is not blocked, that is, the surface of this region is implanted with the same type of impurity as the epitaxy, which not only reduces the resistance of the surface epitaxy , and the crowding of the current channel of the device is alleviated, so that the resistance of the JFET is reduced, and the on-state resistance of the device is generally reduced.

The device structure corresponding to the dotted line AA-BB in Fig. 14 is: a thick field oxide layer is locally retained, the JFET injection is blocked by the field oxide layer, and the cross-sectional structure of the gate polysilicon material corresponding to the field oxide layer is removed. A thick field oxide layer is partially retained and gate polysilicon material above the field oxide layer is removed, thereby further reducing the parasitic capacitance of the device. At the same time, JEFT implantation is not performed in a local area, so that the withstand voltage of the device is less affected by the JEFT implantation.

15 is a schematic diagram of the hexagonal cell structure of an N-channel vertical double-diffused MOSFET in Embodiment 2 of the present invention. The gate polysilicon above the field oxide layer in the CDE area is removed to further reduce the gate-drain parasitic capacitance of the device. Since the field oxide layer can block the injection of the p-well, the cost of adding a layer of photomask will not arise .

The device structure corresponding to the dotted line A-B in Figure 15 is: the thick field oxide layer is removed, and the JFET implantation is not blocked by the thick field oxide layer. The resistance is reduced and the current path of the device is less crowded, which reduces the resistance of the JFET and reduces the on-state resistance of the device as a whole.

The device structure corresponding to the dotted line AA-BB in FIG. 15 is: a thick field oxide layer is partially retained, JFET implantation is blocked by the thick field oxide layer, and the gate polysilicon material above the field oxide layer is removed.

Partially retaining the thick field oxide layer and removing the polysilicon gate material corresponding to the thick field oxide layer can effectively reduce the gate-drain parasitic capacitance of the device. At the same time, no JEFT implantation is performed in this region, so that the withstand voltage of the device will not be greatly affected by the JEFT implantation.

As a preferred solution, the vertical double diffused metal oxide semiconductor field effect transistor of the present invention is a P channel vertical double diffused metal oxide semiconductor field effect transistor, the first conductive type semiconductor is a P type semiconductor, and the second conductive type semiconductor is N-type semiconductor. Its device structure is similar to that of the N-channel vertical double-diffused metal-oxide-semiconductor field effect transistor, so it will not be repeated here.

In the vertical double-diffused metal oxide semiconductor field effect transistor of the present invention, the field oxide layer is intermittently provided between the gate oxide layer and the epitaxial layer, and the area where the field oxide layer is provided between the gate oxide layer and the epitaxial layer can be effectively reduced. The gate-drain parasitic capacitance of the vertical double-diffused metal oxide semiconductor field effect transistor improves the switching speed of the device. In addition, the region without the field oxide layer between the gate oxide layer and the epitaxial layer is convenient for device JFET implantation, and can effectively reduce the on-state resistance of the device.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (7)

1. A vertical double-diffused metal-oxide-semiconductor field-effect transistor structure, characterized in that it comprises, from bottom to top: a drain electrode, a first conductivity type semiconductor substrate, and a first conductivity type semiconductor epitaxial layer; the first The conductive type semiconductor epitaxial layer includes a second conductive type semiconductor first well region and a second conductive type semiconductor second well region separated from each other; A first source region of a semiconductor of the first conductivity type is arranged inside the first well region of the semiconductor of the second conductivity type, and a second source region of the semiconductor of the first conductivity type is arranged inside the second well region of the semiconductor of the second conductivity type; The first source region of the semiconductor of the first conductivity type and the first well region of the semiconductor of the second conductivity type are partially covered with the first source region, the second source region of the semiconductor of the first conductivity type and the second well region of the semiconductor of the second conductivity type partially covered with a second source region; A gate oxide layer is provided between the first source region and the second source region; A gate is arranged on the top of the gate oxide layer; a field oxide layer is intermittently arranged between the gate oxide layer and the epitaxial layer. 2 . The vertical double-diffused MOSFET structure according to claim 1 , wherein the semiconductor of the first conductivity type is an N-type semiconductor, and the semiconductor of the second conductivity type is a P-type semiconductor. 3 . The vertical double-diffused MOSFET structure according to claim 1 , wherein the semiconductor of the first conductivity type is a P-type semiconductor, and the semiconductor of the second conductivity type is an N-type semiconductor. 4 . 4. The vertical double-diffused metal oxide semiconductor field effect transistor structure according to claim 1, wherein the region corresponding to the gate and the field oxide layer is provided with a groove communicating with the gate oxide layer. 5. The vertical double-diffused MOSFET structure according to claim 1, wherein the gate is polysilicon. 6. The vertical double-diffused MOSFET structure according to claim 1, wherein the source and the drain are metal electrodes. 7. The vertical double-diffused metal oxide semiconductor field effect transistor structure according to claim 1, wherein both the field oxide layer and the gate oxide layer are insulating layers.