CN102479814B - Transistor and manufacturing method thereof - Google Patents
Transistor and manufacturing method thereof Download PDFInfo
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- CN102479814B CN102479814B CN201010558393.XA CN201010558393A CN102479814B CN 102479814 B CN102479814 B CN 102479814B CN 201010558393 A CN201010558393 A CN 201010558393A CN 102479814 B CN102479814 B CN 102479814B
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- Prior art keywords
- insulation column
- epitaxial loayer
- semiconductor substrate
- drain region
- source region
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000009413 insulation Methods 0.000 claims description 72
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000035755 proliferation Effects 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 7
- 238000002360 preparation method Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a transistor and a manufacturing method thereof. The method comprises the steps of: providing a semiconductor substrate; forming an insulating support on the semiconductor substrate; forming an epitaxial layer covering the semiconductor substrate and the insulating support, wherein the thickness of the epitaxial layer is larger than the height of the insulating support; forming a gate structure on the surface of the epitaxial layer, wherein the gate structure is located above the insulating support; and forming a source region and a drain region in the epitaxial layer at both sides of the gate structure, wherein the source region and the drain region are located at two sides of the insulating support. By adopting the manufacturing method provided by the invention, the short channel effect of the transistor is improved and the performance of the transistor is improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly transistor and preparation method thereof.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is manufactured, and it is widely used in various integrated circuits, and the doping type difference during according to main charge carrier and manufacture, is divided into NMOS and PMOS transistor.
Prior art provides a kind of transistorized manufacture method.Please refer to Fig. 1 to Fig. 3, is the transistorized manufacture method cross-sectional view of prior art.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, form gate dielectric layer 101 and grid 102 in described Semiconductor substrate 100, described gate dielectric layer 101 and grid 102 form grid structure.
Continue with reference to figure 1, carry out oxidation technology, form the oxide layer 103 that covers described grid structure.
Then, please refer to Fig. 2, form light doping section 104 in the Semiconductor substrate of grid structure both sides, described light doping section 104 forms by Implantation.
Then, please refer to Fig. 3, in the Semiconductor substrate of grid structure both sides, form the side wall 105 of grid structure.Carry out source/drain region heavy doping injection (S/D), in the interior formation of Semiconductor substrate 100 source region 106 and the drain region 107 of grid structure both sides.
In the Chinese patent application that is CN101789447A at publication number, can find more information about prior art.
Find in practice, the transistor short-channel effect that existing method is made is obvious, and the performance of device is undesirable.
Summary of the invention
The problem that the present invention solves has been to provide a kind of transistor and preparation method thereof, has suppressed transistorized short-channel effect, has improved transistorized performance.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form insulation column;
In described insulation column and Semiconductor substrate, form epitaxial loayer, the thickness of described epitaxial loayer is more than or equal to the height of described insulation column;
On epitaxial loayer, form grid structure, described grid structure is positioned at described insulation column top;
In the epitaxial loayer of described grid structure both sides, form source region and drain region, described source region and drain region are positioned at the both sides of described insulation column.
Alternatively, the material of described insulation column is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the width range of described insulation column is 5 nanometer～1 micron.
Alternatively, high 20～100 nanometers of the height of insulation column described in the Thickness Ratio of described epitaxial loayer.
Correspondingly, the present invention also provides a kind of transistor, comprising:
Semiconductor substrate;
Epitaxial loayer, is positioned in described Semiconductor substrate;
Grid structure, is positioned on described epitaxial loayer;
Insulation column, is positioned at the epitaxial loayer of described grid structure below, and the height of described insulation column is less than the thickness of described epitaxial loayer;
Source region, is positioned at the epitaxial loayer of described insulation column one side;
Drain region, is positioned at the epitaxial loayer of described insulation column opposite side.
Alternatively, the material of described insulation column is silica, silicon nitride, carborundum or silicon oxynitride.
Alternatively, the width range of described insulation column is 5 nanometer～1 micron.
Alternatively, high 20～100 nanometers of the height of insulation column described in the Thickness Ratio of described epitaxial loayer.
Compared with prior art, the present invention has the following advantages:
By form insulation column in Semiconductor substrate, then, form the epitaxial loayer that covers described insulation column, in described epitaxial loayer, form the source region and the drain region that are positioned at described insulation column both sides.Because described source region and drain region are positioned at the epitaxial loayer of the both sides of insulation column, thereby described insulation column can prevent the doping ion generation horizontal proliferation in described source region and drain region, improve transistorized short-channel effect, and described insulation column is between described source region or drain region and described Semiconductor substrate, thereby reduce the junction capacitance between described source region or drain region and Semiconductor substrate, reduce junction leakage, improved the performance of device.
Accompanying drawing explanation
Fig. 1～Fig. 3 is the preparation method of transistor cross-sectional view of prior art;
Fig. 4 is preparation method of transistor schematic flow sheet of the present invention;
Fig. 5～Figure 10 is the preparation method of transistor cross-sectional view of one embodiment of the invention.
Embodiment
The transistorized short-channel effect that existing method is made is obvious, and the performance of device is undesirable.Along with the development of semiconductor technology, super shallow junction technology is applied to makes source region and drain region, ion horizontal proliferation between source region and drain region is more serious, thereby make described short-channel effect more obvious, and there is larger junction capacitance and junction leakage in source region and drain region and Semiconductor substrate, thereby reduce the response speed of device, affected the performance of device.
In order to address the above problem, inventor proposes a kind of transistorized manufacture method, please refer to the preparation method of transistor schematic flow sheet of the present invention shown in Fig. 4, and described method comprises:
Step S1, provides Semiconductor substrate;
Step S2 forms insulation column in described Semiconductor substrate;
Step S3 forms epitaxial loayer in described insulation column and Semiconductor substrate, and the thickness of described epitaxial loayer is more than or equal to the height of described insulation column;
Step S4 forms grid structure on epitaxial loayer, and described grid structure is positioned at described insulation column top;
Step S5 forms source region and drain region in the epitaxial loayer of described grid structure both sides, and described source region and drain region are positioned at the both sides of described insulation column.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.
First, please refer to Fig. 5, Semiconductor substrate 200 is provided.Described Semiconductor substrate 200 materials can be silicon or germanium silicon.In described Semiconductor substrate 200, form insulating barrier 211.Described insulating barrier 211 utilizes chemical vapor deposition method to make.Described insulating barrier 211 is for making insulation column.Described insulation column is isolated source region or the drain region of follow-up formation.
The material of described insulating barrier 211 is selected from insulation material, and described insulation material can be silica, silicon nitride, carborundum or silicon oxynitride.
Then, please refer to Fig. 6, insulating barrier 211 described in partial etching forms insulation column 201 in described Semiconductor substrate 200.Described etching is wet etching.
In a preferred embodiment of the invention, the width of described insulation column 201 should be considered the width of the transistorized channel region that will form and design, preferably, the width of described insulation column 201 equals or approaches the width of described channel region, thereby makes described insulation column 201 can effectively isolate the diffusion of the doping ion in source region and drain region.
As an embodiment, the width range of described insulation column 201 is 5 nanometer～1 micron, and for example width of described insulation column 201 can be 5 nanometers, 500 nanometers or 1 micron.
Then, please refer to Fig. 7, at described Semiconductor substrate 200 and insulation column 201 growing epitaxial layers 203, the thickness of described epitaxial loayer 203 is more than or equal to the height of described insulation column 201.Described epitaxial loayer 203 utilizes epitaxial growth technology to make.
The thickness of described epitaxial loayer 203 is greater than the height of described insulation column 201, thereby can be used as the channel region between source region and the drain region of follow-up formation at the part epitaxial loayer 203 above insulation column 203.As an embodiment, large 10～100 nanometers of height of insulation column 201 described in the Thickness Ratio of described epitaxial loayer 203.
Then, please refer to Fig. 8, on described epitaxial loayer 203, form grid structure, described grid structure is positioned at described insulation column top.
As an embodiment, the manufacture method of described grid structure comprises:
On described epitaxial loayer 203, form gate dielectric layer 204, described gate dielectric layer 204 is positioned at described insulation column 201 tops, and the material of described gate dielectric layer 204 is preferably silica, and the thickness range of described gate dielectric layer 204 is 10～300 dusts;
On described gate dielectric layer 204, form grid 205, described grid 205 is positioned at described gate dielectric layer 204 tops, and the material of described grid 205 is polysilicon.
As the preferred embodiments of the present invention, after described grid structure forms, also need to form oxide layer 206 in described grid structure outside, described oxide layer 206, for the protection of described grid structure, prevents that described grid structure is subject to the damage of etching technics.In the present embodiment, the thickness range of described oxide layer 206 is 10～200 dusts.
Then, please refer to Fig. 9, in the interior formation of epitaxial loayer 203 light doping section 207 of described grid structure both sides.Described light doping section 207 forms by light dope Implantation.Light dope Implantation, as those skilled in the art's known technology, is not described in detail at this.
Then, please refer to Figure 10, form side wall 208 on epitaxial loayer 208 surfaces of described grid structure both sides.As an embodiment, described side wall 208 is the ONO structure that silica-silicon-nitride and silicon oxide forms.
Then,, take described grid structure and side wall 208 as mask, carry out source/leakage Implantation, in the interior formation of epitaxial loayer 203 source region 209 and the drain region 210 of described grid structure both sides.Described source region 209 and drain region 210 lay respectively in the epitaxial loayer 203 of described insulation column 201 both sides.Described source/leakage Implantation forms the method in source region 209 and drain region 210 as those skilled in the art's known technology, is not described in detail at this.
Through said method, the transistor arrangement of formation please refer to Figure 10.Described transistor comprises:
In the present embodiment, the material of described insulation column 201 is insulation material, and such as described insulation column 201 can be silica, silicon nitride, carborundum or silicon oxynitride etc.
As one embodiment of the present of invention, the width range of described insulation column 201 is 5 nanometer～1 micron.
The thickness of described epitaxial loayer 203 is higher than the height of described insulation column 201, thereby can be used as the conducting channel between described source region 209 and drain region 210 at the epitaxial loayer 203 of described insulation column 201.As an embodiment, large 10～100 nanometers of height of insulation column described in the Thickness Ratio of described epitaxial loayer 203.
To sum up, transistor provided by the invention and preparation method thereof, between source region and drain region, form insulation column, described insulation column can prevent the doping ion diffusion between source region and drain region, reduce transistorized short-channel effect, prevent from forming junction capacitance between source region and drain region and Semiconductor substrate, reduced junction leakage, improved transistorized performance.
Although oneself discloses the present invention as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (8)
1. a transistorized manufacture method, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form insulation column;
In described insulation column and Semiconductor substrate, form epitaxial loayer, the thickness of described epitaxial loayer is more than or equal to the height of described insulation column;
On epitaxial loayer, form grid structure, described grid structure is positioned at described insulation column top;
In the epitaxial loayer of described grid structure both sides, form source region and drain region, described source region and drain region are positioned at the both sides of described insulation column;
Wherein, the width of described insulation column equals the width of channel region, when the insulation column of described width is used for preventing the doping ion generation horizontal proliferation in source region and drain region, reduces the junction capacitance between source region or drain region and Semiconductor substrate.
2. transistorized manufacture method as claimed in claim 1, is characterized in that, the material of described insulation column is silica, silicon nitride, carborundum or silicon oxynitride.
3. transistorized manufacture method as claimed in claim 1, is characterized in that, the width range of described insulation column is 5 nanometer～1 micron.
4. transistorized manufacture method as claimed in claim 1, is characterized in that, high 20～100 nanometers of height of insulation column described in the Thickness Ratio of described epitaxial loayer.
5. a transistor, is characterized in that, comprising:
Semiconductor substrate;
Epitaxial loayer, is positioned in described Semiconductor substrate;
Grid structure, is positioned on described epitaxial loayer;
Insulation column, is positioned at the epitaxial loayer of described grid structure below, and the height of described insulation column is less than the thickness of described epitaxial loayer;
Source region, is positioned at the epitaxial loayer of described insulation column one side;
Drain region, is positioned at the epitaxial loayer of described insulation column opposite side;
Wherein, the width of described insulation column equals the width of channel region, when the insulation column of described width is used for preventing the doping ion generation horizontal proliferation in source region and drain region, reduces the junction capacitance between source region or drain region and Semiconductor substrate.
6. transistor as claimed in claim 5, is characterized in that, the material of described insulation column is silica, silicon nitride, carborundum or silicon oxynitride.
7. transistor as claimed in claim 5, is characterized in that, the width range of described insulation column is 5 nanometer～1 micron.
8. transistor as claimed in claim 5, is characterized in that, high 20～100 nanometers of height of insulation column described in the Thickness Ratio of described epitaxial loayer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010558393.XA CN102479814B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010558393.XA CN102479814B (en) | 2010-11-24 | 2010-11-24 | Transistor and manufacturing method thereof |
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| CN102479814A CN102479814A (en) | 2012-05-30 |
| CN102479814B true CN102479814B (en) | 2014-07-02 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365445B1 (en) * | 2001-05-01 | 2002-04-02 | Advanced Micro Devices, Inc. | Field effect transistor formed in SOI technology with semiconductor material having multiple thicknesses |
| CN1469491A (en) * | 2002-06-18 | 2004-01-21 | ���ǵ�����ʽ���� | Semiconductor device and manufacturing method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6365445B1 (en) * | 2001-05-01 | 2002-04-02 | Advanced Micro Devices, Inc. | Field effect transistor formed in SOI technology with semiconductor material having multiple thicknesses |
| CN1469491A (en) * | 2002-06-18 | 2004-01-21 | ���ǵ�����ʽ���� | Semiconductor device and manufacturing method thereof |
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| CN102479814A (en) | 2012-05-30 |
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