CN102456622A - Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove - Google Patents
Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove Download PDFInfo
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- CN102456622A CN102456622A CN2010105274688A CN201010527468A CN102456622A CN 102456622 A CN102456622 A CN 102456622A CN 2010105274688 A CN2010105274688 A CN 2010105274688A CN 201010527468 A CN201010527468 A CN 201010527468A CN 102456622 A CN102456622 A CN 102456622A
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- barrier schottky
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- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 230000004888 barrier function Effects 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000004026 adhesive bonding Methods 0.000 claims abstract description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 23
- 229910052760 oxygen Inorganic materials 0.000 claims description 23
- 239000001301 oxygen Substances 0.000 claims description 23
- 239000003292 glue Substances 0.000 claims description 11
- 238000003384 imaging method Methods 0.000 claims description 5
- 238000004380 ashing Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 11
- 238000001259 photo etching Methods 0.000 abstract description 6
- 238000000151 deposition Methods 0.000 abstract 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical group C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 5
- 239000002184 metal Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- -1 tetramethyl aqua ammonia Chemical compound 0.000 description 1
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Abstract
The invention provides a preparation method of a trench-type MOS (metal oxide semiconductor) barrier schottky groove, wherein the method comprises the following steps: depositing a field oxide layer on a substrate, gluing, photoetching and developing, etching the field oxide layer, and forming a window between an MOS region and a schottky contact region; gluing the surface of the structure obtained in the previous step, photoetching and developing, thus exposing the schottky contact region; etching a first groove with the first depth on the schottky contact region; and etching the surface of the structure obtained form the previous step, and etching to form a second groove with the second depth. According to the method provided by the invention, the residual photoresist in the groove can be removed effectively, the technology cost is lowered, and the technology quality is improved; and in addition, a mask plate is not required to be customized additionally for the method provided by the invention, and the method is compatible with the previous technology.
Description
Technical field
The invention belongs to the semiconductor fabrication process technical field, be specifically related to a kind of channel MOS barrier schottky groove preparation method.
Background technology
Channel MOS barrier schottky (TMBS) structure by the groove through etching realization, chip front side on substrate, the substrate or on the epitaxial loayer on the substrate as forming on the metal level of anode electrode and the chip back as the metal level of cathode electrode and the oxide layer between groove and the anode metal layer.Comprise MOS zone and Schottky contacts zone from the angle TMBS of electricity.
Above-mentioned groove also can be divided into MOS zone groove and Schottky contacts zone groove according to the angle of electricity.Because the oxide layer that needs etching Schottky contacts zone to cover when making the window in Schottky contacts zone, and etching process can etch into the substrate part under the window area usually, so the degree of depth of the regional groove of Schottky contacts is darker than the regional groove of MOS.
The process of prior art for preparing TMBS groove generally includes following steps:
1) semi-conductive substrate is provided, this substrate comprises MOS device region and Schottky contact region; 2) oxygen layer of deposit on said Semiconductor substrate; 2) gluing, and exposure imaging define the etching groove zone on the said Semiconductor substrate; 3) oxygen layer in etching field is to exposing said semiconductor substrate surface, and removes photoresist; 4) make mask with said oxygen layer, etching forms first groove with first degree of depth; 5) the body structure surface gluing that obtains in step 4), and photoetching development is removed the photoresist that covers said Schottky contact region; 6) make mask with said oxygen layer, be etched in said Schottky contacts zone and form second groove with second degree of depth.
In preparation TMBS configuration process, need be in above-mentioned deep trench gluing, remove photoresist at last.Because groove is darker, in groove, often there is photoresist remaining behind the glue of dieing.Removing residual photoresist needs ad hoc approach, has so increased the technology cost, to the processing quality influence obviously.
Summary of the invention
The technical problem that the present invention will solve provides a kind of channel MOS barrier schottky groove preparation method, and this preparation method has solved the problem of residual photoresist when the TMBS groove is made, and reduces the technology cost.
For solving the problems of the technologies described above, the present invention provides channel MOS barrier schottky groove preparation method, may further comprise the steps: 1) semi-conductive substrate is provided, and said substrate comprises the first area and the second area that is used to prepare Schottky that is used to prepare the MOS device; 2) at oxygen layer of said semiconductor substrate surface deposit; 3) gluing, and exposure imaging define the etching groove zone on the said Semiconductor substrate; 4) the field oxygen layer in the said etching groove of etching zone is to exposing said semiconductor substrate surface, and removes photoresist; 5) the body structure surface gluing that obtains in step 4), and exposure imaging is removed the photoresist that covers said second area; Make mask with said oxygen layer, form first groove in said second area etching with first degree of depth; 6) remove the photoresist that covers said first area; 7) make mask with said oxygen layer, etching forms second groove with second degree of depth in said first area, simultaneously said first etching groove is deepened second degree of depth.
Wherein, above-mentioned oxygen layer is low temperature oxide layer.
Above-mentioned concrete steps of removing photoresist comprise: 1) dry ashing; 2) wet method is removed.
The first above-mentioned groove is the groove of Schottky contacts zone substrate exposed area etching, and described second groove is the groove of MOS zone substrate exposed area etching.
The first depth range
said second depth range
The deposit of above-mentioned oxygen layer realizes through the CVD method.
Above-mentioned etching process adopts the plasma etching method.
Optional above-mentioned photoresist is positive glue.
Optional, above-mentioned photoresist is negative glue.
Channel MOS barrier schottky groove preparation method of the present invention avoids gluing in than deep trench, has solved the photoresist residue problem in groove that causes thus, has improved processing quality, has improved productivity ratio and has reduced the technology cost; Can adopt positive glue or negative glue in the photoetching, alternative big, and need not customize the additional masks plate during the course, existing technology promptly capable of using is operated, so workable.
Description of drawings
Fig. 1 is a channel MOS barrier schottky groove preparation method flow chart of steps provided by the invention;
Fig. 2-Fig. 7 is channel MOS barrier schottky groove preparation method flowage structure figure provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
Fig. 1 is a channel MOS barrier schottky groove preparation method flow chart of steps provided by the invention.
As shown in Figure 1, the channel MOS barrier schottky groove preparation method that this embodiment provides may further comprise the steps:
Step S11 provides semi-conductive substrate 100.
As shown in Figure 2, Semiconductor substrate 100 comprises MOS device region and Schottky contact region, and wherein, the MOS device region is used to make the MOS device, and Schottky contact region is used to make the Schottky contacts structure.
Step S12, deposit one deck field oxygen layer 101 on Semiconductor substrate 100.
As shown in Figure 3; In this embodiment; Field oxygen layer 101 is low temperature oxides; Thickness range 1000-5000
and deposit realize that through the CVD method oxygen layer 101 is used for serving as the mask of etching.As most preferred embodiment; Oxygen layer 101 adopts PE TEOX, thickness be 3000
its deposition process is PECVD.
Step S13, etching field oxygen layer be to exposing said semiconductor substrate surface, and remove photoresist, and be as shown in Figure 3.
In this embodiment, the developer solution that is adopted in the described developing process all adopts the tetramethyl aqua ammonia; Said process of removing photoresist, concrete steps are first dry ashings, and the rewetting method is removed.
As most preferred embodiment, photoresist 102 adopts positive glue.
As optional embodiment, photoresist 102 adopts negative glue.
Step S14, the body structure surface gluing that obtains at step S13, and photoetching development is removed the photoresist 102 that covers said Schottky contact region.
As shown in Figure 4, the MOS device region is made the MOS device, and Schottky contact region is made the Schottky contacts structure, and two zones are all covered by photoresist 102, and photoresist 102 tops cover a lithography mask version 103.
Step S15 makes mask with said oxygen layer 101, is etched in said Schottky contacts zone and forms first groove 104 with first degree of depth.
As shown in Figure 5, the groove width that etching obtains is 0.3 μ m-0.6 μ m; First depth bounds be 1000
the i.e. groove of substrate exposed area etching of first groove in Schottky contacts zone.
As most preferred embodiment first groove width is 0.35 μ m; First degree of depth be 2000
step S16, remove photoresist.
As shown in Figure 6, remove the photoresist that covers said MOS device region.
Step S17 makes mask with said oxygen layer 101, and etching forms second groove 105 with second degree of depth.
Figure 7 shows the second groove width of 0.3μm-0.6μm; second depth range of 6000
-11000
The second trench exposed area for the MOS region substrate etching trenches; second trench etched to said field oxide layer as a mask, the structure obtained in step S16, the surface etching; etching process, the first groove 104 may be simultaneously etched deeper second depth, time, the depth of the first groove 104: The first depth + second depth.
As a preferred embodiment, the channel type MOS Barrier Schottky trench preparation method, the second groove width dimension of 0.35μm; second depth of 7000
is the second groove depth of the groove 105 7000
first groove The final depth of the groove 104 9000
Channel MOS barrier schottky groove preparation method in this embodiment avoids gluing in than deep trench, has solved the photoresist residue problem in groove that causes thus, has improved processing quality, has improved productivity ratio and has reduced the technology cost; Can adopt positive glue or negative glue in the photoetching, alternative big, and need not customize the additional masks plate during the course, existing technology promptly capable of using is operated, so workable.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the specification.
Claims (9)
1. a channel MOS barrier schottky groove preparation method is characterized in that, may further comprise the steps: 1) semi-conductive substrate is provided, and said substrate comprises the first area and the second area that is used to prepare Schottky that is used to prepare the MOS device; 2) at oxygen layer of said semiconductor substrate surface deposit; 3) gluing, and exposure imaging define the etching groove zone on the said Semiconductor substrate; 4) the field oxygen layer in the said etching groove of etching zone is to exposing said semiconductor substrate surface, and removes photoresist; 5) the body structure surface gluing that obtains in step 4), and exposure imaging is removed the photoresist that covers said second area; Make mask with said oxygen layer, form first groove in said second area etching with first degree of depth; 6) remove the photoresist that covers said first area; 7) make mask with said oxygen layer, etching forms second groove with second degree of depth in said first area, simultaneously said first etching groove is deepened second degree of depth.
2. channel MOS barrier schottky groove preparation method according to claim 1 is characterized in that, said oxygen layer is low temperature oxide layer.
3. channel MOS barrier schottky groove preparation method according to claim 1 is characterized in that said concrete steps of removing photoresist comprise: 1) dry ashing; 2) wet method is removed.
4. channel MOS barrier schottky groove preparation method according to claim 1; It is characterized in that; Described first groove is the groove of Schottky contacts zone substrate exposed area etching, and described second groove is the groove of MOS zone substrate exposed area etching.
5. channel MOS barrier schottky groove preparation method according to claim 1; It is characterized in that, said first depth bounds be 1000
-4000
said second depth bounds be 6000-
11000
6. channel MOS barrier schottky groove preparation method according to claim 1 is characterized in that, the deposit of said oxygen layer realizes through the CVD method.
7. channel MOS barrier schottky groove preparation method according to claim 1 is characterized in that, said etching process adopts the plasma etching method.
8. according to any described channel MOS barrier schottky groove preparation method of claim 1-7, it is characterized in that said photoresist is positive glue.
9. according to any described channel MOS barrier schottky groove preparation method of claim 1-7, it is characterized in that said photoresist is negative glue.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010527468 CN102456622B (en) | 2010-10-29 | 2010-10-29 | Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove |
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|---|---|---|---|
| CN 201010527468 CN102456622B (en) | 2010-10-29 | 2010-10-29 | Preparation method of trench-type MOS (metal oxide semiconductor) barrier schottky groove |
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| CN102456622B CN102456622B (en) | 2013-10-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112666438A (en) * | 2019-09-30 | 2021-04-16 | 中国科学院半导体研究所 | Sample preparation and optimization method for researching silicon carbide MOS interface state by using DLTS |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020008237A1 (en) * | 2000-07-20 | 2002-01-24 | Advanced Power Devices | Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication |
| CN101621062A (en) * | 2008-06-30 | 2010-01-06 | 万国半导体股份有限公司 | Device structure and method for improving Schottky breakdown voltage without affecting MOSFET-Schottky integration |
| US7816732B2 (en) * | 2008-06-23 | 2010-10-19 | Force Mos Technology Co., Ltd. | Integrated trench MOSFET and Schottky rectifier with trench contact structure |
-
2010
- 2010-10-29 CN CN 201010527468 patent/CN102456622B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020008237A1 (en) * | 2000-07-20 | 2002-01-24 | Advanced Power Devices | Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication |
| US7816732B2 (en) * | 2008-06-23 | 2010-10-19 | Force Mos Technology Co., Ltd. | Integrated trench MOSFET and Schottky rectifier with trench contact structure |
| CN101621062A (en) * | 2008-06-30 | 2010-01-06 | 万国半导体股份有限公司 | Device structure and method for improving Schottky breakdown voltage without affecting MOSFET-Schottky integration |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112666438A (en) * | 2019-09-30 | 2021-04-16 | 中国科学院半导体研究所 | Sample preparation and optimization method for researching silicon carbide MOS interface state by using DLTS |
| CN112666438B (en) * | 2019-09-30 | 2023-06-06 | 中国科学院半导体研究所 | Sample preparation and optimization method for studying SiC MOS interface states by using DLTS |
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| CN102456622B (en) | 2013-10-09 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140506 |
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Effective date of registration: 20140506 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |