CN102420103A - Metal-insulator-metal capacitor structure of copper Damascus process and manufacturing process thereof - Google Patents
Metal-insulator-metal capacitor structure of copper Damascus process and manufacturing process thereof Download PDFInfo
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- CN102420103A CN102420103A CN2011101381543A CN201110138154A CN102420103A CN 102420103 A CN102420103 A CN 102420103A CN 2011101381543 A CN2011101381543 A CN 2011101381543A CN 201110138154 A CN201110138154 A CN 201110138154A CN 102420103 A CN102420103 A CN 102420103A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 174
- 239000002184 metal Substances 0.000 title claims abstract description 174
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 128
- 239000010949 copper Substances 0.000 title claims abstract description 128
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 127
- 239000003990 capacitor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims description 181
- 238000005530 etching Methods 0.000 claims description 29
- 239000011159 matrix material Substances 0.000 claims description 26
- 238000001259 photo etching Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- -1 SiOCH Chemical compound 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 150000001879 copper Chemical class 0.000 claims 1
- 239000010410 layer Substances 0.000 description 176
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000015847 Hesperis matronalis Nutrition 0.000 description 1
- 240000004533 Hesperis matronalis Species 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
According to the structure of the metal-insulating layer-metal capacitor in the copper Damascus process and the manufacturing process thereof, two mask plates are added, and the metal-insulating layer-metal capacitor and the inductor are simultaneously manufactured by using a single Damascus process, so that the metal-insulating layer-metal double-layer capacitor structure produced by the technical scheme of the invention can be completely compatible with the copper Damascus process of a CMOS logic circuit and the inductor, and the density of the metal-insulating layer-metal capacitor is increased.
Description
Technical field
The present invention relates to a kind of copper Damascus technics, relate in particular to a kind of copper Damascus technics metal-insulator-metal (Metal-Insulator-Metal is called for short MIM) capacitance structure and manufacturing approach.
Background technology
Along with reducing of feature sizes of semiconductor devices, the semiconductor rear section copper wiring replaces aluminum manufacturing procedure becomes main flow technology.In mixed signal and radio circuit, the exploitation mim capacitor structure and the manufacturing process of the copper Damascus technics of CMOS compatible logical circuit and inductance fully necessitates.This has not only improved the complexity of technology; And use low resistance copper can improve the MIM capacitive property as battery lead plate.
Patent US6329234, the structure and the technological process of process for copper CMOS compatible metal dielectric layer metal capacitor, the technical scheme that it adopted is in double damask structure, to make individual layer Damascus MIM electric capacity.
Patent US6670237, the structure and the technological process of process for copper CMOS compatible metal dielectric layer metal capacitor, the technical scheme that it adopted is in the through-hole structure of single Damascus, to make individual layer Damascus MIM electric capacity.
And, must reduce the MIM capacity area along with the reducing of semiconductor dimensions.This just requires to increase capacitance density.
Double-deck mim capacitor structure and copper Damascus manufacturing process that the present invention proposes, the MIM of the copper Damascus technics of CMOS compatible logical circuit and inductance, and increase fully capacitance density.
Summary of the invention
The invention discloses a kind of copper Damascus technics metal-insulating layer-metal capacitor structure and manufacturing approach, fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase the MIM capacitance density.
Above-mentioned purpose of the present invention realizes through following technical scheme:
A kind of copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach, wherein,
Deposit one matrix dielectric layer forms first electrode trenches and metal interconnected line trenches through Damascus technics on matrix, and makes first electrode and metal interconnecting wires;
Deposit first dielectric barrier layer and first dielectric layer successively on the matrix dielectric layer;
Etching first dielectric layer, first dielectric barrier layer form second electrode trenches, make the bottom of said second electrode trenches contact said first electrode;
Deposit forms first insulating barrier, makes said first insulating barrier cover said first dielectric layer and said second electrode trenches;
Form through hole through photoetching and etching, make said through hole pass said first insulating barrier, said first dielectric layer and said first dielectric barrier layer, contact said metal interconnecting wires;
At through hole and be coated with that deposit forms metal barrier and copper seed layer in second electrode trenches of first insulating barrier, and fill metallic copper, carry out the cmp planarization afterwards,, form second electrode and through hole line to remove excess metal;
Deposit second dielectric barrier layer and second dielectric layer on said first dielectric layer successively;
Etching second dielectric layer, second dielectric barrier layer form the third electrode groove, make the bottom of said third electrode groove contact said second electrode;
Deposit forms second insulating barrier, makes said second insulating barrier cover said second dielectric layer and said third electrode groove;
Etching second insulating barrier, second dielectric layer, second dielectric barrier layer form the first line groove and the second line groove; Make the said first line groove pass said second insulating barrier, said second dielectric layer and said second dielectric barrier layer, contact said through hole line; Make the said second line groove pass said second insulating barrier, said second dielectric layer and said second dielectric barrier layer, contact said second electrode;
At the first line groove, the second line groove and be coated with that deposit forms metal barrier and copper seed layer in the third electrode groove of second insulating barrier; Fill metallic copper; And carry out the cmp planarization; To remove excess metal, form third electrode, the first groove line and the second groove line.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach; Wherein, Said Damascus technics is specially: through photoetching be etched on the matrix dielectric layer and form first electrode trenches and metal interconnected line trenches, depositing metal barrier layer and copper seed layer; In first electrode trenches and metal interconnected line trenches, fill metallic copper; The cmp planarization to remove excess metal, forms first electrode and metal interconnecting wires.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach; Wherein, form said matrix dielectric layer, said first dielectric layer, said second dielectric layer, said first dielectric barrier layer and said second dielectric barrier layer through chemical vapor deposition.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach, wherein, the material of the said matrix dielectric layer of deposit, said first dielectric layer and said second dielectric layer is chosen from SiO2, SiOCH, FSG etc.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach, wherein, said first dielectric barrier layer of deposit and said second dielectric barrier layer material are chosen from SiN, SiCN etc.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach wherein, forms said metal barrier and copper seed layer through physical vapor deposition.
Aforesaid copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach, wherein, the material of the said metal barrier of deposit is TaN or Ta.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, through the copper the prevented diffusion dielectric layer of chemical vapor deposition or atomic layer deposition guarantor type, to form said first insulating barrier and said second insulating barrier.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, can prevent that copper diffusion dielectric layer often adopts silicon nitride.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, all is deposited with the high sacrificing protection layer of one deck etching selection ratio, to avoid the damage of successive process to insulating barrier on said first insulating barrier and said second insulating barrier.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, the sacrificing protection layer that before carrying out the physical vapor deposition metal barrier, will be deposited on respectively on said first insulating barrier and said second insulating barrier is removed.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, through the double-deck dielectric layer of chemical vapor deposition or atomic layer deposition to form said first insulating barrier and said second insulating barrier.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor wherein, is used SiN layer and SiO2 layer institute as double-deck dielectric layer, or is used SiN layer and high dielectric constant material layer as double-deck dielectric layer.
The manufacturing approach of aforesaid copper Damascus technics metal-insulating layer-metal capacitor, wherein, said high dielectric constant material adopts HfO, ZrO, AlO, LaO etc.
A kind of structure of copper Damascus technics metal-insulating layer-metal capacitor, wherein,
Be coated with a matrix dielectric layer in one substrate; The upper surface of said matrix dielectric layer is provided with first electrode trenches and metal interconnected line trenches; Said first electrode trenches and said metal interconnecting wires grooved inner surface all are coated with metal barrier; And fill metallic copper in said first electrode trenches and the said metal interconnected line trenches, respectively as first electrode and metal interconnecting wires;
Be provided with one first dielectric barrier layer and one first dielectric layer on the said matrix dielectric layer successively; Offer second electrode trenches and through hole on said first dielectric layer; Said second electrode trenches passes said first dielectric layer and said first dielectric barrier layer terminates in said first electrode; Said through hole passes said first dielectric layer and said first dielectric barrier layer terminates in said metal interconnecting wires; The said second electrode trenches inner surface is coated with one first insulating barrier and metal barrier successively, and to be filled with metallic copper in said second electrode trenches be second electrode; Said through-hole wall and bottom are provided with metal barrier, and all to be filled with metallic copper in the said through hole be the through hole line;
Be provided with one second dielectric barrier layer and one second dielectric layer on said first dielectric layer successively; Said second dielectric layer is provided with third electrode groove, the first line groove and the second line groove; Said third electrode groove passes said second dielectric layer and said second dielectric barrier layer terminates in said second electrode; The said first line groove passes said second dielectric layer and said second dielectric barrier layer terminates in said through hole line, and the said second line groove passes said second dielectric layer and said second dielectric barrier layer terminates in said second electrode; Said third electrode grooved inner surface is coated with one second insulating barrier and metal barrier successively, and to be filled with metallic copper in the said third electrode groove be third electrode; The said first line grooved inner surface is coated with metal barrier, and to be filled with metallic copper in the said first line groove be the first groove line; The said second line trench wall is coated with metal barrier, and to be filled with metallic copper in the said second line groove be the second groove line.
In sum; Owing to adopted technique scheme; The structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; Through adding two mask plates; Use single Damascus technics to make metal-insulating layer-metal capacitor and inductance simultaneously, make the metal-insulator-metal double layer capacity structure produced through technical scheme of the present invention fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase metal-insulating layer-metal capacitor density.
Description of drawings
Fig. 1 is structure and formation first electrode of manufacturing process and the structural representation behind the metal interconnecting wires of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 2 is structure and deposit first dielectric barrier layer of manufacturing process and the structural representation behind first dielectric layer of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 3 is the structural representation after photoetching and the etching of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second electrode trenches;
Fig. 4 is the structural representation after the deposit of completion first insulating barrier of structure and manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 5 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation through hole of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 6 is structure and formation second electrode of manufacturing process and the structural representation behind the through hole line of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 7 is the structural representation after the deposit of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second dielectric barrier layer and second dielectric layer;
Fig. 8 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation third electrode groove of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Fig. 9 is the structural representation after the deposit of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second insulating barrier;
Figure 10 is the structural representation after photoetching and the etching of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms the first line groove and the second line groove;
Figure 11 is the structural representation behind the formation third electrode, the first groove line, the second groove line of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention;
Figure 12 is the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and the circuit diagram of manufacturing process thereof.
Embodiment
Be further described below in conjunction with the accompanying drawing specific embodiments of the invention:
A kind of copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach, wherein,
Fig. 1 is structure and formation first electrode of manufacturing process and the structural representation behind the metal interconnecting wires of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 1; Form first electrode trenches 3011 and metal interconnected line trenches 4011 through Damascus technics chemical wet etching on matrix dielectric layer 101; Depositing metal barrier layer 801 and copper seed layer; Electroplate and fill metallic copper, excess metal is removed in the cmp planarization, makes first electrode 301 and metal interconnecting wires 401;
Fig. 2 is structure and deposit first dielectric barrier layer of manufacturing process and the structural representation behind first dielectric layer of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 2; Deposit first dielectric barrier layer 201 and first dielectric layer 102 successively on matrix dielectric layer 101; Because first electrode 301 all is formed in the matrix dielectric layer 101 with metal interconnecting wires 401, so first dielectric barrier layer covers first electrode 301 with metal interconnecting wires 401 fully;
Fig. 3 is the structural representation after photoetching and the etching of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second electrode trenches; See also Fig. 3; The spin coating photoresist forms the figure of said second electrode 302 through photoetching, afterwards etching first dielectric layer 102, first dielectric barrier layer 201; To form second electrode trenches 3021; Open first dielectric barrier layer 201, make the bottom of said second electrode trenches 3021 contact said first electrode 301, said second electrode trenches, 3021 parts are positioned at first electrode, 301 tops;
Fig. 4 is the structural representation after the deposit of completion first insulating barrier of structure and manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 4; Deposit forms first insulating barrier 3022; Make said first insulating barrier 3022 cover said first dielectric layer 102 and said second electrode trenches 3021, that is to say that first insulating barrier 3022 covers the upper surface of first dielectric layer 102 and the inwall of second electrode trenches 3021;
Fig. 5 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation through hole of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 5; Form through hole 4021 through photoetching and etching; Make said through hole 4021 pass said first insulating barrier 3022, said first dielectric layer 102 and said first dielectric barrier layer 201; Contact said metal interconnecting wires 401, that is to say and in etching process, open first insulating barrier 3022, first dielectric layer 102 and said first dielectric barrier layer 201;
Fig. 6 is structure and formation second electrode of manufacturing process and the structural representation behind the through hole line of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 6; At through hole and be coated with depositing metal barrier layer 801 and copper seed layer in second electrode trenches 3021 of first insulating barrier 3022; Fill metallic copper (ECP); Excess metal is removed in cmp (CMP) planarization; To form second electrode 302 and through hole line 402, in the process of depositing metal barrier layer 801 and copper seed layer and plated metal copper, metal barrier 801 and metallic copper can cover first dielectric layer 102 above; Can directly the metallic copper and the metal barrier 801 that cover above first dielectric layer 102 be removed through carrying out the chemical grinding planarization, first insulating barrier 3022 of same first dielectric layer, 102 upper surfaces also can be removed in process of lapping;
Fig. 7 is the structural representation after the deposit of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second dielectric barrier layer and second dielectric layer; See also Fig. 7; Deposit second dielectric barrier layer 202 and second dielectric layer 103 on said first dielectric layer 102 successively; Wherein, Because second electrode 302 and through hole line 402 all are formed on first dielectric layer 102, second dielectric barrier layer 202 and second dielectric layer 103 cover on second electrode 302 and the through hole line 402 simultaneously;
Fig. 8 is structure and the photoetching of manufacturing process and the structural representation behind the etching formation third electrode groove of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Fig. 8, spin coating photoresist on second dielectric layer 103 is through the figure of photoetching formation third electrode 303; Etching second dielectric layer 103, second dielectric barrier layer 202 afterwards; To form third electrode groove 3031, open second dielectric barrier layer 202, make the bottom of said third electrode groove 3031 contact said second electrode 302; Third electrode groove 3031 is positioned at the top of second electrode 302, is connected with second electrode 302;
Fig. 9 is the structural representation after the deposit of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms second insulating barrier; See also Fig. 9; Deposit forms second insulating barrier 3032; Make said second insulating barrier 3032 cover said second dielectric layer 103 and said third electrode groove 3031, that is to say that second insulating barrier 3032 of deposit has covered the upper surface of second dielectric layer 103 and the inwall of third electrode groove 3031;
Figure 10 is the structural representation after photoetching and the etching of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention forms the first line groove and the second line groove; See also Figure 10; Form the first line groove 4031 and the second line groove 5011 through photoetching and etching; Be etching second insulating barrier 3032, second dielectric layer 103, second dielectric barrier layer 202, form the first line groove 4031 and the second line groove 5011, make the said first line groove 4031 pass said second insulating barrier 3032, said second dielectric layer 103 and said second dielectric barrier layer 202; Contact said through hole line 402; Make the said second line groove 5011 pass said second insulating barrier 3032, said second dielectric layer 103 and said second dielectric barrier layer 202, contact said second electrode 302, that is to say; In one embodiment of the invention; Open second insulating barrier 3032, second dielectric layer 103 and second dielectric barrier layer, 202, the first electrode trenches, 4031 bottoms in the etching process and be communicated with through hole line 402, the second line groove, 5011 bottoms are connected with second electrode 302;
Figure 11 is the structural representation behind the formation third electrode, the first groove line, the second groove line of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Figure 11; At the first line groove 4031, the second line groove 5011 and be coated with depositing metal barrier layer 801 and copper seed layer in the third electrode groove 3031 of second insulating barrier 3032; Electroplate afterwards and fill metallic copper; Excess metal is removed in the cmp planarization, to form third electrode 303, the first groove line 403 and the second groove line 501, in the process of depositing metal barrier layer 801 and copper seed layer and plated metal copper; Metal barrier 801 and metallic copper can cover second dielectric layer 103 above; Can directly the metallic copper and the metal barrier 801 that cover above second dielectric layer 103 be removed through carrying out the cmp planarization, same, second insulating barrier 3032 of second dielectric layer, 103 upper surfaces also can be removed simultaneously.
Form said matrix dielectric layer 101, said first dielectric layer 102, said second dielectric layer 103, said first dielectric barrier layer 201 and said second dielectric barrier layer 202 through chemical vapor deposition (CVD) among the present invention.
The material of the said matrix dielectric layer of deposit 101, first dielectric layer 102 and said second dielectric layer 103 is chosen from SiO2, SiOCH, FSG etc. among the present invention.
Said first dielectric barrier layer 201 of deposit and said second dielectric barrier layer, 202 materials are chosen from SiN, SiCN etc. among the present invention.
Form said metal barrier 801 and copper seed layer through physical vapor deposition (PVD) among the present invention.
The material of the said metal barrier of deposit is TaN or Ta among the present invention.
The copper prevented through chemical vapor deposition or atomic layer deposition guarantor type among the present invention spreads dielectric layer, to form said first insulating barrier 3022 and said second insulating barrier 3032.
Can prevent described in the present invention that copper diffusion dielectric layer often adopts the silicon nitride of guarantor's type.
Make said first electrode trenches 3011 identical among the present invention in the etching process, so that the thickness of the thickness of said first electrode 301 and said metal interconnecting wires 401 is suitable with the degree of depth of said metal interconnected line trenches 4011.
Make said second electrode trenches 3021 identical among the present invention in the etching process, so that the height of the thickness of said second electrode 302 and said through hole line 402 is suitable with said through hole 4021 degree of depth.
Be that said third electrode groove 3031 is identical with the degree of depth of the said first line groove 4031 and the second line groove 5011 in the etching process among the present invention, so that the thickness of the thickness of said third electrode 303 and the said first groove line 403 and the second groove line 501 is suitable.
All be deposited with the high sacrificing protection layer of one deck etching selection ratio on first insulating barrier 3022 and said second insulating barrier 3032 described in the present invention, to avoid the damage of successive process to insulating barrier.
Before carrying out physical vapor deposition metal barrier 801, will be deposited on said first insulating barrier 3022 among the present invention respectively removes with the sacrificing protection layer on said second insulating barrier 3032.
Among the present invention through the double-deck dielectric layer of chemical vapor deposition or atomic layer deposition to form said first insulating barrier 3022 and said second insulating barrier 3032.
Use SiN layer and SiO2 layer institute as double-deck dielectric layer among the present invention, or use SiN layer and high dielectric constant material layer as double-deck dielectric layer.
High dielectric constant material described in the present invention adopts HfO, ZrO, AlO, LaO etc.
Figure 11 is the structural representation behind the formation third electrode, the first groove line, the second groove line of structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; See also Figure 11; A kind of structure of copper Damascus technics metal-insulating layer-metal capacitor; Wherein
Be coated with a matrix dielectric layer 101 in one substrate; The upper surface of said matrix dielectric layer 101 is provided with first electrode trenches 3011 and metal interconnected line trenches 4011; The degree of depth of first electrode trenches 3011 is identical with the degree of depth of metal interconnected line trenches 4011; Said first electrode trenches 3011 and said metal interconnected line trenches 4011 inner surfaces all are coated with metal barrier 801, and are filled with metallic copper in said first electrode trenches 3011 and the said metal interconnected line trenches 4011, respectively as first electrode 301 and metal interconnecting wires 401; Wherein, the thickness of the thickness of first electrode 301 and said metal interconnecting wires 401 is suitable;
Be provided with one first dielectric barrier layer 201 and one first dielectric layer 102 on the said matrix dielectric layer 101 successively; Offer second electrode trenches 3021 and through hole 4021 on said first dielectric layer 102; Said second electrode trenches 3021 passes said first dielectric layer 102 and said first dielectric barrier layer 201 terminates in said first electrode 301; Said through hole 4021 passes said first dielectric layer 102 and said first dielectric barrier layer 201 terminates in said metal interconnecting wires 401; The degree of depth of second electrode trenches 3021 is identical with the degree of depth of through hole 4021; Said second electrode trenches, 3021 inner surfaces are coated with one first insulating barrier 3022 and metal barrier 801 successively, and to be filled with metallic copper in said second electrode trenches 3021 be second electrode 302; Said through hole 4021 inwalls and bottom are provided with metal barrier 801, and to be filled with metallic copper in the said through hole 4021 be through hole line 402, and wherein, the height of the thickness of second electrode 302 and through hole line 402 is suitable;
Be provided with one second dielectric barrier layer 202 and one second dielectric layer 103 on said first dielectric layer 102 successively; Said second dielectric layer 103 is provided with third electrode groove 3031 and the first line groove 4031 and the second line groove 5011; Said third electrode groove 3031 passes said second dielectric layer 103 and said second dielectric barrier layer 202 terminates in said second electrode 302; The said first line groove 4031 passes said second dielectric layer 103 and said second dielectric barrier layer 202 terminates in said through hole line 402; The said second line groove 5011 passes said second dielectric layer 103 and said second dielectric barrier layer 202 terminates in said second electrode 302; The degree of depth of the first line groove 4031 and the second line groove 5011 is identical with the degree of depth of third electrode groove 3031; Said third electrode groove 3031 inner surfaces are coated with one second insulating barrier 3032, metal barrier 801 successively, and to be filled with metallic copper in the said third electrode groove 3031 be third electrode 303; Said first line groove 4031 and the second line groove, 5011 inner surfaces are coated with metal barrier 801; And be filled with metallic copper in the said first line groove 4031 and the second line groove 5011 and be respectively the first groove line 403 and the second groove line 501; Wherein, the thickness of third electrode 303 and the first groove line 403 are suitable with the second groove line, 501 thickness.
Figure 12 is the structure of copper Damascus technics metal-insulating layer-metal capacitor of the present invention and the circuit diagram of manufacturing process thereof; See also Figure 12; Produce metal-insulating layer-metal capacitor through technology provided by the invention and structure; The electric capacity that forms has two, is provided with an electric capacity between first electrode and second electrode, is provided with an electric capacity equally between the third electrode and second electrode.
Disclosed structure of the present invention and processing step are in the single-layer metal layer, to make multiple layer metal-insulating barrier-metal capacitance; Certainly the present invention is not limited only to single-layer metal, and the disclosed method and structure of the present invention is applicable to too makes the more metal-insulating layer-metal capacitor of multilayer in the multiple layer metal.
In sum; Owing to adopted technique scheme; The structure and the manufacturing process thereof of copper Damascus technics metal-insulating layer-metal capacitor of the present invention; Through adding two mask plates; Use single Damascus technics to make metal-insulating layer-metal capacitor and inductance simultaneously, make the metal-insulator-metal double layer capacity structure produced through technical scheme of the present invention fully CMOS compatible logical circuit and inductance the copper Damascus technics, and increase metal-insulating layer-metal capacitor density.
More than specific embodiment of the present invention is described in detail, but it is just as example, the present invention is not restricted to the specific embodiment of above description.To those skilled in the art, any equivalent modifications that the present invention is carried out with substitute also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of being done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (15)
1. a copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach is characterized in that,
Deposit one matrix dielectric layer forms first electrode trenches and metal interconnected line trenches through Damascus technics on matrix, and makes first electrode and metal interconnecting wires;
Deposit first dielectric barrier layer and first dielectric layer successively on the matrix dielectric layer;
Etching first dielectric layer, first dielectric barrier layer form second electrode trenches, make the bottom of said second electrode trenches contact said first electrode;
Deposit forms first insulating barrier, makes said first insulating barrier cover said first dielectric layer and said second electrode trenches;
Form through hole through photoetching and etching, make said through hole pass said first insulating barrier, said first dielectric layer and said first dielectric barrier layer, connect said metal interconnecting wires;
At through hole and be coated with that deposit forms metal barrier and copper seed layer in second electrode trenches of first insulating barrier, and fill metallic copper, carry out the cmp planarization afterwards,, form second electrode and through hole line to remove excess metal;
Deposit second dielectric barrier layer and second dielectric layer on said first dielectric layer successively;
Etching second dielectric layer, second dielectric barrier layer form the third electrode groove, make the bottom of said third electrode groove contact said second electrode;
Deposit forms second insulating barrier, makes said second insulating barrier cover said second dielectric layer and said third electrode groove;
Etching second insulating barrier, second dielectric layer, second dielectric barrier layer form the first line groove and the second line groove; Make the said first line groove pass said second insulating barrier, said second dielectric layer and said second dielectric barrier layer, contact said through hole line; Make the said second line groove pass said second insulating barrier, said second dielectric layer and said second dielectric barrier layer, contact said second electrode;
At the first line groove, the second line groove and be coated with that deposit forms metal barrier and copper seed layer in the third electrode groove of second insulating barrier; Fill metallic copper; And carry out the cmp planarization; To remove excess metal, form third electrode, the first groove line and the second groove line.
2. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1; It is characterized in that; Said Damascus technics is specially: through photoetching be etched on the matrix dielectric layer and form first electrode trenches and metal interconnected line trenches, depositing metal barrier layer and copper seed layer; In first electrode trenches and metal interconnected line trenches, fill metallic copper; The cmp planarization to remove excess metal, forms first electrode and metal interconnecting wires.
3. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1; It is characterized in that, form said matrix dielectric layer, said first dielectric layer, said second dielectric layer, said first dielectric barrier layer and said second dielectric barrier layer through chemical vapor deposition.
4. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1 is characterized in that the material of the said matrix dielectric layer of deposit, said first dielectric layer and said second dielectric layer is chosen from SiO2, SiOCH, FSG etc.
5. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1 is characterized in that said first dielectric barrier layer of deposit and said second dielectric barrier layer material are chosen from SiN, SiCN etc.
6. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1 is characterized in that, forms said metal barrier and copper seed layer through physical vapor deposition.
7. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 1 is characterized in that the said metal barrier layer material of deposit is TaN or Ta.
8. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 1; It is characterized in that; Through the copper the prevented diffusion dielectric layer of chemical vapor deposition or atomic layer deposition guarantor type, to form said first insulating barrier and said second insulating barrier.
9. copper Damascus technics metal-insulating layer-metal capacitor manufacturing approach according to claim 8 is characterized in that, saidly prevents that copper diffusion dielectric layer often adopts silicon nitride.
10. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 1; It is characterized in that; All be deposited with the high sacrificing protection layer of one deck etching selection ratio on said first insulating barrier and said second insulating barrier, to avoid the damage of successive process to insulating barrier.
11. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 10; It is characterized in that the sacrificing protection layer that before carrying out the physical vapor deposition metal barrier, will be deposited on respectively on said first insulating barrier and said second insulating barrier is removed.
12. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 1 is characterized in that, through the double-deck dielectric layer of chemical vapor deposition or atomic layer deposition to form said first insulating barrier and said second insulating barrier.
13. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 12 is characterized in that, uses SiN layer and SiO2 layer institute as double-deck dielectric layer, or uses SiN layer and high dielectric constant material layer as double-deck dielectric layer.
14. the manufacturing approach of copper Damascus technics metal-insulating layer-metal capacitor according to claim 13 is characterized in that, said high dielectric constant material adopts HfO, ZrO, AlO, LaO etc.
15. the structure of a copper Damascus technics metal-insulating layer-metal capacitor is characterized in that,
Be coated with a matrix dielectric layer in one substrate; The upper surface of said matrix dielectric layer is provided with first electrode trenches and metal interconnected line trenches; Said first electrode trenches and said metal interconnecting wires grooved inner surface all are coated with metal barrier; And fill metallic copper in said first electrode trenches and the said metal interconnected line trenches, respectively as first electrode and metal interconnecting wires;
Be provided with one first dielectric barrier layer and one first dielectric layer on the said matrix dielectric layer successively; Offer second electrode trenches and through hole on said first dielectric layer; Said second electrode trenches passes said first dielectric layer and said first dielectric barrier layer terminates in said first electrode; Said through hole passes said first dielectric layer and said first dielectric barrier layer terminates in said metal interconnecting wires; The said second electrode trenches inner surface is coated with one first insulating barrier and metal barrier successively, and to be filled with metallic copper in said second electrode trenches be second electrode; Said through-hole wall and bottom are provided with metal barrier, and all to be filled with metallic copper in the said through hole be the through hole line;
Be provided with one second dielectric barrier layer and one second dielectric layer on said first dielectric layer successively; Said second dielectric layer is provided with third electrode groove, the first line groove and the second line groove; Said third electrode groove passes said second dielectric layer and said second dielectric barrier layer terminates in said second electrode; The said first line groove passes said second dielectric layer and said second dielectric barrier layer terminates in said through hole line, and the said second line groove passes said second dielectric layer and said second dielectric barrier layer terminates in said second electrode; Said third electrode grooved inner surface is coated with one second insulating barrier and metal barrier successively, and to be filled with metallic copper in the said third electrode groove be third electrode; The said first line grooved inner surface is coated with metal barrier, and to be filled with metallic copper in the said first line groove be the first groove line; The said second line trench wall is coated with metal barrier, and to be filled with metallic copper in the said second line groove be the second groove line.
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| US20210343829A1 (en) * | 2014-04-30 | 2021-11-04 | Stmicroelectronics, Inc. | Dram interconnect structure having ferroelectric capacitors exhibiting negative capacitance |
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| CN102420103B (en) | 2013-09-11 |
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