CN102426819B - Establishment voltage circuit for Y-driving circuit of color plasma display panel - Google Patents
Establishment voltage circuit for Y-driving circuit of color plasma display panel Download PDFInfo
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- CN102426819B CN102426819B CN 201110409299 CN201110409299A CN102426819B CN 102426819 B CN102426819 B CN 102426819B CN 201110409299 CN201110409299 CN 201110409299 CN 201110409299 A CN201110409299 A CN 201110409299A CN 102426819 B CN102426819 B CN 102426819B
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- feeder ear
- voltage
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Abstract
The invention relates to a driving circuit of a color plasma display panel, in particular to an initial voltage circuit for a Y-driving circuit of the color plasma display panel. Aiming at the problems in the prior art, the invention provides an establishment voltage circuit for the Y-driving circuit of the color plasma display panel. The loss of the establishment voltage circuit is reduced in a mode of using a two-stage establishment voltage circuit. In the establishment voltage circuit, the design is realized by each original mutual connection. The establishment voltage circuit is mainly applied to the field of Y-driving circuit control of the color plasma display panels.
Description
Technical field
The present invention relates to the driving circuit of color plasma display, especially relate to a kind of initial voltage circuit for color plasma display Y driving circuit.
Background technology
Plasma scope (Plasma Display Panel, be called for short PDP), be a kind of display device that develops rapidly in recent years, it mainly is to utilize gas discharge to produce the excited by vacuum ultraviolet light-emitting phosphor, and this process is finished by driving and control circuit control.Driving circuit is produced and is driven required high drive waveform by the logical control waveform control that Drive and Control Circuit produces, and finally finishes the scanning addressing and keeps the demonstration image.In addition, utilize the editable logic waveform generator of Drive and Control Circuit part, realize the adjustment of shape, pulsewidth, energy parameter release time, display brightness and the other times parameter of high drive waveform.
In general plasma scope has various structure according to the difference of its type of drive, needed voltage also is different, electric pressure commonly used has: about logic voltage Vcc(5V), about addressing voltage Va(55V), keep about voltage Vsus(200 V), scanning voltage Vsc (about 150V), the Ve voltage segment of X drive part etc.Above voltage one is removed by keeping voltage Vsus(200V) through the DC/DC(DC-DC) the conversion generation, design is on drive circuit board.
As shown in Figure 1a, the Y driving circuit generally comprises a power tube Q0, the magnitude of voltage that power pack is provided by the Vsus feeder ear, the control input signal is by the work of control power tube Q0 grid, make the source class conducting of power tube Q0 drain electrode and power tube Q0, thereby make the YG output voltage values rise to the magnitude of voltage that the Vsus feeder ear provides gradually, circuit power consumption synoptic diagram such as Fig. 1 (b)
P1=（I1*Vsus）*t1/2， （1）
Wherein Vsus is equivalent to △ V among Fig. 1 a.
Summary of the invention
The present invention is directed to problems of the prior art, a kind of potential circuit of setting up for color plasma display Y driving circuit is provided, use two stages to set up the potential circuit mode, reduce to set up the loss of potential circuit.
For achieving the above object, the technical solution used in the present invention is:
A kind of potential circuit of setting up for color plasma display Y driving circuit, comprise the first power tube Q1, the first diode D1, the Ve feeder ear, the second power tube Q2, the second diode D2, the 3rd power tube D3, first resistance R 1, second resistance R 2, the Vsus feeder ear, the Vcc_YG feeder ear, described Ve feeder ear is connected with first power tube Q1 drain electrode by the first diode D1, the control input signal is input to the first power tube Q1 grid, described Vcc_YG feeder ear is by the 3rd diode D3, second resistance R 2 is connected with the second power tube Q2 grid, second power tube Q2 drain electrode is connected with the Vsus feeder ear, the second diode D2 anode is connected with the second power tube Q2 source class, first resistance R, 1 two ends respectively with the second power tube Q2 grid, the second power tube Q2 source class connects, the second diode D2 negative electrode and the first diode D1, the first power tube Q1 connection that drains.
Described input control signal is imported the first power tube Q1 grid, first triode Q1 source class output YG output signal.
Described Vcc_YG supply voltage value is than the high 15V of YG output signal voltage value, and Vsus feeder ear voltage range is 190V～210V, and Ve feeder ear voltage range is 1/2 of Vsus feeder ear magnitude of voltage.
Described Vsus feeder ear voltage range is 200V.
First power tube, second power tube are N raceway groove insulated gate bipolar transistor.
From the architectural feature of the invention described above as can be seen, its advantage is
By adopting this circuit mode, increase by the second power tube Q2 on the prior art basis and control other device that the second power tube Q2 works, can reduce the loss power of circuit itself, particularly for slim color plasma display, can effectively reduce device temperature, improve device reliability.
Description of drawings
The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 a is that the Y driving circuit is set up potential circuit analysis analysis synoptic diagram in the prior art;
Fig. 1 b is that the Y driving circuit is set up potential circuit power consumption synoptic diagram in the prior art;
Fig. 2 is the design's circuit diagram;
Fig. 3 is the design's circuit voltage rising synoptic diagram;
Fig. 4 a is the design's circuit analysis synoptic diagram;
Fig. 4 b the design power consumption synoptic diagram.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
Circuit diagram the present invention includes the first power tube Q1, the first diode D1, Ve feeder ear as shown in Figure 2, and described Ve feeder ear is connected with first power tube Q1 drain electrode by the first diode D1, and the control input signal is input to the first power tube Q1 grid; Also comprise the second power tube Q2, the second diode D2, the 3rd power tube D3, first resistance R 1, second resistance R 2, the Vsus feeder ear, the Vcc_YG feeder ear, described Vcc_YG feeder ear is by the 3rd diode D3, second resistance R 2 is connected with the second power tube Q2 grid, second power tube Q2 drain electrode is connected with the Vsus feeder ear, the second diode D2 anode is connected with the second power tube Q2 source class, first resistance R, 1 two ends respectively with the second power tube Q2 grid, the second power tube Q2 source class connects, the second diode D2 negative electrode and the first diode D1, the first power tube Q1 connection that drains.Wherein input control signal is imported the first power tube Q1 grid, first triode Q1 source class output YG output signal.
As shown in Figure 3, in order to reduce the loss of setting up potential circuit in the prior art, use the power supply of two stage manner be will keep voltage Vsus by circuit of the present invention and be converted to the Y driving circuit and set up voltage Vsetup, in conjunction with shown in Figure 2, the course of work of the present invention as can be known:
Phase one is powered (phase one of not powered separately by the Ve feeder ear in the prior art) by first diode by Ve feeder ear (voltage Ve is provided), import the first power tube Q1 grid by the control input signal, make win power tube source class and first power tube drain electrode conducting, make that setting up potential circuit YG output signal voltage value rises to voltage Ve gradually, and this moment, the second diode D2 cathode voltage value was Ve, the second diode D2 anode voltage is that Vcc_YG feeder ear (it is Vcc_YG that magnitude of voltage is provided) is by first resistance R 1, second resistance R 2 provides magnitude of voltage, this moment, the YG output voltage values rose to magnitude of voltage Ve gradually, but also do not arrive magnitude of voltage Ve, the second diode D2 cathode voltage value is Ve, this moment, the second diode D2 anode voltage added the VCC magnitude of voltage for the YG output voltage, do not reach before magnitude of voltage Ve deducts magnitude of voltage VCC at the YG output voltage, the second diode D2 anode is less than magnitude of voltage Ve, the second diode D2 is in cut-off state, the second diode D2 no current passes through, and the second power tube Q2 does not work.Wherein VCC is about fixed value 15V.
Subordinate phase is powered by Vsus, when YG output signal voltage value reaches magnitude of voltage Ve, be the grid power supply of the second diode Q2 through second resistance R, 2 dividing potential drops by the VCC_YG feeder ear, this moment, the second diode D2 anode voltage value was greater than the second diode D2 cathode voltage value Ve, the second diode D2 conducting, second power tube Q2 is controlled starts working, and makes to set up potential circuit YG output voltage and increase gradually and reach value Vsus.Magnitude of voltage VCC_YG=V wherein
YG+ VCC, V
YGBe the YG output voltage, VCC is generally about 15V, and wherein the loss power that produces of the first power tube Q1 is minimum, and main loss is at the second power tube Q2, the power consumption analysis circuit diagram shown in Fig. 4 a, the power consumption synoptic diagram shown in Fig. 4 b,
Pt2=P2+P3=I2*Ve*t2/2+I2*(Vsus-Ve)*(t3-t2)/2 （2）
Wherein shown in Fig. 4 a, Ve=△ V2, (Vsus-Ve)=△ V1,
Suppose Ve ≈ 1/2Vsus, bring formula (2) into, then Pt2 ≈ (I2*Vsus*t3)/4.
With Fig. 1 a with during Fig. 1 b compares, I1=I2 among Fig. 4 a, I2, I1 are respectively the electric current that flows through first power tube, second power tube, t1=t3 is the circuit working time of the present invention, then P1〉Pt2.
Disclosed all features in this instructions except mutually exclusive feature, all can make up by any way.
Disclosed arbitrary feature in this instructions (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
Claims (3)
1. potential circuit of setting up that is used for color plasma display Y driving circuit, comprise first power tube (Q1), first diode (D1), Ve feeder ear, described Ve feeder ear is connected with first power tube (Q1) drain electrode by first diode (D1), control input signal be input to first power tube (Q1) grid, it is characterized in that also comprising second power tube (
Q2), second diode (D2), the 3rd diode (D3), first resistance (R1), second resistance (R2), the Vsus feeder ear, the Vcc_YG feeder ear, described Vcc_YG feeder ear is by the 3rd diode (D3), second resistance (R2) is connected with second power tube (Q2) grid, second power tube (Q2) drain electrode is connected with the Vsus feeder ear, second diode (D2) anode is connected with second power tube (Q2) source electrode, first resistance (R1) two ends respectively with second power tube (Q2) grid, second power tube (Q2) source electrode connects, second diode (D2) negative electrode and first diode (D1) negative electrode, first power tube (Q1) drain electrode connects, first power tube (Q1) source electrode output YG output signal
,Described Vcc_YG supply voltage value is than the high 15V of YG output signal voltage value, and Vsus feeder ear voltage range is 190V～210V, and Ve feeder ear voltage range is 1/2 of Vsus feeder ear magnitude of voltage.
2. a kind of potential circuit of setting up for color plasma display Y driving circuit according to claim 1 is characterized in that described Vsus feeder ear voltage range is 200V.
3. a kind of potential circuit of setting up for color plasma display Y driving circuit according to claim 2 is characterized in that first power tube (Q1), second power tube (Q2) are N raceway groove insulated gate bipolar transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110409299 CN102426819B (en) | 2011-12-12 | 2011-12-12 | Establishment voltage circuit for Y-driving circuit of color plasma display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110409299 CN102426819B (en) | 2011-12-12 | 2011-12-12 | Establishment voltage circuit for Y-driving circuit of color plasma display panel |
Publications (2)
| Publication Number | Publication Date |
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| CN102426819A CN102426819A (en) | 2012-04-25 |
| CN102426819B true CN102426819B (en) | 2013-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201110409299 Expired - Fee Related CN102426819B (en) | 2011-12-12 | 2011-12-12 | Establishment voltage circuit for Y-driving circuit of color plasma display panel |
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Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001013912A (en) * | 1999-06-30 | 2001-01-19 | Fujitsu Ltd | Method and circuit for driving capacitive load |
| CN1161736C (en) * | 1999-08-30 | 2004-08-11 | 达碁科技股份有限公司 | Common driving circuit for scanning electrode in plasma display |
| JP4652936B2 (en) * | 2005-09-09 | 2011-03-16 | 日立プラズマディスプレイ株式会社 | Plasma display device and driving method thereof |
| KR100823512B1 (en) * | 2006-09-11 | 2008-04-21 | 삼성에스디아이 주식회사 | Plasma display device and its voltage generator |
| KR100870329B1 (en) * | 2007-08-08 | 2008-11-25 | 삼성에스디아이 주식회사 | Plasma display device and driving method thereof |
| KR20090050690A (en) * | 2007-11-16 | 2009-05-20 | 삼성에스디아이 주식회사 | Plasma Display and Driving Device |
| JP2009300565A (en) * | 2008-06-11 | 2009-12-24 | Panasonic Corp | Plasma display device |
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