CN102412152A - Method for manufacturing metal oxide semiconductor device with lightly doped drain structure - Google Patents

Abstract

The invention provides a method for manufacturing a Metal Oxide Semiconductor (MOS) element with a Lightly Doped Drain (LDD) structure, which comprises the following steps: providing a substrate of a first conductivity type; forming an insulating structure in the substrate to define an element region; forming a gate structure in the device region, wherein the gate structure comprises a dielectric layer, a stack layer and a spacer layer on the outer side wall of the gate structure; implanting impurities of a second conductive type into the substrate in the form of accelerated ions at an inclined angle with respect to the surface of the substrate to form a drain lightly doped structure, wherein part of the accelerated ions penetrate through the spacer layer and are implanted into the substrate to form a part of the drain lightly doped structure below the spacer layer; and implanting second conductive type impurities into the substrate in the form of accelerated ions to form a source and a drain.

Description

Method for manufacturing metal oxide semiconductor device with lightly doped drain structure

technical field

The invention relates to a method for manufacturing a metal oxide semiconductor element, in particular to a method for manufacturing a metal oxide semiconductor element with a lightly doped drain structure.

Background technique

1A-1E show the manufacturing method of MOS elements with LDD structure in the prior art. As shown in FIG. 1A, a substrate 11 is provided, such as a P-type silicon substrate, and an insulating structure 12 is formed in the substrate 11, such as regional oxidation. (local oxidation of silicon, LOCOS) structure to define the device area 100 . Next, please refer to FIG. 1B , in the device region 100 , the dielectric layer 13 a and the stacked layer 13 b in the gate structure are formed. Then, as shown in FIG. 1C, using ion implantation technology, impurities, such as but not limited to N-type impurities, are implanted into the substrate 11 in the form of accelerated ions, because the insulating structure 12 and the dielectric layer 13a in the gate structure The LDD structure 14 will be formed in the region where the ion is implanted with the shielding of the stacked layer 13 b and the photomask. Afterwards, a spacer layer 13C is formed on the peripheral sidewalls of the dielectric layer 13a and the stacked layer 13b. As shown in FIG. 1D, the material of the spacer layer 13C can be silicon oxide, silicon nitride, or a combination of the two, For the shielding of the spacer layer 13c, in the next process, as shown in FIG. 1E, impurities, such as N-type impurities, are implanted into the substrate 11 in the form of accelerated ions by ion implantation technology to form the source electrode. Unlike the drain electrode 15, impurities will not be doped into the substrate 11 below the spacer layer 13c. Wherein, the N-type impurity doping concentration of the source and drain 15 is on the order of 10 ¹⁵ -10 ¹⁶ /cm ² , while the N-type impurity doping concentration of the LDD structure 14 is about 10 ¹² -10 ¹³ /cm ² orders of magnitude.

The N-type impurity doping concentration gradient of the MOS device with LDD structure can be used to reduce the electric field intensity distribution of the drain of the MOS device in the device region 100 to overcome the hot carrier effect.

In the prior art mentioned above, two photomask processes are required to complete the LDD structure 14 and the source and drain electrodes 15. The manufacturing cost is relatively high, and in the middle of the two impurity doping processes, there are other process steps for forming the spacer layer 13c , such as deposition, etching, and thermal processing steps, which make it difficult to control the range of the thermal diffusion of the two doped impurities. U.S. Patent No. 5,966,604 proposes a method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure, which can integrate the steps of forming the LDD structure 14 and the source and drain 15 before forming the spacer layer 13c, but this On the one hand, the amount of thermal budget is reduced, and the invention uses impurities of the opposite conductivity type to adjust the concentration, which increases the complexity of the control of impurities in the device.

In addition, the impurity distribution gradients of the above two prior art have only two different depths, and as the device size shrinks, the depths of the LDD structure 14 and the source and drain 15 need to become shallower and shallower, and the required ion implantation The input energy is also getting lower and lower. For ion implantation technology, the implantation technology with lower and lower acceleration voltage is more difficult to achieve the accuracy required by the MOS device process.

In view of this, the present invention aims at the shortcomings of the above-mentioned prior art, and proposes a method for manufacturing a metal oxide semiconductor element with a lightly doped drain structure, which can not only save a photomask, but also improve the thermal budget of doping impurities; and through The impurity distribution gradient is eased, the hot carrier effect is further improved, and the accuracy problem of low-energy implantation in ion implantation technology can be solved.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose a method for manufacturing a metal oxide semiconductor element with a lightly doped drain structure, which can save a photomask, improve the thermal budget of doping impurities; and ease the impurity distribution Gradients can further improve the hot carrier effect, and can solve the problem of low-energy implantation accuracy in ion implantation technology.

To achieve the above object, the present invention provides a method for manufacturing a metal oxide semiconductor element with a lightly doped drain structure, comprising: providing a substrate of a first conductivity type; forming an insulating structure in the substrate to define an element region; forming a gate structure in the element region, the gate structure includes a dielectric layer, a stack layer, and a spacer layer on the outer sidewall of the gate structure; the second conductivity type impurity, in the form of accelerated ions, and The surface of the substrate is formed at an inclined angle, and the substrate is implanted to form a lightly doped drain structure, wherein part of the accelerated ions are implanted into the substrate through the spacer layer to form a part of the lightly doped drain structure located below the spacer layer and implanting impurities of the second conductivity type into the substrate in the form of accelerated ions to form source electrodes and drain electrodes.

In one implementation, the first conductivity type is P-type, and the second conductivity type is N-type. In another implementation mode, the first conductivity type is N type, and the second conductivity type is P type.

In one embodiment, the insulating structure may be a region oxide structure or a shallow trench isolation (STI) structure.

In one preferred implementation form, the inclination angle is between 30 degrees and 90 degrees.

The method for manufacturing the above-mentioned metal oxide semiconductor device with a lightly doped drain structure further includes: rotating the substrate on the horizontal plane by at least one rotation angle, and mixing impurities of the second conductivity type with the substrate in the form of accelerated ions The surface is formed at the inclination angle, and the substrate is implanted to form a lightly doped drain structure symmetrical to the gate structure, wherein part of the accelerated ions are implanted into the substrate through the spacer layer.

In a preferred embodiment of the method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure, the rotation angle is: 90 degrees, 180 degrees, or 270 degrees.

In one embodiment, the steps of forming the lightly doped drain structure and forming the source and drain share the same mask to define the doped region.

In one implementation mode, the steps of forming the lightly doped drain structure and forming the source and drain are performed in a full-scale implantation manner, using the gate structure and the insulating structure to define a doped region.

The following will be described in detail through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

1A-1E show the manufacturing method of the MOS element with LDD structure in the prior art;

2A-2E mark the cross-sectional view of the first embodiment of the present invention;

Figure 2F shows a cross-sectional view of a second embodiment of the present invention.

Explanation of symbols in the figure

11 Substrate

12 Insulation structure

12a STI insulation structure

13a Dielectric layer

13b stacked layers

13c Spacer layer

14 LDD structure

14a, 14b, 15a accelerated ions

15 Source and drain

Detailed ways

The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the upper and lower sequence relationship between each layer, as for the shape, thickness and width, they are not drawn to scale.

Please refer to the cross-sectional flowcharts of FIGS. 2A-2E , which show an embodiment of the present invention. This embodiment shows a method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure. As shown in FIG. 2A, a substrate 11 is firstly provided, such as but not limited to a P-type or N-type silicon substrate, and then an insulating structure 12 is formed in the substrate 11 to define an element region 100. As shown in this figure, the element region 100 Defined between the insulating structures 12 , the insulating structures 12 may be formed by area oxidation (LOCOS) or shallow trench isolation (STI) process technology. In this embodiment, the insulating structures 12 are, for example, LOCOS structures. Next, as shown in FIG. 2B , a part of the gate structure including the dielectric layer 13 a and the stacked layer 13 b is formed in the device region 100 . Next, different from the prior art, this embodiment does not form the LDD structure 14 or/and the source and drain 15 at this time, but forms the spacer layer 13c of the gate structure as shown in FIG. 2C . There are various methods for forming the gate structure and materials, which are well known to those skilled in the art. Since they are not the focus of this case, they will not be described in detail.

Next, as shown in FIG. 2D, by ion implantation technology, impurities, such as P-type or N-type impurities, are in the form of accelerated ions, as indicated by the dotted arrow 14a in this figure, and form an alignment with the surface of the substrate 11. The oblique angle is implanted into the substrate 11 to form a lightly doped drain structure 14 . It should be noted that: when the substrate 11 is N-type, P-type impurities are used; when the substrate 11 is P-type, N-type impurities are used. Due to the shielding of the insulating structure 12 , the dielectric layer 13 a and the stacked layer 13 b in the gate structure, or/and the mask, the ion-implanted region will form the LDD structure 14 . As for the inclined angle between the accelerated ions and the surface of the substrate 11 , a preferred embodiment is that the inclined angle is between 30 degrees and 90 degrees. In addition, part of the accelerated ions will hit the spacer layer 13c. Because of the influence of factors such as ion acceleration, type, inclination angle, thickness and material of the spacer layer 13c, different accelerated ions reach different depths after hitting the spacer layer 13c. In the substrate 11 below 13c, the distribution gradient of impurities is shown in the small figure in Figure 2D. It can be seen from the small figure that the closer to the dielectric layer 13a of the gate structure, that is, the inside of the MOS element channel, the deeper the impurity distribution is. Shallow, which is beneficial to improve the hot carrier effect. And, because accelerating ions needs to overcome spacer layer 13c, so ion implantation technology needs to accelerate ion with bigger accelerating voltage, like this, for the LDD structure 14 that needs to be distributed in relatively shallow depth, can improve ion implantation technology in When the acceleration voltage is small, the accuracy is not good.

After implanting from one direction, it is preferred to rotate the substrate 11 on the horizontal plane by at least one rotation angle, such as 90 degrees, 180 degrees, 270 degrees, or two or more of the above rotation angles, and Impurities, in the form of accelerated ions, as indicated by the dotted arrow 14b in this figure, are implanted into the substrate 11 at an inclination angle between 30 degrees and 90 degrees above the surface of the substrate 11 to form an LDD symmetrical to the gate structure. The structure, likewise, partially accelerates ions implanted into the substrate 11 through the spacer layer 13c, and can be distributed at a shallower depth.

Next, as shown in FIG. 2E, using ion implantation technology, impurities, such as P-type or N-type impurities, are implanted into the substrate 11 in the form of accelerated ions, as indicated by the dotted arrow 14a in this figure, to The source and drain 15 are formed, and impurities will not be doped into the substrate 11 below the spacer layer 13c. In this way, the distribution of impurities in the LDD structure 14 and the source and drain 15 will be close to the channel of the MOS element. The distribution of different impurity concentrations and depths is formed to improve the hot carrier effect. Among them, the steps of forming the LDD structure 14 and forming the source and drain 15 can share the same mask to define the doped region, or do not use the mask to define, but use the gate structure and the insulating structure in a comprehensive implantation method. 12 Define the doped region. Compared with the prior art, the present invention can save the mask cost, which is another advantage.

FIG. 2F marks the second embodiment of the present invention. This embodiment shows that the insulating structure 12 in the present invention can also be formed by STI process technology.

The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. First of all, the angle of rotation referred to in the present invention is, for example, "90 degrees, 180 degrees, or 270 degrees", which does not mean that it must be rotated exactly 90 degrees, 180 degrees, or 270 degrees absolutely without error, but should be regarded as allowable width deviation. For example, other process steps or structures, such as deep well regions, can be added without affecting the main characteristics of the device; as another example, the lithography technology is not limited to the photomask technology, and can also include the electron beam lithography technology. The scope of the present invention is intended to cover the above and all other equivalent variations.

Claims (9)

1. A method for manufacturing a metal oxide semiconductor element with a lightly doped drain structure, characterized in that it comprises: providing a substrate of a first conductivity type; forming an insulating structure in the substrate to define an element region; forming a gate structure in the element region, the gate structure including a dielectric layer, a stack layer, and a spacer layer on the outer sidewall of the gate structure; Implanting impurities of the second conductivity type into the substrate at an oblique angle to the surface of the substrate in the form of accelerated ions to form a lightly doped drain structure, wherein part of the accelerated ions are implanted into the substrate through the spacer layer to form the drain the portion of the very lightly doped structure underlying the spacer layer; and The impurity of the second conductivity type is implanted into the substrate in the form of accelerated ions to form the source and the drain. 2 . The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1 , wherein the first conductivity type is P-type, and the second conductivity type is N-type. 3 . 3 . The method of manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1 , wherein the first conductivity type is N type, and the second conductivity type is P type. 4 . 4 . The method of manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1 , wherein the insulating structure is a region oxide structure or a shallow trench isolation structure. 5 . The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1 , wherein the inclination angle is between 30 degrees and 90 degrees. 6. The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1, further comprising: rotating the substrate on the horizontal plane by at least one rotation angle, and turning the substrate having the second conductivity type Impurities, in the form of accelerated ions, are implanted into the substrate at the oblique angle to the substrate surface to form a lightly doped drain structure symmetrical to the gate structure, wherein part of the accelerated ions are implanted into the substrate through the spacer layer. 7 . The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 6 , wherein the rotation angle is: 90 degrees, 180 degrees, or 270 degrees. 8. The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1, wherein the steps of forming the lightly doped drain structure and forming the source and drain share the same mask Define doped regions. 9. The method for manufacturing a metal oxide semiconductor device with a lightly doped drain structure as claimed in claim 1, wherein the steps of forming the lightly doped drain structure and forming the source and drain are comprehensive In an implantation method, the gate structure and the insulating structure are used to define a doped region.

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