CN102404000A

CN102404000A - High-performance small-area narrow-band phase locked loop

Info

Publication number: CN102404000A
Application number: CN201010283111XA
Authority: CN
Inventors: 孙茂友
Original assignee: Individual
Current assignee: Individual
Priority date: 2010-09-14
Filing date: 2010-09-14
Publication date: 2012-04-04

Abstract

A high-performance small-area narrow-band phase locked loop (see chart 2) is formed by a phase discriminator, a charge pump, a low pass filter, a voltage-controlled oscillator and a divider. The phase discriminator enables the charge pump to respectively send or absorb two current pulses I1 and I2 to the low pass filter by comparing data in voice (DIV)-clock (CLK) phase position of feedback oscillating signals with reference (REF)-clock (CLK) phase position of a parameter clock. Sum of two-way voltages are equivalent to output voltage VCNTL of an original phase locked loop filter, the two-way voltages are used for controlling the voltage-controlled oscillator (VCO), and the VCO outputs a signal and sends a feedback signal DIV-CLK through the divider to the phase discriminator so as to determine the oscillating speed of the voltage-controlled oscillator VCO. If the current pulse I2 is 10 times less than the current pulse I1, the capacitor C1A can be decreased by 10 times as well, and capacitor C1A integrated on a chip only occupies one tenth of the area of an original capacitor.

Description

A kind of high-performance small size narrow band phase lock loop

Technical field

The present invention relates to be used in a kind of integrated circuit the narrow band phase lock loop of FREQUENCY CONTROL, refer specifically to a kind of can be integrated into a chip have a high-performance small size narrow band phase lock loop.

Background technology

Like figure (1), the existing phase-locked loop that is used for integrated circuit medium frequency control is the phase place of the oscillator signal Div_Clk that relatively feeds back to through phase discriminator and the phase place of parameter clock Ref_Clk; Export a comparative result UP, DN signal; According to UP, DN signal, charge pump is seen off or is absorbed a current impulse I1 to low pass filter, and this electric current is given the electric capacity charge or discharge of filter; The output voltage V CNTL of filter is used to control voltage-controlled oscillator (VCO) VCO; VCO output signal send feedback signal Div_Clk to be used for the position to phase discriminator through divider and compares, confirm the concussion speed of voltage-controlled oscillator (VCO) VCO, thereby further adjust.For the low pass filter in the above phase-locked loop, its capacitor C 1 is bigger, for the narrow band phase lock loop filter; Because of its bandwidth narrow; Used capacitor C 1 is more than 100PF, and because of electric capacity occupies very large chip area, the narrow band phase lock loop low pass filter is difficult to be integrated on the chip.

Summary of the invention

The present invention proposes following technical solution in order to solve the problem that exists in the above technology.

Like figure (2); The present invention is made up of phase discriminator, charge pump, low pass filter, voltage controlled oscillator and divider; Be oscillator signal DIV, the phase place of CLK and the phase place of parameter clock REF-CLK that relatively feeds back to through phase discriminator, comparative result exported with UP, DN signal, according to UP, DN signal; Charge pump is seen off respectively or is absorbed two current impulse I1 and I2 to low pass filter, wherein flow through R1 and C2 of one tunnel current impulse I1; Another road current impulse I2 is through C1; The output voltage V CNTL that is equivalent to original phase locked loop filter after the addition of two-way voltage is used to control voltage-controlled oscillator (VCO) VCO; VCO output signal send feedback signal DIV-CLK to be used for the position to phase discriminator through divider and compares, confirm the concussion speed of voltage-controlled oscillator (VCO) VCO.If current impulse I2 reduces 10 times than I1; Be I2=I1/10; Capacitor C 1A can reduce 10 times equally so, i.e. C1A=C1/10, and the voltage of the output voltage of C1A and original C1 is the same and capacitance C1A has reduced 10 times like this; If capacitor C 1A is integrated into the area that will only take original electric capacity 1/10 on the chip like this, effectively reduced chip area.

Adopt said method will obtain big ratio and dwindle capacity area, I2 is very little for charge pump current, and electric current I 2 is difficult to control so on the one hand, is keeping loop noise variation under the identical loop bandwidth condition on the other hand, and the present invention can improve like figure (3) for this reason.Charge pump is exported two essentially identical electric current I 1 and I2=9/10 * I1 like this; And capacitor C 1A can reduce 10 times equally; Low pass filter also can be exported the voltage-controlled voltage VCNTL of identical VCO; Effectively like this reduce the low-pass filter capacitance area and phase demodulation ring PLL loop output noise characteristic is unaffected, made the low frequency narrow band phase lock loop can be integrated into fully on the chip.

In addition, when the loop operate as normal, VCO control voltage VCNTL can change in 0 to VDDA scope, and when one of charge pump current I2 and I1 were output, another was to absorb, and current value changes with Vcntl.Adopt figure of the present invention (3) method; The ratio of charge pump current I2 and I1 becomes big with the variation of VCO control voltage VCNTL or diminishes; For the ratio of holding current I2 and I1 does not change with the variation of VCO control voltage VCNTL, the present invention can improve shown in figure (4), through using active filter; It is constant that charge pump output voltage can remain on charge pump supply power voltage half the (VDDA/2), and VCO control voltage VCNTL changes and no longer influences I2 and I1.

Shown in figure (5), when UP be high electricity frequently, DN is a low electricity frequently the time, charge pump output charging current I1 and input discharging current I2, the charge pump output end voltage is controlled near the VDDA/2.Shown in figure (6), when UP be low electricity frequently, DN is a high electricity frequently the time, charge pump output charging current I2 and input discharging current I1, the charge pump output end voltage is controlled near the VDDA/2.

Description of drawings

Below in conjunction with accompanying drawing the present invention is further described.

Figure (1) is existing phase-locked loop circuit sketch map.

Figure (2) is to replace the low pass filter sketch map by the two-way equivalence filter.

Figure (3) replaces the low-pass filter circuit sketch map with equivalence filter.

Figure (4) is that the present invention adopts the active low-pass filter circuit diagram.

Circuit diagram when figure (5) is the high UP of the present invention, low DN.

Circuit diagram when figure (6) is the low UP of the present invention, high DN.

Embodiment

The present invention is finally as shown in Figure 4; Constitute by phase discriminator 1, charge pump 2, low pass filter 3, voltage controlled oscillator 4 and divider 5; The phase place of the phase place of the oscillator signal Div_Clk that phase discriminator relatively feeds back to and parameter clock Ref_Clk is exported comparative result, according to UP, DN signal with UP, DN signal; Charge pump is seen off respectively and is absorbed two current impulse I1 and I2 to low pass filter; Flow through R1 and C2 of current impulse I1 wherein, current impulse poor (I1-I2) C1 that flows through, and discharge and recharge to C1.When UP is a high level, when DN is low level, charge pump output charging current I1 and input discharging current I2, the charge pump output end voltage is controlled near the VDDA/2; When UP is a low level, when DN is high level, charge pump output charging current I2 and input discharging current I1; The charge pump output end voltage is controlled near the VDDA/2, like this, no matter UP and DN are high level or low level; The charge pump output end voltage is controlled near the VDDA/2; With VCO control change in voltage, charge pump current ratio I1/ (I1-I2) can not be set in very big numerical value and not become flower with Vcntl for charge pump current I1 and I2 size, and filter capacitor C1 can be reduced to very fractional value.Therefore, low pass filter is integrated into and takies very small size on the chip, makes that the high-performance narrow band phase lock loop can be fully integrated to a chip.

Claims

1. high-performance small size narrow band phase lock loop; By forming by phase discriminator, charge pump, low pass filter, voltage controlled oscillator and divider; It is characterized in that current impulse I2 reduces 10 times than I1; Capacitor C 1A can reduce 10 times equally so, will only take the area of original electric capacity 1/10 to being integrated into capacitor C 1A on the chip.

2. by the described high-performance small size of claim 1 narrow band phase lock loop; It is characterized in that like figure (3), two essentially identical electric current I 1 of charge pump output and I2=9/10 * I1, and capacitor C 1A can reduce 10 times equally; Low pass filter also can be exported the voltage-controlled voltage VCNTL of identical VCO; Reduced the low-pass filter capacitance area effectively, and phase demodulation ring PLL loop output noise characteristic is unaffected, makes the low frequency narrow band phase lock loop can be integrated into fully on the chip.

3. by the described high-performance small size of claim 1 narrow band phase lock loop; It is characterized in that like figure (4); It is constant that charge pump output voltage can be remained on charge pump supply power voltage half the (VDDA/2), and the ratio of electric current I 2 and I1 is not changed with the variation of VCO control voltage VCNTL

4. by the described high-performance small size of claim 1 narrow band phase lock loop, it is characterized in that shown in figure (5), when UP be high electricity frequently, DN is a low electricity frequently the time, charge pump output charging current I1 and input discharging current I2, the charge pump output end voltage is controlled near the VDDA/2; Shown in figure (6), when UP be low electricity frequently, DN is a high electricity frequently the time, charge pump output charging current I2 and input discharging current I1, the charge pump output end voltage is controlled near the VDDA/2.