CN102368689B - Multi-point data transmission system based on wireless spread spectrum communication - Google Patents

Abstract

The invention discloses a multi-point data transmission system based on wireless spread spectrum communication. Both the transmitting end and the receiving end adopt modular software and hardware design, and the main signal processing work of the system is implemented in a programmable logic device, which simplifies The hardware structure reduces system power consumption and size. At the same time, the receiving end adopts digital intermediate frequency receiving technology to sample the signal at the intermediate frequency. The instantaneous processing signal bandwidth of digital intermediate frequency receiving technology is greatly increased, the dynamic range is larger, the scalability is better, and the flexibility is higher. The analog link makes the noise introduced by the front end less, the signal distortion is smaller, and the circuit is more concise. The receiving end adopts the method of parallel processing to receive data, and the software processing process is modularized. For different transmitting ends, only a few parameters need to be modified to achieve accurate reception. At the same time, the system expansion method is simple. When the number of sending ends increases, the corresponding software modules of the receiving end can be added.

Description

Multipoint Data Transmission System Based on Wireless Spread Spectrum Communication

technical field

The present invention relates to a multi-point data transmission system based on wireless spread spectrum communication. The system mainly adopts direct sequence spread spectrum communication technology, which is used for simultaneous confidential data transmission between multiple transmitters and receivers. The system is easy to expand and configure flexible.

Background technique

The existing spread spectrum data transmission system generally has defects such as complex hardware structure and low data transmission speed. In addition, the receiving end of the traditional data transmission system generally adopts time-division communication when receiving data from multiple transmitting ends, and cannot receive data from multiple transmitting ends at the same time. data, which greatly reduces the data transmission efficiency of the system.

The invention provides a spread spectrum data transmission system capable of multi-point high-speed data transmission at the same time, with strong anti-interference ability and good confidentiality.

Contents of the invention

The purpose of the present invention is to provide a system capable of simultaneous multi-point high-speed data transmission by using wireless spread spectrum communication technology. The data transmission rate of the system is 20-80kbps, the bandwidth of the spread spectrum signal is 5MHz, the frequency point of the intermediate frequency is 70MHz, and the frequency of radio frequency communication is 400MHz. The length of the spreading code is 31 bits to 127 bits. At the same time, the system adopts the multi-user detection technology in the baseband digital signal processing to remove the multiple access interference of the system.

The present invention is realized by adopting the following technical means:

The present invention is characterized in that it contains: at least one user's transmitting end, and a receiving end for receiving a transmitted signal, wherein:

The sending end of each user contains: the first programmable logic device, the direct digital frequency synthesizer DDS, the first local oscillator, the analog up-conversion circuit, the first band-pass filter, the first low-noise amplifier, and the second band-pass filter, power supply, and transmit antenna, where:

The first programmable logic device is provided with: a user data input interface, a software configuration interface, a power supply module (71), the direct digital frequency synthesizer DDS (hereinafter referred to as DDS) and the initialization module of the first local oscillator, in:

The user data input interface is used to input source data;

The software configuration interface is used to download the configuration file of the application program and store it in the flash memory;

In the first programmable logic device, there is also: a data processing module, including: a differential encoding and a direct-sequence spread spectrum module whose input is a PN1 code, wherein: the input terminal of the differential encoding module is connected to the user data The input interface is connected, and the direct-sequence spread spectrum module adopts direct sequence spread spectrum to the differential coded data input from the differential code module and sends it to the DDS for direct spread spectrum, using 31-bit spread spectrum code sequence and 127-bit GOLD code Spreading sequence, the data processing module inputs the output information of the above two initialization modules.

DDS generates a local carrier signal under the control of a programmable logic device to perform binary phase-shift BPSK modulation on the spread-spectrum source data, and then sends the modulated source data to the analog up-conversion circuit;

An analog up-conversion circuit, which inputs a local oscillator signal from the first local oscillator, up-converts the input modulated source data to a radio frequency of 400 MHz, and passes through the first band-pass filter, the first low-noise amplifier, and the second After the band-pass filter is sent out through the transmitting antenna;

The receiving end is a source data receiving end shared by multiple users, which is equipped with: a front-end analog processing part, a data buffer and a second programmable logic device;

The front-end analog processing part includes: an analog down-conversion processing circuit for radio frequency signals, a controllable gain amplifier, an analog/digital converter, and a clock distributor, wherein:

The analog down-conversion circuit of the radio frequency signal is composed of a receiving antenna, a third band-pass filter, a second low-noise amplifier, an analog down-conversion circuit whose input terminal is connected to the output terminal of the second local oscillator, and a fourth band-pass filter in sequence It is connected in series, and the receiving antenna sends the received radio frequency signals of each user to the second low-noise amplifier for analog amplification processing through the third band-pass filter for front-end filtering processing, and then passes the analog down-conversion circuit. The frequency conversion of the radio frequency signal to a 70MHz intermediate frequency analog signal is sent to the controllable gain amplifier after passing through the fourth bandpass filter, and the controllable gain amplification is performed before sampling;

A controllable gain amplifier, amplifying the amplitude of the filtered 70MHz intermediate frequency analog signal to the range [-1,1] under the control of the second programmable logic device, and then sending it to the analog/digital converter for further processing sampling;

An analog/digital converter, sampling the intermediate frequency analog signal at the 80MHz sampling rate given by the second programmable logic device according to the clock distribution signal set by the second programmable logic device for the clock distributor , after a down-conversion process, the intermediate frequency digital signal of 10MHz is obtained as a sampling output, and sent to the data buffer cache;

The second programmable logic device is provided with: a plurality of user data output interfaces (1211-121n) equal to the number of users, n is the total number of users, a software configuration interface, a power supply module (72), and an initialization module, the initialization output: A digital/analog conversion signal (18), a clock distribution signal (19), a local oscillator signal (17) and a controllable gain amplifier initialization signal (20), the second programmable logic unit (12) supplies the controllable gain The amplifier (101) outputs the control word of the amplification factor and the low power consumption mode control signal, and the second programmable logic unit (12) inputs the 10MHz intermediate frequency digital signal output by the data buffer (9) and also inputs the 10MHz intermediate frequency digital signal output by the first The 70MHz intermediate frequency analog signal output by the four-bandpass filter (54), the second programmable logic device (12) is also provided with:

A data processing module, which consists of a 10MHz digital signal down-conversion module and each code synchronous despreading module, carrier frequency synchronous demodulation module and differential decoding module respectively connected in series to each source data output circuit, outputting each user data , the input of the intermediate frequency digital signal down-conversion module is a 10MHz intermediate frequency digital signal output is a 2.5MHz baseband signal, which is sent to each user for each baseband signal processing and user sorting through several output terminals; a data output circuit, and an automatic The gain control module includes: a signal level detection module, a comparator and a loop filter connected in series in sequence, and an expected value output module whose output terminal is connected to the input terminal of the comparator, wherein:

Signal level detection module, the input is the 70MHz intermediate frequency digital signal, and the output is the amplitude of the intermediate frequency digital signal on the continuous set number of sampling points;

Comparator, one input is the minimum value of the preset intermediate frequency digital signal amplitude output by the expected value output module, when the amplitude of the intermediate frequency digital signal at the set number of continuous sampling points is less than the When the expected value is expected, an identification signal "1" is generated corresponding to the set maximum amplification factor, which is filtered by the loop filter and then sent to the control word output interface to control the amplification factor of the controllable gain amplifier. If it is greater than The expected value generates an identification signal "0", which corresponds to other set amplification factors, and is sent to the control word output terminal for controllable gain amplification after passing through the loop filter.

Compared with the prior art, a multi-point data transmission system based on wireless spread spectrum communication of the present invention has the following obvious advantages and beneficial effects:

Both the transmitting end and the receiving end adopt modular software and hardware design, and the main signal processing work of the system is implemented in the programmable logic device, which simplifies the hardware structure and reduces the power consumption and volume of the system. At the same time, the receiving end adopts digital intermediate frequency receiving technology to sample the signal at the intermediate frequency. The instantaneous processing signal bandwidth of digital intermediate frequency receiving technology is greatly increased, the dynamic range is larger, the scalability is better, and the flexibility is higher. The analog link makes the noise introduced by the front end less, the signal distortion is smaller, and the circuit is more concise.

The receiving end adopts the method of parallel processing to receive data, and the software processing process is modularized. For different transmitting ends, only a few parameters need to be modified to achieve accurate reception. At the same time, the system expansion method is simple. When the number of sending ends increases, the corresponding software modules of the receiving end can be added.

Description of drawings

Fig. 1 is a system basic block diagram of the present invention;

Fig. 2 (a) is the hardware block diagram of the transmitting end of the present invention;

Figure 2(b) is a block diagram of the internal functional modules of the programmable logic device at the sending end;

Fig. 3 (a) is the hardware block diagram of the receiving end of the present invention;

Figure 3(b) is a block diagram of the internal functional modules of the programmable logic device at the receiving end;

Fig. 4 is the structural diagram of automatic gain control;

Fig. 5 is a schematic diagram of the system structure of the present invention.

in:

10 analog down-conversion circuit; 11 first programmable logic device; 12 second programmable logic device; 101 controllable gain amplifier; 102 analog/digital converter; 103 clock distributor; 111 user data input interface; 112 software configuration interface ; 1211-121n multiple user data output interfaces; 122 software configuration interface; 2 direct digital frequency synthesizer DDS; 31 first local oscillator; 32 second local oscillator; 4 analog up-conversion circuit; 51 first band-pass filter; 52 the second band-pass filter; 53 the third band-pass filter; 54 the fourth band-pass filter; 61 the first low-noise amplifier; 62 the second low-noise amplifier; 71 the first power supply module; 72 the second power supply module; ; 81 transmit antenna; 82 receive antenna; 9 data buffer.

Detailed ways

Embodiments of the present invention will be further described below in conjunction with the accompanying drawings:

The basic block diagram of the system of the present invention is shown in Fig. 1, and the system can realize one-to-one and many-to-one spread spectrum wireless data transmission macroscopically. User data is transmitted wirelessly after direct sequence spread spectrum and BPSK (Binary Phase Shift Keying, Binary Phase Shift Keying) modulation at the sending end, and then recovered after down-converting, synchronous despreading and synchronous demodulation at the receiving end Raw data. When the system is one-to-one data transmission, a 31-bit spreading code can be used, and the system transmission speed is 80kbps; when the system is many-to-one transmission, a 127-bit spreading code is used, and the system transmission speed is 20kbps .

Fig. 2 a shows the hardware block diagram of the sending end of the present invention, the sending end software program is downloaded into the flash memory by the software configuration interface 112, after the sending end is powered on and starts working, the programmable logic device 11 loads the program and the configuration file from the flash memory start working. The task of the programmable logic device 11 at the sending end is to perform source coding and spread spectrum coding on the user data; configure the direct digital frequency synthesizer 2 through the control line, and configure the local oscillator in the analog up-conversion circuit 4 . The internal functional logic of the programmable logic device 11 is shown in FIG. 2b. The spread spectrum coding part adopts direct sequence spread spectrum, the 31-bit spread spectrum code is the m sequence, and the 127-bit spread spectrum sequence is the GOLD code sequence (a code sequence invented by Robert S. Gold). The digital signal after frequency spreading is converted into an analog signal through the direct digital frequency synthesizer 2, then sent to the analog up-conversion circuit 4 for up-conversion to a radio frequency of 400MHz, and then the signal is processed through the first band-pass filter 51 For filtering processing, the first low-noise amplifier 61 amplifies the power of the radio frequency signal accordingly, and finally sends it out through the antenna 81 .

Fig. 3 a is the hardware block diagram of the receiving end of the present invention, similar to the design of the sending end, the software program of the receiving end is also downloaded into the flash memory by the software configuration interface, and the programmable logic device 12 starts loading the program and the configuration file from the flash memory after power-on Work. The task of the programmable logic device 12 at the receiving end is to carry out digital down-conversion, code synchronous despreading, carrier synchronous demodulation, and differential decoding to the intermediate frequency digital signal output by the analog-to-digital converter 102; and the analog-to-digital converter 102, The clock distributor 103, the local oscillator in the analog down-conversion circuit 10, and the controllable gain amplifier 101 perform corresponding initialization and control operations. Regardless of whether the system adopts a one-to-one or many-to-one structure, the front-end analog processing part does the same processing, that is, the antenna 82 sends the received radio frequency signal to the second low-noise amplifier after being processed by the third band-pass filter 53 for front-end filtering 62 for analog amplification processing, and then the analog down-conversion circuit 10 performs analog down-conversion to convert the radio frequency signal to 70MHz, and then sends it to the controllable gain amplifier 101 through the fourth band-pass filter 54 for controllable gain amplification before sampling, and the The amplitude of the IF analog signal is amplified to the range [-1,1]. The controllably amplified intermediate frequency analog signal is sent to the analog-to-digital converter 102 for sampling. Here, the bandwidth sampling technology is introduced to sample the intermediate frequency analog signal at a sampling rate of 80MHz and perform a down-conversion process to obtain a 10MHz digital signal as a sampling output, and The digital signal is sent to the programmable logic device 12 via the data buffer 9 . The internal functional logic of the programmable logic device 12 is shown in FIG. 3b. The digital down-conversion module receives the sampled digital signal at 10MHz, and converts it to 2.5MHz through digital down-conversion. Operations such as digital filtering, code synchronous despreading, carrier synchronous demodulation, and differential decoding after digital down-conversion are all performed on this 2.5MHz baseband digital signal.

FIG. 4 is a structural diagram of the automatic gain control. The purpose of this part is to controllably amplify the amplitude of the analog intermediate frequency signal to the amplitude range [-1, 1] specified by the analog-to-digital converter 102 . The programmable logic unit 12 performs corresponding control operations on the controllable gain amplifier 101 through the control lines, wherein the control lines include 1 power mode control line and 5 gain control lines. When the power consumption mode control line is below 0.8V, the controllable gain amplifier 101 works in the low power consumption mode. The five gain control lines are used to transmit the control word signal generated by the programmable logic device 12, corresponding to 25 amplification factors in total. The process of control word generation considers that the signal may be too small or interrupted in the actual situation. At this time, no matter how amplified, it cannot fall within the expected value range, which will cause the overflow of the loop filter and fail to achieve the effect of automatic gain control. Therefore, an identification module is added to the program design. When multiple consecutive signal amplitudes are lower than the set minimum value, the identification signal sign will be set to '1', and the magnification factor will be set to the maximum; if the signal amplitude during the period is greater than this threshold, Then set the identification signal sign to '0', and perform controllable amplification.

Fig. 5 shows the principle diagram of the system structure of the present invention, where n sending ends are used to send at the same time, and the receiving ends receive in parallel. Each user transmits its own transmission data to the programmable logic device 11 through the user data interface 121, where the differential coding and direct sequence spread spectrum of the user data are completed. In the spreading process, the allocated spreading codes are respectively selected. Here, 31-bit m-sequence or 127-bit GOLD code sequence can be selected for the number of users and transmission speed. The spread spectrum signal is BPSK modulated under the control of the programmable logic device 11 to obtain an intermediate frequency analog signal. The intermediate frequency analog signal is sent out through the antenna 81 after analog up-conversion, filtering, and power amplification operations. The analog part of the receiving end completes power amplification, analog down-conversion and filtering, and controllable gain amplification processing, and then sends it to the analog-to-digital converter 102 for sampling. After sampling, a 10MHz digital signal is obtained, and the digital signal is sent to the programmable logic device 12 Perform digital down-conversion processing to obtain a 2.5MHz baseband digital signal. The baseband digital signal uses different user spreading codes for code synchronous despreading, and at the same time removes mutual interference, then performs carrier synchronous demodulation, and finally performs differential decoding to obtain user data. The above-mentioned processes are processed in parallel and performed synchronously, so as to realize simultaneous reception of multi-channel user data.

Claims (1)

1. the Multi-point data transmission system based on radio spread spectrum communication, is characterized in that, contains: at least one user's transmitting terminal, and a receiving terminal that at least receives a transmitted signal, wherein:

Each user's transmitting terminal, contain: the first programmable logic device (11), Direct Digital Frequency Synthesizers DDS (2), the first local oscillator (31), simulation up-converter circuit (4), the first band pass filter (51), the first low noise amplifier (61), the second band pass filter (52), power supply (7) and transmitting antenna (81), wherein:

The first programmable logic device (11), be provided with: user data input interface (111), software configuration interface (112), supply module (71), described Direct Digital Frequency Synthesizers DDS's (2) and described the first local oscillator (31) initialization module, wherein:

Described user data input interface, for inputting information source data;

Described software configuration interface (112), for the configuration file of down load application program, and deposits in flash memory;

In described the first programmable logic device (11), be also provided with: data processing module, comprise: differential coding module and be input as the direct sequence spread spectrum module of PN1 code, wherein: the input of described differential coding module is connected with described user data input interface (111), described direct sequence spread spectrum module to from the differential coding data acquisition of described differential coding module input with being sent to described DDS (2) Direct-Spread direct sequence spread spectrum, adopt 31 spread spectrum code sequences and 127 GOLD spread spectrum code sequences, described data processing module is inputted the initialization information of differential coding module as above and direct sequence spread spectrum module,

DDS (2), control the lower information source data of local carrier signal after to spread spectrum that produce at programmable logic device (11) and carry out two-phase phase shift BPSK modulation, then the information source data after modulating are sent into described simulation up-converter circuit (4);

Simulation up-converter circuit (4), from described the first local oscillator (31) input local oscillation signal, information source data after the modulation of input are upconverted to rf frequency 400MHz, send by transmitting antenna (81) through the first band pass filter (51), the first low noise amplifier (61), the second band pass filter (52) successively;

Receiving terminal, is a multi-user shared information source data receiver, is provided with: front end simulation process part, a data buffer (9) and second programmable logic device (12);

Described front end simulation process part, contains: the analog down treatment circuit of radiofrequency signal, controllable gain amplifier (101), A/D converter (102), and clock distributor (103), wherein:

The analog down treatment circuit of radiofrequency signal, by a reception antenna (82), the 3rd band pass filter (53), the second low noise amplifier (62), the analog down circuit (10) that input is connected with the second local oscillator (32) output, and four-tape bandpass filter (54) is connected in series and forms successively, reception antenna (82) is given the each user's radiofrequency signal sequentially receiving the second low noise amplifier (62) and is done simulation amplification processing after the 3rd band pass filter (53) carries out front-end filtering processing, by analog down treatment circuit (10), described radiofrequency signal is converted to 70MHz analog intermediate frequency signal again, after four-tape bandpass filter (54), deliver to described controllable gain amplifier (101), controllable gain before sampling amplifies,

Controllable gain amplifier (101), the amplitude of filtered described 70MHz analog intermediate frequency signal under controlling, described the second programmable logic device (12) is amplified to scope [1,1] between, then deliver to described A/D converter (102) and sample;

A/D converter (102), the clock distribution signal of setting for described clock distributor (103) by described the second programmable logic device (12) is sampled to described analog intermediate frequency signal with the given 80MHz sample rate of described the second programmable logic device (12), as sampling output, deliver to described data buffer (9) buffer memory at the digital intermediate frequency signal that obtains 10MHz after a down-converted;

The second programmable logic device (12), be provided with: the multiple user data output interfaces (1211-121n) that equate with number of users, n is total number of users, software configuration interface (122), supply module (72), initialization module, described initialization output: D/A switch signal (18), clock distribution signal (19), local oscillation signal (17) and controllable gain amplifier initializing signal (20), described the second programmable logic device (12) is to control word and the low-power consumption mode control signal of described controllable gain amplifier (101) output multiplication factor, described the second programmable logic device (12) is inputted by the 10MHz digital intermediate frequency signal of described data buffer (9) output and is also inputted the 70MHz analog intermediate frequency signal by four-tape bandpass filter (54) output, in described the second programmable logic device (12), be also provided with:

A data processing module, by a 10MHz digital signal down variable frequency module and the synchronous despreading module of each code, carrier frequency synchronization demodulation module and differential decoding module are connected in series respectively and form Ge road information source data output circuit composition, export each user data, described digital intermediate frequency signal down conversion module input is that the output of 10MHz digital intermediate frequency signal is 2.5MHz baseband signal, be sent to each base band signal process and the user data output circuit of each user's apportion by several outputs, secondly also has an automatic gain control module, contain: the signal level detection module of series connection successively, comparator and loop filter, the desired value output module that also has output to be connected with described comparator input terminal, wherein:

Signal level detection module, input is described 70MHz digital intermediate frequency signal, output is the amplitude of the digital intermediate frequency signal on continuous setting quantity sampled point;

Comparator, input is the minimum value by the described digital intermediate frequency signal amplitude of the prior setting of described desired value output module output, in the time that the amplitude of the digital intermediate frequency signal on continuous described setting quantity sampled point is less than described desired value, produce id signal " 1 ", corresponding to the maximum amplification of setting, after described loop filter filtering, be sent to described control word output interface, control the multiplication factor of described controllable gain amplifier (101), if be greater than described desired value, produce id signal " 0 ", corresponding to other multiplication factors of setting, after described loop filter, be sent to described control word output and carry out controllable gain amplification.