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CN102358613A - Manufacturing method of micro-electromechanical systems (MEMS) arch structure - Google Patents

Manufacturing method of micro-electromechanical systems (MEMS) arch structure Download PDF

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Publication number
CN102358613A
CN102358613A CN2011103086458A CN201110308645A CN102358613A CN 102358613 A CN102358613 A CN 102358613A CN 2011103086458 A CN2011103086458 A CN 2011103086458A CN 201110308645 A CN201110308645 A CN 201110308645A CN 102358613 A CN102358613 A CN 102358613A
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China
Prior art keywords
mems
sio
domes
silicon chip
groove
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CN2011103086458A
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Chinese (zh)
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陈俊
杨增涛
吴建
黄磊
徐俊
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CETC 24 Research Institute
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CETC 24 Research Institute
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Priority to CN2011103086458A priority Critical patent/CN102358613A/en
Publication of CN102358613A publication Critical patent/CN102358613A/en
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Abstract

The invention discloses a manufacturing method of a micro-electromechanical systems (MEMS) arch structure. The novel MEMS arch structure is manufactured by adopting sacrifice layer technology and selective chemical mechanical polishing and coating technology. The manufactured arch structure by means of the manufacturing method can achieve micron-sized structures, the process is simple, and manufacturing efficiency is high. By adopting a low-temperature process, influence of a high temperature annealing process to device performance is avoided. Internal stress of the arch structure is small so that large pre-stressing force existing inside the arch structure is avoided. The step position of a sacrifice layer is smooth, thereby resolving the problem that the arch structure easily breaks. The manufacturing method of the MEMS arch structure is widely applied to the manufacturing field of MEMS devices.

Description

A kind of manufacturing approach of MEMS domes
Technical field
The present invention relates to a kind of manufacturing approach of MEMS domes, its direct application is the manufacturing field of MEMS (MEMS) device.
Background technology
Domes in the MEMS (MEMS) are a kind of common structures in the MEMS device.It generally comprises curved beam and shell etc., and this structure is generally used for making movable micro-structural, is applied in all kinds of microsensors and the microactrator.For various forms of planes movable structure, its production method is fairly simple, and technology is very ripe.Compare with the plane movable structure, domes have more advantage at aspects such as span, amount of deflection, structural stability, bending resistance and anti-adhesive property.
Document 1 (Cheol-Hyun Han etc.; Paper title: Micromachined piezoelectric ultrasonic transducerson dome-shaped-diaphragm in silicon substrate; 1999 IEEE Ultrasonics Symoposium Proceedings; Be on the arch mould, to have made a kind of MEMS domes in October, 1999 P1167-1172).The method is the isotropy hole that to etch a diameter be 2mm in the silicon chip front; Owing to adopt isotropic etch; Erosional surface is bent type concave surface; In concave surface, make domes type transducer then, remove the silicon below the domes transducer through the silicon chip back-etching at last, form the complete and independent domes.The advantage of this method is that manufacturing process is simple, and shortcoming is that it is lower to make efficient owing to need the silicon chip of etch thicknesses 2mm, and the size of domes is bigger.
Document 2 (Robert B.Reichenbach etc., Resistively actuated micromechanical dome resonators, Proceedings of SPIE; Vol.5344; 2004, P 51-58) be a kind of micromechanical resonator, its manufacturing approach is: through at SiO 2Produce polysilicon membrane on the sacrifice layer,, and discharge SiO at 1200 ℃ of high annealings 2Sacrifice layer produces compression in polysilicon membrane, polysilicon membrane arches upward, and forms the MEMS domes.The advantage of this method is can batch making.Shortcoming is: 1) because domes are produced on the sacrifice layer, before making domes, need etching sacrificial layer, around sacrifice layer, produce more steep step, cause fracture easily; 2) discharge SiO through high annealing 2Sacrifice layer has produced bigger thermal stress and compression in domes inside, and structure is caused potential safety hazard; 3) high-temperature technology also can exert an influence to the performance that is integrated in the circuit on the same chip.
Therefore, be badly in need of the low-temperature preparation method of a kind of suitable making micron order, internal stress is less, the sacrifice layer step is level and smooth domes.
Summary of the invention
For addressing the above problem, the present invention proposes a kind of manufacturing approach of MEMS domes, and the domes size that has now in the MEMS domes manufacturing process is big to overcome, internal stress is big, the rough problem in sacrifice layer step place.
For realizing above-mentioned purpose, the manufacturing approach of a kind of MEMS domes of the present invention may further comprise the steps:
(1) on silicon chip, carries out photoetching, etching, form groove;
(2) deposit SiO on the said silicon chip that forms groove 2Sacrifice layer;
(3) adopt CMP process for the first time, leveling is carried out on the surface of silicon chip, the SiO of silicon chip surface 2Remove totally, fill up SiO in the groove 2Sacrifice layer;
(4) adopt CMP process for the second time, remove the certain thickness silicon layer of silicon chip surface;
(5) deposit supporting layer on the silicon chip behind said twice glossing;
(6) photoetching supporting layer, and on supporting layer, leave corrosion window;
(7) adopt dry method or wet corrosion technique, SiO is removed in corrosion 2Sacrifice layer finally forms a kind of MEMS domes.
Gash depth in the said step (1) is 1-10 μ m.
SiO in the said step (2) 2Sacrificial layer thickness is greater than the degree of depth of groove.
Said step is carried out chemically mechanical polishing in (3), and the degree of depth of its polishing is no more than SiO 2The thickness of sacrifice layer.
Said step is carried out chemically mechanical polishing in (4), and the degree of depth of its polishing is no more than the degree of depth of groove.
The material of the supporting layer in the said step (5) can be polysilicon or silicon nitride or various metal.
According to the different components purposes, if need to keep the SiO in the groove 2Sacrifice layer, said step (7) can inoperation.
Beneficial effect:
Because the inventive method has adopted above-mentioned technical scheme, compares with the technology of having reported, the manufacturing approach of MEMS domes of the present invention has following characteristics:
1. the inventive method can not make the internal stress of domes less at the inner stress that produces of domes owing to adopted the selective chemical mechanical polishing process, has avoided the inner existence of domes more high-prestressed.Domes form SiO by twice selective chemical mechanical polishing process 2Sacrifice layer/Si interface contacts with polishing pad cmpletely, and therefore, sacrifice layer step place is level and smooth, has avoided the problem of easy fracture.
2. the inventive method has adopted low temperature process, compare with document 2, has avoided high-temperature technology to circuit or the performance of device that is integrated on the same chip exerted an influence.
3. the silicon wafer thickness of document 1 is 2 millimeters, adopt with the anisotropy corrosion, so the diameter of its hole is 2 millimeters; Can't form micron order, the inventive method then adopts chemical wet etching ditching groove, and the width of groove and the degree of depth all have only several microns; Can reach micron order, the size of its domes is littler, therefore; The domes that the present invention makes can be realized the micron order structure, and technology is simple, make efficiency is high.
Description of drawings
Fig. 1 carries out photoetching, etching, the silicon chip generalized section behind the formation groove on silicon chip;
Fig. 2 is deposit SiO on the silicon chip of Fig. 1 2Generalized section behind the sacrifice layer;
Fig. 3 is the generalized section after leveling on the silicon chip of Fig. 2;
Fig. 4 is the generalized section behind the certain thickness that removes silicon chip surface on the silicon chip of Fig. 3;
Fig. 5 is the generalized section behind deposit supporting layer on the silicon chip of Fig. 4;
Fig. 6 is that SiO is removed in photoetching supporting layer, corrosion on the silicon chip of Fig. 5 2Sacrifice layer, finally form a kind of generalized section of MEMS domes;
Among Fig. 1-6,1 is silicon chip, and 2 is groove, and 3 is SiO 2Sacrifice layer, 31 is the SiO behind the CMP 2Sacrifice layer, 32 is the arch SiO behind the secondary CMP 2Sacrifice layer, 4 is supporting layer.
The specific embodiment
Below in conjunction with specific embodiment and accompanying drawing, the present invention is done further detailed description.Concrete steps of the present invention are following:
1. on silicon chip 1, carry out photoetching, etching, form groove 2:
(1) select the P type silicon chip 1 of < 100>crystal orientation, thickness 525 ± 20 μ m, resistivity 7-13 Ω cm for use, clean, oxidation, oxidated layer thickness is 0.6 ± 0.05 μ m;
(2) trench region 2 is left in conventional photoetching;
(3) use the ammonium fluoride corrosive agent, be etched away the SiO on the trench region 2 2
(4) with under the KOH solution of mass percent 20%~30%, 70 ℃, wet etching 3~5min forms groove 2, and the degree of depth of groove is 3~5 μ m, and is as shown in Figure 1.
2. deposit SiO on the said silicon chip that forms groove 2Sacrifice layer 3:
Silicon chip to having formed groove cleans, under 400 ℃, adopt pecvd process, the thick SiO of deposit 3~5 μ m 2Sacrifice layer 3, as shown in Figure 2.Wherein, sacrificial layer thickness must be greater than the degree of depth of groove.
3. adopt CMP process for the first time, leveling is carried out on the surface of silicon chip, the SiO of silicon chip surface 2Remove totally, fill up SiO in the groove 2Sacrifice layer 31:
Select the silica polishing fluid for use, adopt conventional chemical machine glazed finish (CMP) technology that silicon chip is carried out leveling, the SiO of silicon chip surface 2Remove totally, in groove, still fill up SiO 2Sacrifice layer 31, its thickness are 3~4 μ m.As shown in Figure 3.Wherein, the degree of depth of polishing can not surpass the thickness of sacrifice layer.
4. adopt CMP process for the second time, remove the silicon layer of 1~2 μ m thickness of silicon chip surface:
Select monocrystalline silicon buffing liquid for use, adopt the conventional chemical mechanical polishing process that silicon chip surface is polished, remove the silicon layer of silicon chip surface 1~2 μ m thickness.Since monocrystalline silicon buffing liquid to the corrosion rate of monocrystalline silicon much larger than it to SiO 2Corrosion rate, so groove in arch SiO 2Sacrifice layer 32 has formed convex domes, SiO 2The thickness of sacrifice layer 32 is 3~4 μ m, and is as shown in Figure 4.Wherein, the degree of depth of polishing is no more than the degree of depth of groove.
5. deposit supporting layer on the silicon chip behind said twice glossing:
Silicon chip behind said twice glossing is cleaned, adopt pecvd process down at 400 ℃, the thick silicon nitride of deposit 1~2 μ m, as supporting layer 4, as shown in Figure 5.
But supporting layer 4 material polysilicons, silicon nitride and various metal.
6. photoetching supporting layer, and on supporting layer, leave corrosion window.
7. adopt dry method or wet corrosion technique, SiO is removed in corrosion 2Sacrifice layer finally forms a kind of MEMS domes, and is as shown in Figure 6.
According to the needs of different components purposes, if need to keep the SiO in the groove 2Sacrifice layer can not carry out the operation of step (7).
The photoetching of indication, etching in the inventive method, remove photoresist, cleaning, SiO 2Dry/wet corrosion and CMP technology, pecvd process etc. be those skilled in the art's routine techniques, theme that neither the inventive method is not described in detail in this.

Claims (7)

1. the manufacturing approach of MEMS domes is characterized in that: may further comprise the steps:
(1) on silicon chip, carries out photoetching, etching, form groove;
(2) deposit SiO on the said silicon chip that forms groove 2Sacrifice layer;
(3) adopt CMP process for the first time, leveling is carried out on the surface of silicon chip, the SiO of silicon chip surface 2Remove totally, fill up SiO in the groove 2Sacrifice layer;
(4) adopt CMP process for the second time, remove the certain thickness silicon layer of silicon chip surface;
(5) deposit supporting layer on the silicon chip behind said twice glossing;
(6) photoetching supporting layer, and on supporting layer, leave corrosion window;
(7) adopt dry method or wet corrosion technique, SiO is removed in corrosion 2Sacrifice layer finally forms a kind of MEMS domes.
2. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: the gash depth in the said step (1) is 1-10 μ m.
3. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: the SiO in the said step (2) 2Sacrificial layer thickness is greater than the degree of depth of groove.
4. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: said step is carried out chemically mechanical polishing in (3), and the degree of depth of its polishing is no more than SiO 2The thickness of sacrifice layer.
5. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: said step is carried out chemically mechanical polishing in (4), and the degree of depth of its polishing is no more than the degree of depth of groove.
6. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: the material of the supporting layer in the said step (5) can be polysilicon or silicon nitride or various metal.
7. the manufacturing approach of a kind of MEMS domes according to claim 1 is characterized in that: according to the different components purposes, if need to keep the SiO in the groove 2Sacrifice layer, said step (7) can inoperation.
CN2011103086458A 2011-10-12 2011-10-12 Manufacturing method of micro-electromechanical systems (MEMS) arch structure Pending CN102358613A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106430080A (en) * 2016-10-13 2017-02-22 重庆中科渝芯电子有限公司 Production method for MEMS wide-groove and low-step structure
CN111791026A (en) * 2020-06-15 2020-10-20 深圳市精铸模具有限公司 Micro-thin metal device manufactured by electroforming and precision machining process

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080628A (en) * 1998-05-15 2000-06-27 Vanguard International Semiconductor Corporation Method of forming shallow trench isolation for integrated circuit applications
EP1143506A2 (en) * 2000-04-04 2001-10-10 Nippon Telegraph and Telephone Corporation Pattern forming method
CN1858922A (en) * 2006-05-26 2006-11-08 中国科学院上海微系统与信息技术研究所 Method for preparing phase shift storage by silicon wet etching and keying process
CN101097860A (en) * 2007-06-28 2008-01-02 西安电子科技大学 Fabrication method of air bridge in compound semiconductor microwave high power device
JP2008194816A (en) * 2007-01-26 2008-08-28 Commiss Energ Atom Method of manufacturing cover for protecting component on substrate
CN101859725A (en) * 2009-04-07 2010-10-13 和舰科技(苏州)有限公司 Method for forming wafer by improving edge of shallow trench isolation structure
CN102044489A (en) * 2009-10-14 2011-05-04 台湾积体电路制造股份有限公司 Process for producing substrates free of patterns using an alpha stepper to ensure results
CN102209683A (en) * 2008-11-10 2011-10-05 Nxp股份有限公司 Mems devices

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080628A (en) * 1998-05-15 2000-06-27 Vanguard International Semiconductor Corporation Method of forming shallow trench isolation for integrated circuit applications
EP1143506A2 (en) * 2000-04-04 2001-10-10 Nippon Telegraph and Telephone Corporation Pattern forming method
CN1858922A (en) * 2006-05-26 2006-11-08 中国科学院上海微系统与信息技术研究所 Method for preparing phase shift storage by silicon wet etching and keying process
JP2008194816A (en) * 2007-01-26 2008-08-28 Commiss Energ Atom Method of manufacturing cover for protecting component on substrate
CN101097860A (en) * 2007-06-28 2008-01-02 西安电子科技大学 Fabrication method of air bridge in compound semiconductor microwave high power device
CN102209683A (en) * 2008-11-10 2011-10-05 Nxp股份有限公司 Mems devices
CN101859725A (en) * 2009-04-07 2010-10-13 和舰科技(苏州)有限公司 Method for forming wafer by improving edge of shallow trench isolation structure
CN102044489A (en) * 2009-10-14 2011-05-04 台湾积体电路制造股份有限公司 Process for producing substrates free of patterns using an alpha stepper to ensure results

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106430080A (en) * 2016-10-13 2017-02-22 重庆中科渝芯电子有限公司 Production method for MEMS wide-groove and low-step structure
CN111791026A (en) * 2020-06-15 2020-10-20 深圳市精铸模具有限公司 Micro-thin metal device manufactured by electroforming and precision machining process

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Application publication date: 20120222