CN102355237A - Multiple input-multiple clock maintenance obstruction type JK trigger - Google Patents

Abstract

The invention discloses a multi-input-multi-clock maintaining blocking type JK flip-flop, the JK flip-flop includes a multi-input basic RS latch, two or more input units and a JK conversion circuit; the multi-input basic latch The two output terminals of the device are respectively q and nq; the number of the input unit and the JK conversion circuit is the same; the two output terminals of any one of the input units are respectively connected to the input terminals of the multi-input basic latch to form Maintain blocking D flip-flop; the input unit includes a data input end and a clock trigger end; the data input end of the input unit is connected to the output end of the JK conversion circuit; the JK conversion circuit includes two data input ends. The present invention can be used as a common memory, and is applied to the design of sequential circuits, especially the design of distributed systems and asynchronous circuits driven by events. Compared with the existing flip-flops, in the case of multiple data inputs, the event Drive, data selection circuit is simple, storage speed is fast.

Description

A Multi-Input-Multi-Clock Sustained Blocking JK Flip-Flop

technical field

The invention belongs to the field of electronic technology, and in particular relates to a flip-flop circuit, in particular to a maintenance blocking JK flip-flop with multiple data input channels and multiple clock terminals and a circuit with trigger priority. the

Background technique

Flip-flop is a device with storage function, which is used to form various sequential logic circuits in digital electronic technology. There are many types of flip-flops: according to the trigger mode, it is divided into level trigger, master-slave trigger, and edge trigger; according to the logic function, it is divided into RS flip-flop, D flip-flop, JK flip-flop, T flip-flop, etc. The characteristics of the trigger are described by the trigger mode and logic function. The trigger mode is used to determine the characteristics of the state change, that is, the way to receive the input signal to change the state; the logic function determines the direction of the state change, that is, the next state value. Existing flip-flops all have a single data input channel and a single clock terminal. the

Since existing flip-flops have only one clock terminal, in the design of a synchronous circuit, the clock terminals of all flip-flops are connected together. With the continuous improvement of integrated circuit integration, the contradictions caused by this method, such as clock offset, clock load current, power consumption, electromagnetic radiation interference, etc., are prominent, and event-driven distributed systems and asynchronous circuits have overcome the synchronous However, the existing flip-flops are inconvenient for the design of event-driven distributed systems and asynchronous circuits. the

Contents of the invention

The purpose of the present invention is to provide a JK flip-flop with multiple data input channels and multiple clock terminals and its trigger priority circuit, each data input terminal of the JK flip-flop corresponds to a clock trigger terminal, and each clock trigger terminal uses to receive an external trigger event. the

The technical scheme of the present invention is: a multi-input-multi-clock maintenance blocking type JK flip-flop, comprising a multi-input basic RS latch, two and more input units and JK conversion circuits; the multi-input basic RS lock The two output terminals of the register are respectively q and nq; the quantity of the input unit and the JK conversion circuit is the same; the two output terminals of any one of the input units are respectively connected to the input terminals of the multi-input basic RS latch, To form a maintenance blocking type D flip-flop; the input unit includes a data input end and a clock trigger end; the data input end of the input unit is connected to the output end of the JK conversion circuit; the JK conversion circuit includes two data input end. the

Further, the input unit is composed of two basic RS latches; one input terminal of the two basic RS latches is the clock trigger terminal. the

Further, the JK conversion circuit is composed of an OR gate, two AND gates and a NOT gate, the first data input end of the two data input ends is connected to the first AND gate input end, and the second data input end is passed through the NOT gate Afterwards, be connected with the second AND gate; the other input terminal of the first AND gate is connected to the output terminal nq, and the other input terminal of the second AND gate is connected to the output terminal q; the two AND gates The output end of the OR gate is connected with the input end of the OR gate; the output end of the OR gate is the output end of the JK conversion circuit. the

Further, the multi-input-multi-clock maintaining blocking JK flip-flop includes a priority circuit, and the output end of the priority circuit is connected to the clock trigger end of the input unit. the

Further, the priority circuit includes one or more AND gate circuits, and the number of the AND gate circuits is one less than the number of the input units; except for the input unit with the highest priority, any of the AND gate circuits The input terminals of the circuit are connected to the clock signals of all high-priority input units and the clock signals of the connected input units. the

Further, there are three input units. the

The beneficial effects of the present invention are: each data input channel of the multi-input-multi-clock maintaining blocking type JK flip-flop corresponds to a clock terminal, and the clock terminal of the flip-flop is used to receive an external trigger event. When an external event occurs, the data in the corresponding data input channel is latched. When multiple events arrive at the same time, in order to avoid causing data conflicts, a priority circuit is used to improve the multi-input-multi-clock maintaining blocking JK flip-flop circuit so that the clock with the highest priority can be triggered. The present invention can be used as a common memory, applied to the design of sequential circuits, especially suitable for the design of distributed systems and asynchronous circuits driven by events. Compared with the existing flip-flops, in the case of multiple data input, directly by Event-driven, simple data selection circuit, fast storage speed. the

Description of drawings

Figure 1 is a circuit schematic diagram of a 3-input-3 clock maintaining blocking JK flip-flop

Figure 2 is a 3-input-3 clock maintaining blocking JK function simulation diagram

Figure 3 is a circuit schematic diagram of a 3-input-3 clock maintenance blocking JK flip-flop with priority

Figure 4 is a functional simulation diagram of a 3-input-3 clock maintenance blocking JK flip-flop with priority

Detailed ways

Fig. 1 is an embodiment of the present invention, a circuit schematic diagram of a 3-input-3 clock maintaining blocking JK flip-flop, the flip-flop has three sets of data inputs (j1, k1), (j2, k2), (j3, k3), The corresponding three clocks are cp1, cp2, and cp3, and the output terminals are q and nq, and nq and q are logically complementary.

The 3-input-3 clock maintaining blocking JK flip-flop includes a multi-input basic RS latch, 3 input units and 3 JK conversion circuits. Wherein the NAND gates I20, I21, I22, I25 form the first input unit, the NAND gates I17, I18, I19, I24 form the second input unit, and the NAND gates I14, I15, I16, I23 form the third input unit; or Gate I30, AND gate I35, I36 and NAND gate I38 form the first JK conversion circuit, OR gate I29, AND gate I33, I34 and NAND gate I37 form the second JK conversion circuit, OR gate I28, AND gate I31, I32 The NAND gate I39 forms the third JK conversion circuit. the

The output terminal of the first input unit is connected with the multi-input basic RS latch to form a first group of sustain blocking D flip-flops; the output terminal of the first JK conversion circuit is connected with the data input terminal of the first input unit. The first JK conversion circuit comprises two data input terminals j1 and k1, the input terminal j1 is connected with the input terminal of the AND gate I36, and the input terminal k1 is connected with the AND gate I35 after being reversed by the NAND gate I38; the other input terminal of the AND gate I36 Connect output terminal nq, another input terminal of AND gate I35 is connected output terminal q; The output terminal of AND gate I35 and I36 is connected with the input terminal of OR gate I30; The output terminal of OR gate I30 is the output terminal of described JK conversion circuit . the

The output end of the second input unit is connected with the multi-input basic RS latch to form a second group of blocked D flip-flops; the output end of the second JK conversion circuit is connected with the data input end of the second input unit. The second JK conversion circuit comprises two data input terminals j2 and k2, the input terminal j2 is connected with the input terminal of the AND gate I34, and the input terminal k2 is connected with the AND gate I33 after being reversed by the NAND gate I37; the other input terminal of the AND gate I34 Connect output terminal nq, another input terminal of AND gate I33 is connected output terminal q; The output terminal of AND gate I33 and I34 is connected with the input terminal of OR gate I29; The output terminal of OR gate I9 is the output terminal of described JK conversion circuit . the

The output terminal of the third input unit is connected with the multi-input basic RS latch to form a third group of sustain blocking D flip-flops; the output terminal of the third JK conversion circuit is connected with the data input terminal of the third input unit. The 3rd JK conversion circuit comprises two data input ends j3 and k3, and input end j3 is connected with the input end of AND gate I32, and input end k2 is connected with AND gate I31 after being reversed by NAND gate I39; The other input end of AND gate I32 Connect output terminal nq, another input terminal of AND gate I31 is connected output terminal q; The output terminal of AND gate I31 and I32 is connected with the input terminal of OR gate I28; The output terminal of OR gate I28 is the output terminal of described JK conversion circuit . the

Taking the first group of JK conversion circuits as an example, the input signal k1 is inverted through the NAND gate I38 and then through the AND gate I35 and the signal at the output terminal q for AND logic operation, and the input signal j1 is passed through the AND gate I36 and the multi-input-multiple output The signal at the output terminal nq of the maintaining blocking type JK flip-flop is subjected to an AND logic operation, and the outputs of the AND gates I35 and I36 are subjected to an OR logic operation through the OR gate I30, and its output is used as the input signal of the first group of maintaining blocking type D flip-flops. In this way, the first group of sustain blocking D flip-flops and the first JK conversion circuit jointly constitute the first group of sustain blocking JK flip-flops; the working principle of the other two groups of JK flip-flops is the same as that of the first group of JK flip-flops. Other multi-input-multi-clock JK flip-flops can be expanded according to the circuit structure shown in Figure 1 according to the number of data input channels. the

In the first group of maintained blocking D flip-flop circuits, two basic RS latches composed of I20, I21, I25, and I22 respond to external input data d1 (output of I30) and clock cp1, and their outputs are used as inputs by I12, The direct reset (R) and direct set signal (S) of the third basic RS latch formed by I13 determine the state of the flip-flop. the

，I20输出为d1。d1信号进入触发器，为触发器状态刷新做好准备。  (1) When cp1=0, the NAND gates I21 and I25 are blocked, and their output is 1, so that the output latch is in a holding state, the output q and nq of the flip-flop do not change state, and the feedback signals of I21 and I25 Open the two gates of I20 and I22 respectively, so that the output of I22 is

, I20 output is d1. The d1 signal goes into the flip-flop ready for the flip-flop state refresh.

,触发器按此前d1的逻辑值刷新。  (2) Immediately after cp1 changes from 0 to 1, I21 and I25 are turned on, and their output states are determined by the output states of I20 and I22. The two are always in a complementary logical relationship, ensuring the RS latch constraint RS=0, It can be seen from the logic function of the basic RS latch that at this time

, the trigger is refreshed according to the previous logical value of d1.

(3) During the period of cp1=1, the two basic RS latches composed of I20, I21, I25, and I22 can ensure that the output states of I21 and I25 remain unchanged, so that the state of the flip-flop is not affected by the change of the input signal d1 . When q=1, I21 output state is 0, then I20 and I25 are blocked. The feedback line from I21 to I20 makes the I20 output 1, and maintains the I21 output as 0, thereby maintaining the 1 state of the flip-flop, which is called the 1 maintenance line; the feedback line from the output of I21 to I25 makes the I25 output 1 , although the change of the d1 signal during this period may cause the output of I22 to change accordingly, but it will not change the output state of I25, thus blocking the 0-setting signal input at the d1 terminal, which is called the 0-setting blocking line. When q=0, the output of I25 is 0, then block I22, so that the output of I22 is 1, which blocks the way of d1=1 signal entering the flip-flop, and the output of I22 works together with cp1=1, and the output of I21 is 1 , the I25 output is maintained at 0, and the flip-flop is maintained at a 0 state, so the feedback line that outputs I25 to I22 is called a 1-blocking, 0-maintaining line. The working principle of the remaining two groups of maintaining blocking D flip-flops is the same. the

,JK触发器特性方程为

,令

，通过JK转换电路，就可将维持阻塞型D触发器转换为维持阻塞型JK触发器。  The D flip-flop characteristic equation is

, the characteristic equation of JK flip-flop is

,make

, through the JK conversion circuit, the maintaining blocking type D flip-flop can be converted into maintaining blocking type JK flip-flop.

。

通过I30和

进行或逻辑运算得到信号

+

作为第一组维持阻塞型D触发器的信号输入，即d1=

+

。其余两组JK转换电路工作原理与此相同。  In the first group of JK conversion circuits, the k1 input signal is inverted through I38, and then the output signal q of the multi-input-multiple output maintenance blocking JK flip-flop is carried out by I35 to obtain the signal , the input signal of j1 is obtained by AND logic operation through I36 and the output signal nq of the multi-input-multiple output maintaining blocking JK flip-flop

.

Via I30 and

Perform OR logic operation to get signal

+

As the signal input of the first group of maintenance blocking D flip-flops, that is, d1 =

+

. The working principles of the other two groups of JK conversion circuits are the same.

The working principle of the first group of maintaining blocking JK flip-flops is obtained above, and the working principles of the other two groups of maintaining blocking JK flip-flops are the same. the

的关系；当只有CP2时钟出现时，输出状态满足

的关系；当只有CP3时钟出现时，输出状态满足

的关系。结果显示了它的功能的正确性。  In order to verify its correctness, the functional simulation of the multi-input-multi-clock maintaining blocking JK flip-flop shown in Figure 1 is carried out, and the simulation waveform is shown in Figure 2 (J1, J2, J3, K1, K2 in Figure 2 , K3, CP1, CP2, CP3, Q, NQ correspond to j1, j2, j3, k1, k2, k3, cp1, cp2, cp3, q, nq in Figure 1, respectively). In the waveform diagram shown in Figure 2, when only the CP1 clock appears, the output state satisfies

The relationship; when only the CP2 clock appears, the output state satisfies

The relationship; when only the CP3 clock appears, the output state satisfies

Relationship. The results show the correctness of its function.

The 3-input-3 clock maintaining blocking JK flip-flop with priority designed in Figure 3 is converted from the 3-input-3 clock maintaining blocking JK flip-flop shown in Figure 1 . Each clock signal is connected to the input of the priority circuit. The priority circuit is composed of two AND gate circuits I26 and I27. The output of the priority circuit is then connected to each clock trigger terminal of the 3-input-3 clock maintaining blocking JK flip-flop. When the rising edge of cp1 arrives, I26 and I27 are blocked, and cp2 and cp3 are ineffective; when cp1 is low and the rising edge of cp2 arrives, I27 is blocked, and cp3 is ineffective. The priority order of this circuit is cp1>cp2>cp3. the

In order to verify its correctness, the functional simulation of the 3-input-3 clock maintenance blocking JK flip-flop with priority shown in Figure 3 is carried out, and the simulation waveform is shown in Figure 4 (J1, J2, J3 in Figure 4 , K1, K2, K3, CP1, CP2, CP3, Q, NQ correspond to j1, j2, j3, k1, k2, k3, cp1, cp2, cp3, q, nq in Figure 3, respectively). When the first pulses of CP1 and CP3 appear at the same time, since J1=0 and K1=1, the output Q=0, indicating that CP1 works and CP3 does not work; when the sixth pulse of CP1 and the first pulse of CP2 When the pulses appear at the same time, because J1=0, K1=1, Q=0, it means that CP1 works and CP2 does not work; when the fifth pulse of CP2 and the second pulse of CP3 appear at the same time, because J2=0, K2=0, so the output maintains the original state, that is, Q=1, which means that CP2 works and CP3 does not work. The results show the correctness of its function. the

The present invention is not limited to the above-mentioned specific embodiments, those skilled in the art can implement the present invention by adopting various other specific embodiments according to the technical contents disclosed in the present invention. Therefore, any multi-input-multi-clock, clock The design structure and idea of the priority circuit, applied to other structural forms, or converted flip-flops and application circuits composed of these flip-flops, all fall within the protection scope of the present invention. the

The present invention is particularly suitable for use in event-driven distributed systems and asynchronous circuits, as well as in handshaking protocols, FPGA circuits, and the like. the

Claims (6)

1. A multi-input-multi-clock maintains blocking type JK flip-flop, comprising a multi-input basic RS latch, two and above input units and JK conversion circuits; two outputs of the multi-input basic RS latch The terminals are q and nq respectively; the number of the input unit and the JK conversion circuit is the same; the two output terminals of any one of the input units are respectively connected to the input terminals of the multi-input basic RS latch to form a maintenance blocking type D flip-flop; the input unit includes a data input end and a clock trigger end; the data input end of the input unit is connected to the output end of the JK conversion circuit; the JK conversion circuit includes two data input ends. 2. A kind of multi-input-multi-clock maintaining blocking type JK flip-flop according to claim 1, is characterized in that: described input unit is made up of two basic RS latches; Both described two basic RS latches An output terminal is connected with the clock trigger terminal. 3. A kind of multi-input-multi-clock maintaining blocking type JK flip-flop according to claim 1 or 2, is characterized in that: said JK conversion circuit is made up of an OR gate, two AND gates and a NOT gate, so The first data input end of the JK conversion circuit is connected to the first AND gate input end, and the second data input end is connected to the second AND gate after passing through the NOT gate; the other input end of the first AND gate is connected to the output terminal nq, the other input end of the second AND gate is connected to the output end q; the output ends of the two AND gates are connected with the input end of the OR gate; the output end of the OR gate is the JK conversion output of the circuit. 4. A kind of multi-input-multi-clock maintaining blocking type JK flip-flop according to claim 2, characterized in that: said multi-input-multi-clock maintaining blocking type JK flip-flop comprises a priority circuit, and said priority circuit The output end is connected to the clock trigger end of the input unit. 5. A kind of multi-input-multi-clock maintaining blocking type JK flip-flop according to claim 4, characterized in that: said priority circuit comprises one and more AND gate circuits, the number of said AND gate circuits is greater than the The number of input units is one less; except for the input unit with the highest priority, the input end of any AND gate circuit is connected to the clock signals of all high-priority input units and the clock signal of the connected input unit. 6 . The multi-input-multi-clock sustain blocking JK flip-flop according to claim 5 , wherein there are three input units.

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