CN102347084B - Adjustment method, adjustment device and test system of reference unit threshold voltage - Google Patents
Adjustment method, adjustment device and test system of reference unit threshold voltage Download PDFInfo
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Abstract
The invention provides an adjustment method, an adjustment device and a test system of reference unit threshold voltage. The adjustment device comprises a state control machine located in a non-volatile memory chip, a programming device and a verification device. The state control machine comprises a reception module for receiving reference unit information from a test machine, and a control module for controlling the programming device and the verification device to work according to the reference unit information. The programming device is utilized for carrying out programming processes on a current reference unit. The verification device is utilized for carrying out verification processes on the current reference unit and then feeding back a verification result to the state control machine. The state control machine also comprises a determination module which is utilized for determining if the verification result satisfies preset conditions or not, wherein if the verification result satisfies the preset conditions, current adjustment is finished, and if the verification result does not satisfy the preset conditions, the determination module notices the control module so that the control module still controls the current reference unit. The adjustment method, the adjustment device and the test system of reference unit threshold voltage can reduce the time spent on reference unit threshold voltage adjustment.
Description
Technical Field
The invention relates to the technical field of semiconductor chip testing, in particular to a method and a device for adjusting the threshold voltage of a reference unit and a testing system.
Background
In order to verify the correctness of the nonvolatile memory product, a series of test procedures are performed before the product is shipped. These non-volatile memory products may include Flash memory Flash, electrically erasable programmable read-only memory EEPROM, and the like.
In practice, before performing the logic function test, the electrical erasing characteristic test and the program code test, the threshold voltage of the reference cell of the nonvolatile memory chip to be tested needs to be precisely adjusted.
Take SLC (Single Layer Cell) Flash memory as an example, the read-out principle is briefly introduced: the same gate terminal and drain terminal voltages are applied to the memory cell and the reference cell, and the drain terminal currents thereof are compared, and if the current of the memory cell is larger than that of the reference cell, it is defined that "1" is stored, whereas it is defined that "0" is stored. That is, the definition of a memory cell having a "1" and a "0" is to see that the threshold voltage of the memory cell is lower or higher than the threshold voltage of the reference cell. Therefore, the threshold voltage of the reference cell is a decision point for storing data, is the basis of the whole Flash memory readout system, and needs to be adjusted relatively accurately before testing.
Threshold Voltage Trimming (Threshold Voltage Trimming) refers to programming a reference cell to have its Threshold Voltage VTHAnd the requirements of system performance evaluation tests are met. Referring to fig. 1, a conventional method for adjusting a threshold voltage of a reference cell generally includes:
a programming step 101, performing a programming (Program) operation on a reference cell;
and a checking step 102, measuring the current of the reference unit, and judging whether the current meets a finishing condition, if so, finishing the adjustment, otherwise, returning to the programming step 101.
Wherein, the completion condition may be: the measured current is less than the target reference value.
The above method requires the programming step 101 and the verifying step 102 to be repeatedly performed until the verifying step 102 measures that the current meets the completion condition.
However, each time switching is performed between the programming step 101 and the verifying step 102, the testing machine needs to perform frequent power-down and power-up switching, for example, power-down for the programming step 101 and power-up for the verifying step 102, or power-down for the verifying step 102 and power-up for the programming step 101, and so on, which usually takes ms-order time to stabilize the voltage required by the testing machine; especially when the number of reference cells (e.g., 64,128) inside the nonvolatile memory chip is large, the switching will further increase the threshold voltage adjustment time, which results in a greatly increased test time and a greatly increased test cost.
In summary, one of the technical problems that needs to be urgently solved by those skilled in the art is: how to reduce the test time of the nonvolatile memory chip, especially the adjustment time of the threshold voltage of the reference unit.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method and a device for adjusting the threshold voltage of a reference unit and a test system, which can greatly shorten the time for adjusting the threshold voltage of the reference unit and reduce the test cost.
In order to solve the above problems, the present invention discloses a reference cell threshold voltage adjusting device, which comprises a control state machine, a programming device and a verifying device, wherein the control state machine, the programming device and the verifying device are arranged in a nonvolatile memory chip; wherein,
the control state machine includes:
the receiving module is used for receiving reference unit information from the test machine; and
the control module is used for controlling the programming device and the verifying device to work according to the reference unit information;
the programming device is used for programming the current reference unit;
the checking device is used for checking the current reference unit and feeding back a checking result to the control state machine;
the control state machine further comprises:
and the judging module is used for judging whether the checking result meets the preset condition, if so, the adjustment of the current reference unit is ended, and otherwise, the control module is informed to continue to execute the control operation on the current reference unit.
Preferably, the programming device comprises a plurality of first enabling terminals, and the verifying device comprises a plurality of second enabling terminals;
the control module is used for controlling the programming device to work through the first enabling end according to the reference unit information and controlling the verifying device to work through the second enabling end.
Preferably, the apparatus further comprises: an external reference input path for generating a target current;
the checking device is used for measuring the current of the current reference unit, judging whether the measured current is smaller than the target current or not and feeding back the judgment result serving as a checking result to the control state machine;
the preset condition is that the check result is true.
Preferably, the receiving module is further configured to receive reference unit state query information from a test machine;
the control state machine further comprises:
and the state output module is used for outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
Preferably, the adjustment state includes: in operation, end of operation, and failure of operation.
On the other hand, the invention also discloses a test system, which comprises a test machine and the adjusting device of the threshold voltage of the reference unit;
the test machine is used for sending the reference unit information of the nonvolatile memory chip to the receiving module.
On the other hand, the invention also discloses a method for adjusting the threshold voltage of the reference unit, which is executed in the nonvolatile memory chip and comprises the following steps:
receiving reference unit information from a test machine;
generating a first control signal and a second control signal according to the reference unit information;
performing programming operation on the current reference unit according to the first control signal;
according to the second control signal, checking the current reference unit to obtain a checking result;
and judging whether the verification result meets a preset condition, if so, finishing the adjustment of the current reference unit, and otherwise, continuously executing programming operation on the current reference unit.
Preferably, the first control signal is a first enable signal, and the second control signal is a second enable signal.
Preferably, the method further comprises:
receiving externally input target current;
the checking step is that the current of the current reference unit is measured, whether the measured current is smaller than the target current or not is judged, and the judgment result is used as a checking result;
the preset condition is that the check result is true.
Preferably, the method further comprises:
receiving reference unit state query information from a test machine;
and outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
Preferably, the adjustment state includes: in operation, end of operation, and failure of operation.
Compared with the prior art, the invention has the following advantages:
according to the invention, the threshold voltage of the reference unit is adjusted in the nonvolatile memory chip, specifically, only voltage pulse and voltage in the chip are required to be multiplexed, and the normal work of a programming device and a verifying device in the chip can be controlled; the switching time of the magnitude order of mus is only needed from the power-off to the power-on of the internal voltage of the chip, so that the stable voltage of the test machine can be provided, and compared with the switching time of the magnitude order of ms in the prior art, the threshold voltage adjusting time of the reference unit can be greatly reduced;
moreover, compared with the limitation of one test channel in the prior art, the reference units in the chip can only be adjusted in series one by one, and the invention can adjust a plurality of reference units in the nonvolatile memory chip in parallel without the chip and an external test channel, thereby further reducing the whole test time of the reference units in the chip and further reducing the test cost.
Drawings
FIG. 1 is a flow chart of a method for adjusting a reference cell threshold voltage according to the prior art;
FIG. 2 is a block diagram of an embodiment of an apparatus for adjusting a threshold voltage of a reference cell according to the present invention;
FIG. 3 is an exemplary apparatus for adjusting the threshold voltage of a reference cell according to the present invention;
FIG. 4 is a block diagram of one embodiment of a test system of the present invention;
FIG. 5 is a flowchart of a method for adjusting the threshold voltage of a reference cell according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
One of the core concepts of the embodiment of the invention is that the adjustment of the threshold voltage of the reference unit is performed inside the nonvolatile memory chip; the time from the power-off to the power-on of the internal voltage of the nonvolatile memory chip is only in the order of mus, so that the stable voltage can be provided for a test machine, and the time for adjusting the threshold voltage of the reference unit can be reduced.
Referring to fig. 2, a structural diagram of an embodiment of an adjusting apparatus for reference cell threshold voltage according to the present invention is shown, and may specifically include a control state machine 201, a programming apparatus 202, and a verifying apparatus 203 located inside a nonvolatile memory chip; wherein,
the control state machine 201 may specifically include:
a receiving module 211, configured to receive reference unit information from a test machine; and
a control module 212, configured to control the programming device 202 and the verifying device 203 to operate according to the reference cell information;
the programming device 202 is used for performing programming operation on the current reference unit;
the checking device 203 is configured to perform a checking operation on the current reference unit, and feed back a checking result to the control state machine;
the control state machine 201 may further include:
a judging module 213, configured to judge whether the check result meets a preset condition, if so, end adjustment of the current reference unit, otherwise, notify the control module 212 to continue to perform control operation on the current reference unit.
The adjusting device of the invention can be applied to the test process of various nonvolatile memory chips, such as Flash chips, EEPROM chips, etc., and the following description only takes the Flash chips as an example, and other nonvolatile memory chips should be referred to.
In practice, a user can input the reference unit information in the form of instructions through a testing machine; suppose that the current Flash chip includes 128 reference units, the numbers are respectively: 0, 1, 2.,. 127, the reference unit information may be any combination of the reference unit numbers, such as { reference unit 0}, { reference unit 0, reference unit 50, reference unit 100}, etc., wherein the content in the set symbol { } represents the reference unit information.
In the invention, the control state machine 201 mainly has two functions, one is the interface function of the test machine, and the control state machine receives the reference unit information from the test machine; the second is a control function, i.e. according to the reference unit information. And controlling the programming device 202 and the verifying device 203 to work, and automatically completing the adjustment of the threshold voltage of the reference cell.
In particular, the control state machine 201 is capable of controlling all operations of the programming means 202, and all operations of the verification means 203.
In a specific implementation, the control may be implemented based on an enable signal; for example, a plurality of first Enable (Enable) terminals a are provided in the programming device 202, wherein each first Enable terminal a corresponds to a programming operation; thus, for the first enable terminal a, when it is valid, the corresponding programming operation is started, and when it is invalid, the corresponding programming operation is ended; therefore, the control module 212 can control all operations of the programming device 202 by controlling all the first enable terminals a.
Similarly, a plurality of second enabling terminals B may also be arranged in the verifying apparatus 203, where each second enabling terminal B corresponds to one verifying operation; the control module 212 may control all operations of the verifying unit 203 by controlling all the second enabling terminals B.
In order to make the present invention better understood by those skilled in the art, the following describes the adjustment process of the present invention by specific examples, which may specifically include:
step S1, the receiving module 211 receives the reference unit information { reference unit 0} from the test machine;
in practice, reference cells in a Flash chip may be represented using address bits, e.g., 128 reference cells using 7 bits of data, 64 reference cells using 6 bits of data, etc.; thus, the programming device 202 and the verifying device 203 can know the operation object according to the specific address bit.
Step S2, the control module 212 controls the programming device 202 to perform a programming operation with respect to the reference cell 0;
for example, when initiating the programming operation, the control module 212 may cause the programming device 202 to apply a voltage pulse of magnitude 4V and width 2 μ s to the drain terminal (drain) of the reference cell via the active first enable terminal A1, and cause the programming device 202 to apply a voltage of 9.5V to the gate terminal (gate) of the reference cell via the active first enable terminal A2, and so on.
At the end of the program operation, the control module 212 may turn off the voltage of the drain terminal by disabling the first enable terminal a1, and cause the voltage of the gate terminal to become 0 by disabling the first enable terminal a2, and so on.
Step S3, the control module 212 controls the calibration apparatus 203 to perform a calibration operation with respect to the reference cell 0, and feeds back a calibration result to the control state machine;
for example, when initiating the entire verify operation, the control module 212 may cause the verifying device 203 to apply a voltage of 1V to the drain terminal of the reference cell through the active second enable terminal B1, and cause the verifying device 203 to apply a voltage of 7V to the gate terminal of the reference cell through the active second enable terminal B2, and so on.
In the case of switching between steps, step S2 involves the powering down of the voltage: drain terminal 4V → 0, gate terminal 9.5V → 0; step S3 involves the power-up of the voltage: drain terminal 0 → 1V, gate terminal 0 → 7V; wherein, symbol → represents the voltage variation process.
Because the chip is internally provided with voltage pulses and voltages, the programming device 202 and the verifying device 203 can work normally only by multiplexing the voltage pulses and the voltages; the time from the power-off to the power-on of the internal voltage of the chip only needs the time of the order of mu s, and the stable voltage can be provided for the test machine, so that the method can greatly reduce the adjustment time of the threshold voltage of the reference unit compared with the switching time of the order of ms in the prior art.
After the verifying device 203 applies voltages to the drain terminal and the gate terminal of the reference cell, the verifying device 203 may work by measuring the current of the current reference cell and determining the measured current IrefWhether or not less than the target current ITHAnd feeding back the judgment result as a verification result to the control state machine; that is, the verification result in this case may include: true and false.
Referring to FIG. 3, in one example of the invention, the target current ITHMay originate from the external reference input path 3A, i.e. the external reference input path 3A is connected to the input of the checking means 203.
Step S4, the determining module 213 determines whether the check result meets a preset condition, if so, the adjustment of the current reference unit is ended, otherwise, the control module 212 is notified to continue to perform the control operation on the current reference unit.
Corresponding to the above example, when the check result is true, the preset condition is met, and the control state machine 201 can end the adjustment of the current reference unit; and when the verification result is false, continuing to control the programming device 202 and the verifying device 203 to work for the current reference unit.
In a preferred embodiment of the present invention, when a user has a need for adjusting the state of a certain reference unit, a query instruction may be sent to the Flash chip through the test machine.
For example, when the query instruction is the reference unit state query information, the receiving module 211 may be further configured to receive the reference unit state query information from the test equipment;
at this time, the control state machine 201 may further include:
and the state output module is used for outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
In practice, the status output module may use the combination of the output values of the data bits to represent various adjustment statuses of a reference unit, for example, 00 represents operating, 01 represents end of operating, and 10 represents failure of operating, and the tester may obtain these adjustment statuses through a read operation, and the invention is not limited to a specific output manner.
Referring to fig. 4, an embodiment of a test system according to the present invention is shown, which may specifically include:
the chip testing device comprises a probe station 401 and a testing machine station 402, wherein a chip 403 to be tested is installed in the probe station 401 and is connected with the testing machine station 402 through the probe station 401; and
a reference cell threshold voltage adjusting device 404 located inside the chip 403 to be tested;
the test machine 402 may send a test instruction to the chip 403 to be tested through the probe station 401, where the test instruction may include reference unit information and the like;
further, the adjusting device 404 for the threshold voltage of the reference cell may specifically include: a control state machine 4041, a programming device 4042, and a verification device 4043;
the control state machine 4041 may specifically include:
a receiving module 40411, configured to receive reference unit information from the test tool 402; and
a control module 40412, configured to control the programming device 4042 and the verifying device 4043 to operate according to the reference unit information;
the programming device 4042 is used for performing programming operation on the current reference unit;
the checking device 4043 is configured to perform a checking operation on the current reference unit, and feed back a checking result to the control state machine;
the control state machine 4041 may further include:
a judging module 40413, configured to judge whether the check result meets a preset condition, if so, end adjustment of the current reference unit, otherwise, notify the control module 40412 to continue to perform control operation on the current reference unit.
In practice, the chip 403 to be tested may be a nonvolatile memory chip such as a Flash chip or an EEPROM chip.
Specifically, the programming device 4042 may include a plurality of first enable terminals, and the verifying device 4043 may include a plurality of second enable terminals;
at this time, the control module 40412 is configured to control the programming apparatus 4042 to operate through the first enabling terminal and control the verifying apparatus 4043 to operate through the second enabling terminal according to the reference cell information.
Preferably, the adjusting device 404 for the threshold voltage of the reference cell may further include: an external reference input path for generating a target current;
correspondingly, the checking device 4043 is configured to measure the current of the current reference unit, determine whether the measured current is smaller than the target current, and feed back a determination result as a checking result to the control state machine;
the preset condition at this time is that the check result is true.
When a user has a need for adjusting the state of a certain reference cell, the test machine 402 may also send a query instruction to the chip 403 to be tested, and the adjusting device 404 for the threshold voltage of the reference cell in the chip 403 to be tested may feed back corresponding operation state information to the test machine 402: in operation, end of operation, failure of operation, etc.
For example, when the query instruction is reference unit status query information, the receiving module 40411 may be further configured to receive reference unit status query information from the test machine 402;
at this time, the control state machine 4041 may further include:
and the state output module is used for outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
Corresponding to the foregoing device embodiment, the present invention further discloses a method for adjusting a reference cell threshold voltage, where the method is executed in a nonvolatile memory chip, and with reference to fig. 5, the method may specifically include:
502, generating a first control signal and a second control signal according to the reference unit information;
in practice, the first control signal should be able to control various programming operations, and in particular, a first enable signal may be employed to enable various programming operations; likewise, a second enable signal may be employed to enable various verify operations.
And 505, judging whether the verification result meets a preset condition, if so, finishing the adjustment of the current reference unit, otherwise, returning to 503 to continue to execute the programming operation on the current reference unit.
In a preferred embodiment of the present invention, the adjusting method may further include the steps of:
receiving externally input target current;
at this time, the execution process of step 504 may be to measure the current of the current reference cell, determine whether the measured current is smaller than the target current, and use the determination result as the verification result;
the preset condition in step 505 may be that the verification result is true.
In another preferred embodiment of the present invention, in response to a user's requirement for a regulation status of a reference unit, the regulation method may further include:
receiving reference unit state query information from a test machine;
and outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
Wherein the adjusting state may include: in operation, end of operation, and failure of operation, etc.
The invention has the following advantages:
1. adjusting the threshold voltage of a reference unit in a nonvolatile memory chip; the time from the power-off to the power-on of the internal voltage of the nonvolatile memory chip is only in the order of mus, so that the stable voltage can be provided for a test machine, and the time for adjusting the threshold voltage of the reference unit can be reduced.
2. Because only one test channel is arranged on one nonvolatile memory chip, the prior art can only carry out serial adjustment on the reference units in the chip one by one, but the invention does not need the chip and an external test channel and can carry out parallel adjustment on a plurality of reference units in the nonvolatile memory chip, thereby further reducing the whole time of the test of the reference units in the chip.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. As for the method embodiment, since it is basically similar to the apparatus embodiment, the description is simple, and the relevant points can be referred to the partial description of the apparatus embodiment.
The method, the device and the test system for adjusting the threshold voltage of the reference cell provided by the invention are introduced in detail, and a specific example is applied in the text to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (11)
1. The adjusting device of reference unit threshold voltage is characterized by comprising a control state machine, a programming device and a verifying device which are positioned in a nonvolatile memory chip; wherein,
the control state machine includes:
the receiving module is used for receiving reference unit information from the test machine; and
the control module is used for controlling the programming device and the verifying device to work according to the reference unit information;
the programming device is used for programming the current reference unit;
the checking device is used for checking the current reference unit and feeding back a checking result to the control state machine;
the control state machine further comprises:
and the judging module is used for judging whether the checking result meets the preset condition, if so, the adjustment of the current reference unit is ended, and otherwise, the control module is informed to continue to execute the control operation on the current reference unit.
2. The apparatus of claim 1, wherein the programming means comprises a plurality of first enable terminals, the verifying means comprises a plurality of second enable terminals;
the control module is used for controlling the programming device to work through the first enabling end according to the reference unit information and controlling the verifying device to work through the second enabling end.
3. The apparatus of claim 1 or 2, further comprising: an external reference input path for generating a target current;
the checking device is used for measuring the current of the current reference unit, judging whether the measured current is smaller than the target current or not and feeding back the judgment result serving as a checking result to the control state machine;
the preset condition is that the check result is true.
4. The apparatus of claim 1 or 2, wherein the receiving module is further configured to receive reference cell status query information from a test machine;
the control state machine further comprises:
and the state output module is used for outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
5. The apparatus of claim 4, wherein the adjustment state comprises: in operation, end of operation, and failure of operation.
6. A test system comprises a test machine and a reference cell threshold voltage adjusting device of any one of the above 1 to 2;
the test machine is used for sending the reference unit information of the nonvolatile memory chip to the receiving module.
7. A method for adjusting a threshold voltage of a reference cell, the method being performed within a non-volatile memory chip, comprising:
receiving reference unit information from a test machine;
generating a first control signal and a second control signal according to the reference unit information;
performing programming operation on the current reference unit according to the first control signal;
according to the second control signal, checking the current reference unit to obtain a checking result;
and judging whether the verification result meets a preset condition, if so, finishing the adjustment of the current reference unit, and otherwise, continuously executing programming operation on the current reference unit.
8. The method of claim 7, wherein the first control signal is a first enable signal and the second control signal is a second enable signal.
9. The method of claim 7 or 8, further comprising:
receiving externally input target current;
the checking step is that the current of the current reference unit is measured, whether the measured current is smaller than the target current or not is judged, and the judgment result is used as a checking result;
the preset condition is that the check result is true.
10. The method of claim 7 or 8, further comprising:
receiving reference unit state query information from a test machine;
and outputting the adjustment state of the corresponding reference unit according to the reference unit state query information.
11. The method of claim 10, wherein the adjusting the state comprises: in operation, end of operation, and failure of operation.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0833348A1 (en) * | 1996-09-30 | 1998-04-01 | STMicroelectronics S.r.l. | Method and circuit for checking multilevel programming of floating-gate nonvolatile memory cells, particlarly flash cells |
| US20020141235A1 (en) * | 2001-03-27 | 2002-10-03 | Micron Technology, Inc. | Method and apparatus for trimming non-volatile memory cells |
| CN1898751A (en) * | 2003-10-29 | 2007-01-17 | 赛芬半导体有限公司 | Method circuit and system for read error detection in a non-volatile memory array |
| CN101088127A (en) * | 2004-12-23 | 2007-12-12 | 爱特梅尔股份有限公司 | System for performing fast testing during flash reference cell setting |
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| JP3454520B2 (en) * | 1990-11-30 | 2003-10-06 | インテル・コーポレーション | Circuit and method for checking write state of flash storage device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0833348A1 (en) * | 1996-09-30 | 1998-04-01 | STMicroelectronics S.r.l. | Method and circuit for checking multilevel programming of floating-gate nonvolatile memory cells, particlarly flash cells |
| US20020141235A1 (en) * | 2001-03-27 | 2002-10-03 | Micron Technology, Inc. | Method and apparatus for trimming non-volatile memory cells |
| CN1898751A (en) * | 2003-10-29 | 2007-01-17 | 赛芬半导体有限公司 | Method circuit and system for read error detection in a non-volatile memory array |
| CN101088127A (en) * | 2004-12-23 | 2007-12-12 | 爱特梅尔股份有限公司 | System for performing fast testing during flash reference cell setting |
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