CN102254817A - Manufacturing method for trench and manufacturing method of semiconductor device - Google Patents
Manufacturing method for trench and manufacturing method of semiconductor device Download PDFInfo
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- CN102254817A CN102254817A CN2011102186177A CN201110218617A CN102254817A CN 102254817 A CN102254817 A CN 102254817A CN 2011102186177 A CN2011102186177 A CN 2011102186177A CN 201110218617 A CN201110218617 A CN 201110218617A CN 102254817 A CN102254817 A CN 102254817A
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- trench
- fabrication methods
- photoresist
- trench fabrication
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000009271 trench method Methods 0.000 title 1
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 21
- 239000001257 hydrogen Substances 0.000 claims abstract description 21
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000137 annealing Methods 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 61
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 7
- 238000004380 ashing Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 150000002431 hydrogen Chemical class 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Abstract
The invention provides a manufacturing method for trenches and a manufacturing method of semiconductor devices. According to the invention, the manufacturing method for trenches comprises the following steps: providing a silicon substrate, growing oxides or nitrides on the silicon substrate, coating a photoresist, allowing the photoresist to form a pattern, performing trench etching by use of the photoresist mask which forms the patterns, removing the photoresist mask, washing, and performing hydrogen annealing. In the manufacturing method for trenches provided by the invention, the hydrogen annealing step is added posterior to the photoresist mask removing step, to perform chamfering treatment on the upper corner parts and lower corner parts of the trench region, so as to reduce leakage currents, improve the performances of semiconductor devices and improve the uniformity in thickness of oxide liners.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of trench fabrication methods and a kind of method, semi-conductor device manufacturing method that adopts described trench fabrication methods.
Background technology
In the semiconductor device structure design, groove is widely used in the semiconductor device structure.Groove for example may be a shallow trench isolation from (shallow trench isolation, STI).
Fig. 1 schematically shows the flow chart according to the trench fabrication methods of prior art.The trench fabrication methods of prior art shown in Figure 2 has comprised a plurality of processing steps: silicon substrate (S1) at first is provided; Grow oxide or nitride (solder joint oxide or nitride pile up deposit) be (S2) on silicon substrate subsequently; Apply photoresist (S3); Make photoresist form pattern, and utilize the photoresist that forms pattern to carry out etching groove (S4); Remove photoresist (for example ashing and wet method are peeled off) (S5); Clean (S6); Groove liner oxidation (S7) etc.
But, can be very sharp-pointed according to the angle part of the produced groove of described trench fabrication methods, and this is undesirable in a lot of semiconductor device.
Specifically, Fig. 2 schematically shows the configuration diagram of the produced groove of trench fabrication methods according to prior art shown in Figure 1.Wherein show for example structure of observed trench region after removing photoresist (S5) step.
As shown in Figure 2, all very sharp-pointed according to the upper left corner part (see and amplify diagrammatic sketch SC1) and the lower right corner part (see and amplify diagrammatic sketch SC2) of the produced groove of described trench fabrication methods, rather than round angle.And the unshowned upper left corner and lower right corner part may be sharp shape equally, can't form the round angle part.More particularly, the sharp comer on top part will cause problems such as leakage current, reliability reduction, and the sharp comer of bottom part will cause problems such as liner oxide is inhomogeneous.
Therefore, wish to propose a kind of trench fabrication methods that can eliminate the sharp comer part in the groove.
Summary of the invention
An object of the present invention is to provide and a kind ofly can eliminate the trench fabrication methods of the sharp comer part in the groove and the method, semi-conductor device manufacturing method that has adopted described trench fabrication methods.
According to first aspect present invention, a kind of trench fabrication methods is provided, it comprises: silicon substrate is provided; Grow oxide or nitride on silicon substrate; Apply photoresist; Make photoresist form pattern; Utilize the photoresist that forms pattern to carry out etching groove; Remove photoresist; Clean; And execution hydrogen annealing.
Preferably, described trench fabrication methods also comprises the step of groove liner oxidation.
Preferably, in described trench fabrication methods, the step of described removal photoresist comprises that ashing and wet method peel off.
Preferably, in described trench fabrication methods, in the process of described execution hydrogen annealing, the flow velocity of hydrogen is between between the 2SLM to 25SLM.
Preferably, in described trench fabrication methods, in the process of described execution hydrogen annealing, temperature is between 800 ℃ to 1000 ℃.
Preferably, in described trench fabrication methods, in the process of described execution hydrogen annealing, the processing time is no more than 40 seconds.
By adopting according to the described trench fabrication methods of first aspect present invention, increased and removed photoresist hydrogen annealing step afterwards, thereby upper corners part and lower angle to trench region are partly carried out the corners processing, thereby reduced leakage current and improved the performance of semiconductor device, and improved the thickness evenness of liner oxide.
According to second aspect present invention, a kind of method, semi-conductor device manufacturing method is provided, described semiconductor device has trench region, it is characterized in that method, semi-conductor device manufacturing method has adopted according to the described trench fabrication methods of first aspect present invention to make described trench region.
Owing to adopted according to the described trench fabrication methods of first aspect present invention and made described trench region; Therefore, it will be appreciated by persons skilled in the art that according to the method, semi-conductor device manufacturing method of second aspect present invention and can realize the useful technique effect that trench fabrication methods according to a first aspect of the invention can realize equally.Promptly, in method, semi-conductor device manufacturing method according to second aspect present invention, by adopting according to the described trench fabrication methods of first aspect present invention, increased and removed photoresist hydrogen annealing step afterwards, thereby upper corners part and lower angle to trench region are partly carried out the corners processing, thereby reduced leakage current and improved the performance of semiconductor device, and improved the thickness evenness of liner oxide.
Description of drawings
In conjunction with the accompanying drawings, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and feature the present invention by with reference to following detailed, wherein:
Fig. 1 schematically shows the flow chart according to the trench fabrication methods of prior art.
Fig. 2 schematically shows the configuration diagram according to the produced groove of trench fabrication methods of prior art.
Fig. 3 schematically shows the flow chart according to the trench fabrication methods of the embodiment of the invention.
Need to prove that accompanying drawing is used to illustrate the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear and understandable more, content of the present invention is described in detail below in conjunction with specific embodiments and the drawings.
Fig. 3 schematically shows the flow chart according to the trench fabrication methods of the embodiment of the invention.As shown in Figure 3, the trench fabrication methods according to the embodiment of the invention comprises:
First step S1: silicon substrate at first is provided;
Carry out the second step S2 subsequently: grow oxide or nitride on silicon substrate (solder joint oxide or nitride pile up deposit);
Third step S3: apply photoresist;
The 4th step S4: make photoresist form pattern, and utilize the photoresist that forms pattern to carry out groove (for example shallow trench isolation from) etching;
The 5th step S5: remove photoresist (for example ashing and wet method are peeled off);
The 6th step S6: clean;
The 7th step S0: carry out hydrogen annealing;
The 8th step S7: groove liner oxidation (for example shallow trench liner oxidation).
In the trench fabrication methods according to prior art shown in Figure 1, clean S6 and directly carry out groove liner oxidation step S7 afterwards.And in the trench fabrication methods according to the embodiment of the invention shown in Figure 3, clean S6 and at first carry out hydrogen annealing step S0 afterwards, carry out subsequent steps such as groove liner oxidation step S7 subsequently.
In fact, the hydrogen annealing step S0 that is added can regard one " corners processing " as.This hydrogen annealing step S0 can make upper corners part and lower corners branch corners by the migration again (re-mobilization) of silicon.
In a concrete example of the present invention, the treatment conditions of hydrogen annealing step S0 are: the flow velocity of hydrogen (H2) is between between the 2SLM to 25SLM, temperature between 800 ℃ to 1000 ℃, and the processing time be no more than 40 seconds.
By adding hydrogen annealing step S0, make the trench fabrication methods of the embodiment of the invention have following advantage at least:
1. reduce leakage current and improved the performance of semiconductor device;
2. improved the thickness evenness of liner oxide;
3. handle by flute surfaces and the termination dangling bonds, can obtain higher-quality groove liner oxide.
Further, in another embodiment of the present invention, the present invention also provides a kind of method, semi-conductor device manufacturing method that has adopted trench fabrication methods shown in Figure 3.
In addition, those skilled in the art are understandable that though with each step in the above-mentioned flow process the present invention has been described, the present invention does not get rid of the existence of other step except above-mentioned steps.Those skilled in the art are understandable that, can add other step to form other structure or to realize other purpose in described step without departing from the scope of the invention.
Be understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (8)
1. trench fabrication methods is characterized in that comprising:
Silicon substrate is provided;
Grow oxide or nitride on silicon substrate;
Apply photoresist;
Make photoresist form pattern;
Utilize the photoresist that forms pattern to carry out etching groove;
Remove photoresist;
Clean; And
Carry out hydrogen annealing.
2. trench fabrication methods according to claim 1 is characterized in that, also comprises the step of groove liner oxidation.
3. trench fabrication methods according to claim 1 and 2 is characterized in that, the step of described removal photoresist comprises that ashing and wet method peel off.
4. trench fabrication methods according to claim 1 and 2 is characterized in that, in the process of described execution hydrogen annealing, the flow velocity of hydrogen is between between the 2SLM to 25SLM.
5. trench fabrication methods according to claim 1 and 2 is characterized in that, in the process of described execution hydrogen annealing, temperature is between 800 ℃ to 1000 ℃.
6. trench fabrication methods according to claim 1 and 2 is characterized in that, in the process of described execution hydrogen annealing, the processing time is no more than 40 seconds.
7. trench fabrication methods according to claim 1 and 2 is characterized in that, described groove be shallow trench isolation from.
8. method, semi-conductor device manufacturing method, described semiconductor device has trench region, it is characterized in that method, semi-conductor device manufacturing method has adopted according to the described trench fabrication methods of one of claim 1 to 6 to make described trench region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102186177A CN102254817A (en) | 2011-08-01 | 2011-08-01 | Manufacturing method for trench and manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011102186177A CN102254817A (en) | 2011-08-01 | 2011-08-01 | Manufacturing method for trench and manufacturing method of semiconductor device |
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| CN102254817A true CN102254817A (en) | 2011-11-23 |
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| CN2011102186177A Pending CN102254817A (en) | 2011-08-01 | 2011-08-01 | Manufacturing method for trench and manufacturing method of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855070A (en) * | 2012-11-29 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for flattening shallow trench isolation of ultra-low-density active region |
| US9076668B2 (en) | 2013-03-14 | 2015-07-07 | Shanghai Huali Microelectronics Corporation | Method of manufacturing the trench of U-shape |
| CN110504156A (en) * | 2018-05-17 | 2019-11-26 | 美光科技公司 | Method for reducing silicon consumption, the method for forming semiconductor structure, and the method for forming isolation structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037238A (en) * | 1999-01-04 | 2000-03-14 | Vanguard International Semiconductor Corporation | Process to reduce defect formation occurring during shallow trench isolation formation |
| JP2001332613A (en) * | 2000-05-24 | 2001-11-30 | Nec Corp | Method for manufacturing semiconductor device |
| CN101414574A (en) * | 2007-10-16 | 2009-04-22 | 上海华虹Nec电子有限公司 | Plow groove isolation integration method |
| JP4376505B2 (en) * | 2002-10-30 | 2009-12-02 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
-
2011
- 2011-08-01 CN CN2011102186177A patent/CN102254817A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6037238A (en) * | 1999-01-04 | 2000-03-14 | Vanguard International Semiconductor Corporation | Process to reduce defect formation occurring during shallow trench isolation formation |
| JP2001332613A (en) * | 2000-05-24 | 2001-11-30 | Nec Corp | Method for manufacturing semiconductor device |
| JP4376505B2 (en) * | 2002-10-30 | 2009-12-02 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| CN101414574A (en) * | 2007-10-16 | 2009-04-22 | 上海华虹Nec电子有限公司 | Plow groove isolation integration method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855070A (en) * | 2012-11-29 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Method for flattening shallow trench isolation of ultra-low-density active region |
| US9076668B2 (en) | 2013-03-14 | 2015-07-07 | Shanghai Huali Microelectronics Corporation | Method of manufacturing the trench of U-shape |
| CN110504156A (en) * | 2018-05-17 | 2019-11-26 | 美光科技公司 | Method for reducing silicon consumption, the method for forming semiconductor structure, and the method for forming isolation structure |
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| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140430 |
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Effective date of registration: 20140430 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
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| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111123 |