CN102201818B - A kind of output intent of Turbo decode results and device - Google Patents
A kind of output intent of Turbo decode results and device Download PDFInfo
- Publication number
- CN102201818B CN102201818B CN201110122720.1A CN201110122720A CN102201818B CN 102201818 B CN102201818 B CN 102201818B CN 201110122720 A CN201110122720 A CN 201110122720A CN 102201818 B CN102201818 B CN 102201818B
- Authority
- CN
- China
- Prior art keywords
- bit
- data
- code block
- register
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
本发明提供了一种Turbo译码结果的输出方法及装置，所述方法包括：将以码块CB为单位存储的Turbo译码结果读取到并行移位寄存器中；根据所述CB的相关信息，选择并行移位寄存器的抽头位置，进行数据拼接；控制拼接结果的输出。本发明提供的一种Turbo译码结果的输出方法及装置，通过并行移位寄存器和数据拼接控制模块实现了对Turbo译码结果的并行处理，能够低成本、高效率地实现Turbo译码结果的输出，具有存储开销低、处理时延小和处理简单等特点，提高了系统处理能力，利于成本的降低。
The present invention provides a method and device for outputting a Turbo decoding result, the method comprising: reading the Turbo decoding result stored in a code block CB into a parallel shift register; according to the relevant information of the CB , select the tap position of the parallel shift register for data splicing; control the output of the splicing result. A method and device for outputting Turbo decoding results provided by the present invention realizes parallel processing of Turbo decoding results through a parallel shift register and a data splicing control module, and can realize the output of Turbo decoding results at low cost and high efficiency. The output has the characteristics of low storage overhead, small processing delay, and simple processing, which improves the system processing capability and is conducive to cost reduction.
Description
Technical Field
The present invention relates to a decoding processing technology of communication, and in particular, to a method and an apparatus for outputting a Turbo decoding result.
Background
The Turbo code skillfully concatenates two simple component codes in parallel through a pseudorandom interleaver to construct a long code with pseudorandom characteristics, and the performance of the Turbo code far exceeds that of other coding modes, so that more and more attention and development are paid. However, the Turbo decoding process is relatively complex, so in order to improve the Turbo decoding throughput, the baseband system mostly adopts a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC) to complete the Turbo decoding process.
According to The third generation partnership project (3 GPP) TS25.212 and TS25.222, when The length of a Transport Block (TB) is greater than 5114 bits, The TB needs to be segmented into Code Blocks (CBs), The size of The segmented CB may be any value between 40 bits and 5114 bits, and a dummy is usually added to The front end of The first CB to make The size of each CB completely equal. Since the size of the CB is an arbitrary value between 40 bits and 5114 bits and the number of dummy bits added is arbitrary, the size of the actual effective data of the CB is also arbitrary.
After Turbo decoding, if the data is directly output to an external storage device without processing to obtain actual valid data, when the external storage device delivers the decoding result to a Central Processing Unit (CPU) or a digital signal processing chip (DSP) for post-processing, when the CPU or the DSP uses the data, it needs to perform data access processing for the bit position of the actual valid data in the input data, which increases the processing difficulty.
Here, when the CPU or the DSP reads and writes data from and from the external storage device, the processing is performed in the minimum unit, which may be different depending on the system; wherein, the minimum unit is Word, the width w is 8, 16 or 32 respectively, and can be respectively marked as Word8, Word16 or Word 32. In view of the above, it is necessary to complete the Word splicing process of the CB when the Turbo decoding outputs the decoding result, so as to improve the processing efficiency of the overall system.
In the existing method for completing Word splicing, a common method is to set a first-in first-out (FIFO), sequentially write decoding results of each CB into the FIFO, and sequentially take out wbits from the FIFO each time according to the number of dummy bits and the size of the CB during output, thereby completing Word splicing. But the method needs FIFO, increases the storage overhead and has higher implementation cost; and the processing can be performed in series only according to bit, so that the processing delay is longer and the efficiency is lower.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a method and an apparatus for outputting a Turbo decoding result, which can realize outputting a Turbo decoding result with low cost and high efficiency.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a method for outputting Turbo decoding results, the method comprising:
reading Turbo decoding results stored by taking a code block CB as a unit into a parallel shift register;
selecting the tap position of the parallel shift register according to the relevant information of the CB, and carrying out data splicing;
and controlling the output of the splicing result.
Reading the Turbo decoding result stored by taking CB as a unit into the parallel shift register is as follows:
reading a first Word of the CB, and inputting the first Word into a first-stage register of the parallel shift register; wherein the width w of the Word is 8, 16 or 32;
and reading the next Word of the CB, inputting the next Word into a first-stage register of the parallel shift register, and simultaneously shifting the data originally stored in the first-stage register into a second-stage register of the parallel shift register in parallel.
Wherein, according to the relevant information of the CB, the tap position of the parallel shift register is selected as follows:
when the CB is the first CB of the Turbo decoding result, tap positions of the parallel shift register are selected to be bit n-bit (w-1) of a second-stage register and bit 0-bit (n-1) of a first-stage register of the parallel shift register; wherein n is the number of dummy elements of the CB;
and when the CB is not the first CB of the Turbo decoding result, obtaining the bit number m of the effective data which is not output by the last CB according to the CB index of the CB and the size of the CB, and selecting tap positions of the parallel shift register as bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
Wherein the data splicing is performed as follows: the spliced wbit data is the data stored by the bitn-bit (w-1) of the second-stage register and the bit 0-bit (n-1) of the first-stage register from the low bit to the high bit; or,
the spliced wbit data are sequentially stored by the bits (w-m) -bit (w-1) of the second-stage register and the bits 0-bit (w-m-1) of the first-stage register from the low bit to the high bit.
Further, the method further comprises:
judging whether the bit number of effective data in the spliced data is w or not;
and if the bit number of the effective data is not w, further judging whether the currently processed CB is the last CB of the Turbo decoding result.
Wherein, the output of the control splicing result is as follows:
if the bit number of the effective data in the spliced data is w, outputting the splicing result to an external cache;
if the bit number of the effective data in the spliced data is not w and the current processed CB is the last CB, supplementing 0 or 1 behind the effective data, and outputting to an external cache after sufficient bit is achieved;
and if the bit number of the effective data in the spliced data is not w and the current processed CB is not the last CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of the parallel shift register, and reading the first Word of the next CB.
An apparatus for outputting a Turbo decoding result, the apparatus comprising: the device comprises an input selection module, a parallel shift register, a data splicing control module and an output selection module; wherein,
the input selection module is used for reading the Turbo decoding result stored by taking CB as a unit into the parallel shift register;
the data splicing control module is used for selecting the tap position of the parallel shift register according to the relevant information of the CB and splicing data;
and the output selection module is used for controlling the output of the splicing result.
Further, the input selection module is specifically configured to read a first Word of the CB, and input the first Word into a first stage register of the parallel shift register; reading the next Word of the CB, inputting the next Word into the first-stage register, and simultaneously shifting the data originally stored in the first-stage register into a second-stage register of the parallel shift register in parallel; wherein the width w of the Word is 8, 16 or 32.
Further, the data splicing control module is specifically configured to select tap positions of the parallel shift register as bit n to bit (w-1) of a second-stage register and bit0 to bit (n-1) of a first-stage register of the parallel shift register when the CB is a first CB of the Turbo decoding result; wherein n is the number of dummy elements of the CB; and when the CB is not the first CB of the Turbo decoding result, obtaining the bit number m of the effective data which is not output by the last CB according to the CB index of the CB and the size of the CB, and selecting tap positions of the parallel shift register as bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
Further, the wbit data spliced by the data splicing control module are data stored by the bits n-bit (w-1) of the second-stage register and the bits 0-bit (n-1) of the first-stage register from the low bit to the high bit in sequence; or sequentially storing data of bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
Further, the data splicing control module is further configured to determine whether a bit number of valid data in the spliced data is w; and if the bit number of the effective data is not w, further judging whether the currently processed CB is the last CB of the Turbo decoding result.
Further, the output selection module is specifically configured to output the splicing result to an external cache if the number of bits of valid data in the data obtained by splicing is w; if the bit number of the effective data in the spliced data is not w and the current processed CB is the last CB, supplementing 0 or 1 behind the effective data, and outputting to an external cache after sufficient bit is achieved; and if the bit number of the effective data in the spliced data is not w and the current processed CB is not the last CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of the parallel shift register, and reading the first Word of the next CB.
The method and the device for outputting the Turbo decoding result realize the parallel processing of the Turbo decoding result through the parallel shift register and the data splicing control module, thus realizing the output of the Turbo decoding result with low cost and high efficiency, having the characteristics of low storage overhead, small processing time delay, simple processing and the like, further improving the system processing capacity and being beneficial to reducing the cost.
Drawings
FIG. 1 is a schematic diagram illustrating an implementation process of a Turbo decoding result output method according to the present invention;
FIG. 2 is a schematic diagram of an internal buffer format and an expected external buffer format of a Turbo decoding result in an embodiment of a method for outputting a Turbo decoding result according to the present invention;
FIG. 3 is a flowchart illustrating an implementation of a method for outputting a Turbo decoding result shown in FIG. 2 according to an embodiment;
FIG. 4 is a diagram illustrating a register input of a first Word of a first CB in the Turbo decoding result shown in FIG. 2;
FIG. 5 is a diagram illustrating the second Word input of the first CB into the register of the Turbo decoding result shown in FIG. 2;
FIG. 6 is a diagram illustrating the last Word input of the first CB in the Turbo decoding result shown in FIG. 2;
FIG. 7 is a diagram illustrating a register for write-back processing of the last Word of the first CB in the Turbo decoding result shown in FIG. 2;
FIG. 8 is a diagram illustrating the input of the first Word of the second CB into the register of the Turbo decoding result shown in FIG. 2;
FIG. 9 is a schematic diagram of a system structure using the Turbo decoding result output device of the present invention;
FIG. 10 is a schematic structural diagram of a Turbo decoding result output device according to the present invention.
Detailed Description
The basic idea of the invention is as follows: reading Turbo decoding results stored by taking a code block CB as a unit into a parallel shift register; selecting the tap position of the parallel shift register according to the relevant information of the CB, and carrying out data splicing; controlling the output of the splicing result; the information related to the CB may be one or more of the number of dummy bits of the CB, a CB index, and a CB size.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings by way of examples.
Fig. 1 shows an implementation process of the Turbo decoding result output method of the present invention, and as shown in fig. 1, the method includes the following steps:
step 101, reading a Turbo decoding result stored by taking CB as a unit into a parallel shift register;
in this step, the parallel shift register may be 8bit, 16bit, 32bit parallel shift register; specifically, a first Word of a CB of the Turbo decoding result is read from an internal cache in which the Turbo decoding result is stored, the first Word is input into a first-stage register of the parallel shift register, then the next Word is read and input into a first-stage register of the parallel shift register, and data originally stored in the first-stage register is shifted into a second-stage register in parallel; wherein, the width w of the Word can be 8, 16 or 32, which is respectively marked as Word8, Word16 or Word 32;
102, selecting a tap position of a parallel shift register according to the related information of the CB, and carrying out data splicing;
specifically, in this step, the tap position may be selected according to one or more of parameters such as the dummy number of the CB, the CB index, and the CB size; when the CB is the first CB of the Turbo decoding result, tap positions of the parallel shift register are selected to be bit n-bit (w-1) of a second-stage register and bit 0-bit (n-1) of a first-stage register of the parallel shift register; wherein n is the number of dummy elements;
when the CB is not the first CB of the Turbo decoding result, obtaining the bit number m of effective data which is not output by the last CB according to the CB index and the size of the CB, and selecting tap positions of a parallel shift register as bit (w-m) -bit (w-1) of a second-stage register and bit 0-bit (w-m-1) of a first-stage register; wherein: the spliced wbit data is the data stored by the bitn-bit (w-1) of the second-stage register and the bit 0-bit (n-1) of the first-stage register from the low bit to the high bit; or sequentially storing data of bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
Specifically, when w is 8, when the CB is the first CB of the Turbo decoding result, dummy bits may need to be filled to ensure that the length of each CB of the Turbo decoding result is the same; for example, when the number of the dummy bits of the first CB is 2, and when the first 8-bit data of the CB has been input to the second stage register of the parallel shift register, and the second 8-bit data of the CB has been input to the first stage register, the data stored in the first two bits of the second stage register is the dummy bits filled above, and is not valid data of the Turbo decoding result, and therefore, the tap position of the parallel shift register to be selected is the tap of the last six bits of the second stage register and the tap of the first two bits of the first stage register, and 8-bit data is obtained by splicing.
103, controlling the output of the splicing result;
here, the wbit data obtained by the splicing is output to an external cache and the like, and then the steps are repeated until the last group of data of one CB is obtained, and as the size of the CB is not necessarily integral multiple of w, the last group of data can also contain invalid data;
specifically, the method further comprises the following steps: judging whether the bit number of effective data in the spliced data is w or not; if the bit number of the effective data is not w, further judging whether the currently processed CB is the last CB of the Turbo decoding result;
correspondingly, if the bit number of the effective data in the spliced data is w, outputting the splicing result to an external cache;
if the bit number of the effective data in the spliced data is not w and the currently processed CB is the last CB, supplementing 0 or 1 behind the effective data, outputting the effective data to an external cache after the effective data is fully bit-matched, and the like;
if the bit number of the effective data in the spliced data is not w and the current processed CB is not the last CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of a parallel shift register, and then reading the first Word of the next CB; specifically, after the write-back is performed to the first-stage register, at this time, the wbit data obtained by splicing in step 102 are all invalid data, and the wbit data are discarded, and then step 101 is repeated to read the first Word of the next CB.
Fig. 2 shows an internal buffer format and an expected external buffer format of a Turbo decoding result in a specific embodiment of the method for outputting a Turbo decoding result of the present invention, and for convenience of description, it is assumed that the maximum length of a CB in 3GPP is 64 bits, and the length of a currently processed TB is 154 bits, and it is assumed that a DSP/CPU system adopts a Word width w of 8, that is, Word8 is adopted. According to the CB separation algorithm, the total number of the CBs obtained by dividing is 3, the length of each CB is 52 bits, the filled dummy is 2 bits, under the conditions, after Turbo decoding is finished, the internal cache formats of the three CBs are shown as the left side of an arrow in figure 2, and the expected external cache format of the Turbo decoding result is shown as the right side of the arrow in figure 2; three rectangular boxes shown on the left side of the arrow in fig. 2 are hard decision results of a first CB, a second CB, and a third CB in sequence; in the hard decision result of the first CB, the first two bits of the first 8-bit data are filled dummy bits, and the last four bits of each CB are filled invalid data; the expected external cache format shown to the right of the arrow is the concatenation result after the invalid data is removed by the CB on the left.
FIG. 3 is a flowchart illustrating an implementation of a method for outputting the Turbo decoding result shown in FIG. 2 according to an embodiment, where in this embodiment, the width w of Word is 8; as shown in fig. 3, the embodiment comprises the following steps:
step 301, reading a first Word of a first CB, and storing the first Word into a first-stage register of a parallel shift register;
specifically, as shown in fig. 4, the first 8-bit data read from the first CB is stored in the first stage register of the parallel shift register, and at this time, the second stage register of the parallel shift register has not stored any data yet.
Step 302, reading the second Word of the CB, storing the second Word into the first-stage register of the parallel shift register, and shifting the data cached in the original first-stage register into the second-stage register at the moment;
specifically, as shown in fig. 5, the second 8-bit data of the first CB is read and input into the first stage register of the parallel shift register, and the data originally stored in the first stage register is shifted in parallel to the second stage register.
303, selecting tap positions of a first-stage register and a second-stage register according to related information of the CB, such as parameters of dummy number, CB index, CB size and the like, and performing data splicing;
specifically, referring to fig. 5, since the data in the positions bit0 and bit1 of the second level register are filled with dummy bits, the selected tap positions are bit2 to bit7 of the second level register and bit0 to bit1 of the first level register, so as to perform data splicing.
Step 304, outputting the spliced 8-bit data to an external cache and the like;
specifically, the spliced output data sequentially comprises bits 2 to 7 of the second-stage register and then bits 0 to 1 of the first-stage register from the low bit to the high bit.
Step 305, reading the next Word of the CB and storing the next Word into the first-level register of the parallel shift register, at this time, shifting the data cached in the original first-level register into the second-level register, and judging whether the number of bits of valid data in the Word obtained by splicing according to the tap position in the step is 8, if so, executing step 304, and if not, executing step 306;
specifically, the number of bits of valid data in the last Word of the first CB is 4, but less than 8 bits, referring to fig. 6, when the last Word is input into the first-stage register, the number of bits of valid data in the words obtained by splicing at this time is still 8, so step 304 is executed, 8-bit data obtained by splicing is output to an external cache, and then the step is repeatedly executed;
it should be noted that, at this time, the next Word of the Turbo decoding result is not read, but a random 8-bit data is stored in the first-stage register, and meanwhile, the data in the original first-stage register is shifted to the second-stage register in parallel, specifically referring to fig. 7, at this time, the 8-bit data obtained by splicing contains 2-bit valid data, so step 306 is executed.
Step 306, judging whether the currently processed CB is the last CB of the Turbo decoding result, if so, executing step 304, specifically, supplementing 0 or 1 to the back of less than 8-bit effective data, and outputting to an external cache after completing 8 bits; if not, go to step 307;
specifically, referring to fig. 7, the currently processed CB is not the last CB of the Turbo decoding result, so step 307 is performed.
307, moving the valid data in the spliced 8-bit data to the right end, writing the valid data back into a first-stage register, and shifting the data cached in the original first-stage register to a second-stage register;
specifically, referring to fig. 7, the valid data in the 8-bit data obtained by splicing in step 305 is shifted, right-shifted to the rightmost end, and written back to the first-stage register after being complemented to 8 bits by random data.
308, reading the first Word of the next CB, storing the first Word in a first-stage register, shifting 8-bit data containing effective data in the original first-stage register into a second-stage register, executing 303, re-determining the position of a tap, and splicing data;
specifically, referring to fig. 8, after the first Word of the second CB is stored in the first stage register, the positions of bits 6-bit 7 in the second stage register are 2 valid data that are not output by the first CB, and therefore, the determined tap positions are bits 6-7 of the second stage register and bits 0-5 of the first stage register, and then the above steps are repeated until the desired Turbo decoding result in the external buffer format is obtained as shown on the right side of the arrow in fig. 2.
Fig. 9 shows a schematic system structure of the Turbo decoding result output device of the present invention, and as shown in fig. 9, the output device may be built in a Turbo decoding processing unit of ASIC/FPGA, which reads the Turbo decoding result from an internal buffer, outputs the Turbo decoding result to an external storage after being processed by the output device, and then provides the Turbo decoding result to a CPU/DSP for use.
FIG. 10 shows a schematic structure of a Turbo decoding result output device of the present invention, and as shown in FIG. 10, the output device includes an input selection module, a parallel shift register, a data splicing control module, and an output selection module; the input selection module is used for reading a Turbo decoding result stored by taking CB as a unit into the parallel shift register; the data splicing control module is used for selecting the tap position of the parallel shift register according to the relevant information of the CB and splicing data; and the output selection module is used for controlling the output of the splicing result.
Further, the parallel shift register comprises a first stage register and a second stage register.
Further, the input selection module is specifically configured to read a first Word of the CB, and input the first Word into a first stage register of the parallel shift register; reading the next Word of the CB, inputting the next Word into the first-stage register, and simultaneously shifting the data originally stored in the first-stage register into a second-stage register of the parallel shift register in parallel; wherein the width w of Word is 8, 16 or 32, and is respectively marked as Word8, Word16 or Word 32.
Further, the data splicing control module is specifically configured to select tap positions of the parallel shift register as bit n to bit (w-1) of a second-stage register and bit0 to bit (n-1) of a first-stage register of the parallel shift register when the CB is a first CB of the Turbo decoding result; wherein n is the number of dummy elements of the CB; and when the CB is not the first CB of the Turbo decoding result, obtaining the bit number m of the effective data which is not output by the last CB according to the CB index of the CB and the size of the CB, and selecting tap positions of the parallel shift register as bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
The wbit data spliced by the data splicing control module are data stored by the bits n-bit (w-1) of the second-stage register and the bits 0-bit (n-1) of the first-stage register from low bits to high bits in sequence; or sequentially storing data of bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
Further, the data splicing control module is further configured to determine whether a bit number of valid data in the spliced data is w; and if the bit number of the effective data is not w, further judging whether the currently processed CB is the last CB of the Turbo decoding result.
Further, the output selection module is specifically configured to output the splicing result to an external cache if the number of bits of valid data in the data obtained by splicing is w; if the bit number of the effective data in the spliced data is not w and the current processed CB is the last CB, supplementing 0 or 1 behind the effective data, and outputting to an external cache after sufficient bit is achieved; and if the bit number of the effective data in the spliced data is not w and the current processed CB is not the last CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of the parallel shift register, and reading the first Word of the next CB.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (10)
1. A method for outputting Turbo decoding results is characterized by comprising the following steps:
reading Turbo decoding results stored by taking a code block CB as a unit into a parallel shift register;
selecting a tap position of the parallel shift register according to the relevant information of the code block CB, and carrying out data splicing;
controlling the output of the splicing result;
the output of the control splicing result is as follows:
if the bit number of the effective data in the spliced data is w, outputting the splicing result to an external cache;
if the bit number of the effective data in the spliced data is not w and the current processed CB is the last CB, supplementing 0 or 1 behind the effective data, and outputting to an external cache after sufficient bit is achieved;
if the bit number of the effective data in the spliced data is not w and the current processed CB is not the last CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of a parallel shift register, and then reading the first Word of the next CB;
where the width w of Word is 8, 16 or 32.
2. The method according to claim 1, wherein the reading the Turbo decoding results stored in units of code blocks CB into the parallel shift register is:
reading a first Word of the code block CB and inputting the first Word into a first-stage register of the parallel shift register; wherein the width w of the Word is 8, 16 or 32;
and reading the next Word of the code block CB, inputting the next Word into a first-stage register of the parallel shift register, and simultaneously, parallelly shifting the data originally stored in the first-stage register into a second-stage register of the parallel shift register.
3. The method according to claim 1 or 2, wherein the selecting tap positions of the parallel shift register according to the information about the CB is:
when the CB is a first code block CB of a Turbo decoding result, tap positions of the parallel shift register are selected to be bit n-bit (w-1) of a second-stage register and bit 0-bit (n-1) of a first-stage register of the parallel shift register; wherein n is the number of dummy elements of the CB;
and when the CB is not the first CB of the Turbo decoding result, obtaining the bit number m of the effective data which is not output by the last CB according to the CB index of the CB and the size of the CB, and selecting tap positions of the parallel shift register as bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register.
4. The method of claim 3, wherein the performing data splicing is: the spliced wbit data is the data stored by the bitn-bit (w-1) of the second-stage register and the bit 0-bit (n-1) of the first-stage register from the low bit to the high bit; or,
the spliced wbit data are sequentially the data stored by the bits (w-m) -bit (w-1) of the second-stage register and the bits 0-bit (w-m-1) of the first-stage register from the low bit to the high bit;
where the width w of Word is 8, 16 or 32.
5. The method of claim 1, further comprising:
judging whether the bit number of effective data in the spliced data is w or not;
if the bit number of the effective data is not w, further judging whether the current processed code block CB is the last code block CB of the Turbo decoding result;
where the width w of Word is 8, 16 or 32.
6. An apparatus for outputting a Turbo decoding result, the apparatus comprising: the device comprises an input selection module, a parallel shift register, a data splicing control module and an output selection module; wherein,
the input selection module is used for reading Turbo decoding results stored by taking a code block CB as a unit into the parallel shift register;
the data splicing control module is used for selecting the tap position of the parallel shift register according to the relevant information of the code block CB to splice data;
the output selection module is used for controlling the output of the splicing result;
the output selection module is specifically configured to output the splicing result to an external cache if the number of bits of valid data in the spliced data is w; if the bit number of the effective data in the spliced data is not w and the currently processed code block CB is the last code block CB, supplementing 0 or 1 behind the effective data, and outputting the effective data to an external cache after the effective data is fully bit-matched; if the bit number of the effective data in the spliced data is not w and the currently processed code block CB is not the last code block CB, moving the spliced data, right-moving the effective data to the rightmost end, writing the effective data back to a first-stage register of a parallel shift register, and reading the first Word of the next code block CB;
where the width w of Word is 8, 16 or 32.
7. The apparatus according to claim 6, wherein the input selection module, specifically for reading the first Word of the code block CB, is input into a first stage register of the parallel shift register; reading the next Word of the code block CB, inputting the next Word into the first-stage register, and simultaneously shifting the data originally stored in the first-stage register into a second-stage register of the parallel shift register in parallel; wherein the width w of the Word is 8, 16 or 32.
8. The apparatus according to claim 6 or 7, wherein the data splicing control module is specifically configured to select tap positions of the parallel shift register as bit n-bit (w-1) of the second stage register and bit 0-bit (n-1) of the first stage register of the parallel shift register when the code block CB is a first code block CB of a Turbo decoding result; wherein n is the dummy number of the code block CB; when the code block CB is not the first code block CB of the Turbo decoding result, obtaining the bit number m of effective data which is not output by the previous code block CB according to the code block CB index of the code block CB and the code block CB size, and selecting tap positions of the parallel shift register as bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register;
where the width w of Word is 8, 16 or 32.
9. The device according to claim 8, wherein the wbit data spliced by the data splicing control module are data stored by the bits n-bit (w-1) of the second stage register and the bits 0-bit (n-1) of the first stage register in sequence from the low bit to the high bit; or sequentially storing data of bit (w-m) -bit (w-1) of the second-stage register and bit 0-bit (w-m-1) of the first-stage register;
where the width w of Word is 8, 16 or 32.
10. The apparatus according to claim 6, wherein the data splicing control module is further configured to determine whether a bit number of valid data in the spliced data is w; if the bit number of the effective data is not w, further judging whether the current processed code block CB is the last code block CB of the Turbo decoding result;
where the width w of Word is 8, 16 or 32.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122720.1A CN102201818B (en) | 2011-05-12 | 2011-05-12 | A kind of output intent of Turbo decode results and device |
| PCT/CN2011/081264 WO2012151864A1 (en) | 2011-05-12 | 2011-10-25 | Outputting method and device for result of turbo coding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110122720.1A CN102201818B (en) | 2011-05-12 | 2011-05-12 | A kind of output intent of Turbo decode results and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102201818A CN102201818A (en) | 2011-09-28 |
| CN102201818B true CN102201818B (en) | 2015-12-16 |
Family
ID=44662243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110122720.1A Withdrawn - After Issue CN102201818B (en) | 2011-05-12 | 2011-05-12 | A kind of output intent of Turbo decode results and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN102201818B (en) |
| WO (1) | WO2012151864A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201818B (en) * | 2011-05-12 | 2015-12-16 | 中兴通讯股份有限公司 | A kind of output intent of Turbo decode results and device |
| CN103475451A (en) * | 2013-09-10 | 2013-12-25 | 江苏中科梦兰电子科技有限公司 | Datagram network transmission method suitable for forward error correction and encryption application |
| CN104702294B (en) * | 2015-03-26 | 2018-04-27 | 北京思朗科技有限责任公司 | A kind of asymmetric imitate of bit wide of Turbo decoders deposits interface |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101164242A (en) * | 2005-03-11 | 2008-04-16 | 高通股份有限公司 | Parallel TURBO decoder with multiplexed output |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for parallel encoding of low density check code LDPC |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5789363A (en) * | 1980-11-25 | 1982-06-03 | Matsushita Electric Ind Co Ltd | Digital demodulating system |
| US20090287980A1 (en) * | 2008-05-16 | 2009-11-19 | Lsi Corporation | Computational Architecture for Soft Decoding |
| CN102201818B (en) * | 2011-05-12 | 2015-12-16 | 中兴通讯股份有限公司 | A kind of output intent of Turbo decode results and device |
-
2011
- 2011-05-12 CN CN201110122720.1A patent/CN102201818B/en not_active Withdrawn - After Issue
- 2011-10-25 WO PCT/CN2011/081264 patent/WO2012151864A1/en not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101164242A (en) * | 2005-03-11 | 2008-04-16 | 高通股份有限公司 | Parallel TURBO decoder with multiplexed output |
| CN101192833A (en) * | 2006-11-28 | 2008-06-04 | 华为技术有限公司 | A device and method for parallel encoding of low density check code LDPC |
| CN101957743A (en) * | 2010-10-12 | 2011-01-26 | 中国电子科技集团公司第三十八研究所 | Parallel digital signal processor |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012151864A1 (en) | 2012-11-15 |
| CN102201818A (en) | 2011-09-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105049061B (en) | Based on the higher-dimension base stage code decoder and polarization code coding method calculated in advance | |
| RU2009120617A (en) | TURBOCHARGER FOR HIGH DATA TRANSMISSION SPEEDS | |
| CN103427850B (en) | Multimode Veterbi decoding device and its coding/decoding method | |
| KR20150047547A (en) | Systems and methods of data extraction in a vector processor | |
| US9502104B2 (en) | Multi-level cell (MLC) non-volatile memory data reading method and apparatus | |
| US20120066566A1 (en) | Accessing memory during parallel turbo decoding | |
| US8638244B2 (en) | Encoding module, apparatus and method for determining a position of a data bit within an interleaved data stream | |
| CN102201818B (en) | A kind of output intent of Turbo decode results and device | |
| CN113222129A (en) | Convolution operation processing unit and system based on multi-level cache cyclic utilization | |
| CN106502922A (en) | A kind of data read-write method of data fifo buffer and data buffer | |
| CN101674161B (en) | Rate de-matching method and device | |
| CN105607888A (en) | Data bit width conversion method and device | |
| WO2019137231A1 (en) | Decoding method and device | |
| CN103986557B (en) | The parallel block-wise decoding method of LTE Turbo codes in low path delay | |
| WO2021143634A1 (en) | Arithmetic coder, method for implementing arithmetic coding, and image coding method | |
| CN105933090B (en) | A Multi-core Parallel SCMA Decoding System | |
| CN102184214A (en) | Data grouping quick search positioning mode | |
| JP2011141914A (en) | Input/output control method and device of nand type flash memory | |
| CN101895374B (en) | Method and device for velocity matching | |
| US20210082082A1 (en) | Data processing method and processing circuit | |
| WO2012149741A1 (en) | De-interleaving method and device for rate de-matching | |
| CN102751994B (en) | Short code length block code decoder device based on two finite group symbols | |
| CN112181356B (en) | Design method and device of configurable MIMO FIFO | |
| US9467199B1 (en) | Compression using mu-law approximation | |
| CN101145789B (en) | High-speed Viterbi decoder survivor path management module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201106 Address after: No.8, wisdom Avenue, Donghu scenic area, Dayu Town, Rudong County, Nantong City, Jiangsu Province, 226000 Patentee after: Nantong Donghu International Travel Agency Co.,Ltd. Address before: 518057 Nanshan District Guangdong high tech Industrial Park, South Road, science and technology, ZTE building, Ministry of Justice Patentee before: ZTE Corp. |
|
| TR01 | Transfer of patent right | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20151216 Effective date of abandoning: 20250923 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20151216 Effective date of abandoning: 20250923 |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |