CN102200940A - HDD (Hard Disk Driver) backboard testing system - Google Patents

Abstract

The invention provides a HDD backboard test system, which includes a PC communication interface module, a microprocessor module, an SGPIO communication interface module and an SGPIO bus; one end of the PC communication interface module is connected with the microprocessor module, and the other end receives the PC host The test signal sent; the microprocessor module converts the received test signal into an SGPIO signal according to the SGPIO communication protocol; one end of the SGPIO communication interface module is connected to the microprocessor module, and the other end outputs the SGPIO signal to the SGPIO bus; the SGPIO bus is connected to Between the SGPIO communication interface module and the HDD backplane; the SGPIO signal is transmitted to the HDD backplane through the SGPIO bus to test the HDD backplane. The microprocessor module converts the received test signal into SGPIO signal, so that the host PC can directly test the HDD backplane, effectively reducing the test cost.

Description

HDD Backplane Test System

technical field

The invention relates to a test system, in particular to a HDD (Hard Disk Driver) backplane test system.

Background technique

The SGPIO (Serial General Purpose Input/Output) bus is a serial bus interface for communication between the HBA (Host BUS Adapter) card and the HDD backplane in the computer server, and is usually used to transmit the working status of the hard disk connected to the HDD backplane indication signal. In the production of server products, it is necessary to test the relevant functions of the HDD backplane to determine whether the HDD backplane is in a normal working state.

The HDD backplane test can be divided into two parts: one part is to test the data communication function of all HDD hard disks assembled on the HDD backplane. This part of the test can be connected to a more expensive servo system or passed Connect to any other interface card that can provide the corresponding HDD signal, or use a relatively cheap common PC motherboard to test; however, another part of the HDD backplane test, that is, the functional test of the hard disk status light on the HDD backplane, is It is impossible to test with a common PC motherboard, because these lights are controlled by SGPIO signals. Since the SGPIO signal sent by the external HBA card or control chip to the HDD backplane cannot be directly obtained from the ordinary PC motherboard, this signal is only available for the corresponding servo system HBA card or control chip, so the previous HDD backplane function For testing, it can only be tested by connecting it to the servo system where it is located or its compatible servo system, so the test cost is much higher than the test cost with a common PC host.

Contents of the invention

In view of this, it is necessary to provide a HDD backplane test system with low test cost.

A HDD backplane test system, which is used to test the HDD backplane; said HDD backplane test system includes a PC communication interface module, a microprocessor module, a SGPIO communication interface module and a SGPIO bus; said One end of the PC communication interface module is connected with the microprocessor module, and the other end receives a test signal sent by a PC host; the microprocessor module converts the received test signal into an SGPIO signal according to the communication protocol of SGPIO; One end of the SGPIO communication interface module is connected with the microprocessor module, and the other end outputs the SGPIO signal to the SGPIO bus; the SGPIO bus is connected between the SGPIO communication interface module and the HDD backplane; the SGPIO signal passes through the SGPIO bus Send to the HDD backplane to test the HDD backplane.

The microprocessor module provided by the present invention converts the signal received from the PC communication interface module into an SGPIO signal, so that the common PC host connected to the PC communication interface module can directly test the HDD backplane, effectively reducing the HDD backplane. cost of testing.

Description of drawings

FIG. 1 is a schematic diagram of functional modules of an HDD backplane testing system provided by an embodiment of the present invention.

FIG. 2 is a circuit diagram of the HDD backplane testing system in FIG. 1 .

Description of main component symbols

HDD Backplane Test System 100

HDD backplane v 110

LED lights 111

PC host 120

PC communication interface module 10

USB interface 11

UART interface 12

Microprocessor module 20

Memory 21

Controller 22

Processor 23

SGPIO communication interface module 30

SGPIO bus 40

Microcontroller chip U1

Interface chip U3

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 1 and FIG. 2 , an HDD backplane testing system 100 provided in an embodiment of the present invention is used for testing an HDD backplane 110 . The HDD backplane testing system 100 includes a PC communication interface module 10 , a microprocessor module 20 , a SGPIO communication interface module 30 and a SGPIO bus 40 .

The PC communication interface module 10 is used for connecting with a PC host 120 and receiving the test signal sent by the PC host 120 . The PC communication interface module 10 includes a USB (Universal Serial Bus) interface 11 and a UART (Universal Asynchronous Receiver/Transmitter) interface 12. The USB interface 11 and the UART interface 12 are interfaces of two different signal transmission protocols. The USB interface 11 includes a DATA- terminal and a DATA+ terminal connected to the microprocessor module 20 . Described UART interface 12 is a serial interface, and it comprises an interface chip U3 and a COM1 interface, and described interface chip U3 is connected with COM1 interface, and described interface chip U3 comprises a ROUT1 that is connected with microprocessor module 20 terminal and a DIN1 terminal. It can be understood that the PC communication interface module 10 may also include other interfaces to match the interface of the host PC 120 for outputting test signals.

The microprocessor module 20 includes a micro-control chip U1 and auxiliary circuits connected to the micro-control chip U1 ; the micro-control chip U1 includes at least a memory 21 , a controller 22 and a processor 23 . The memory 21 stores multiple signal format conversion modes, for example, a conversion mode for converting USB signals into SGPIO signals and a conversion protocol for converting UART signals into SGPIO signals. After the microcontroller chip U1 receives the test signal, the controller 22 controls the processor 23 to unpack the test signal, and then converts the received test signal into an SGPIO signal according to the SGPIO communication protocol. The micro-control chip U1 includes a terminal RB0, a terminal RB1, a terminal RB2, a terminal RD7, and terminals RC4-RC7. The DATA- and DATA+ of the USB interface 11 are respectively connected to the RC4 terminal and the RC5 terminal of the microcontroller chip U1. The ROUT1 terminal and the DIN1 terminal of the interface chip U3 are connected to the RC6 terminal and the RC7 terminal of the micro-control chip U1 respectively.

Described SGPIO communication interface module 30 is a J1 interface, and described J1 interface comprises the first to the fifth end, and described first to the fourth end are respectively connected with the RB1 end, RB2 end, RB0 end and the described micro-control chip U1 RD7 terminals are connected, and the fifth terminal is grounded.

The SGPIO bus 40 is a serial bus connected between the HBA (Host BUS Adapter) card and the HDD backplane 110 in the computer server, and is usually used to transmit the indication signal of the working state of the hard disk connected to the HDD backplane 110 . The SGPIO bus 40 can only transmit signals of the SGPIO protocol.

The HDD backplane 110 includes a J2 interface corresponding to the J1 interface, a plurality of J3 interfaces for installing HDD hard disks, and each HDD hard disk J3 interface is correspondingly provided with three LED lights 111, and the The three LED lamps 111 respectively display the states of being in use, being searched and being failed. The SGPIO bus 40 is connected between the J1 interface and the J2 interface, and is used to transmit the SGPIO signal output by the microprocessor module 20 to the HDD backplane 110 .

Before the test, the HDD backplane 110 is connected to one end of the SGPIO bus 40, and the PC host 120 is connected to the microprocessor module 20 through the USB interface 11 or the UART interface 12. In the present embodiment, the USB interface is selected. 11 is connected with microprocessor module 20. The PC host 120 sends a test signal to the microprocessor module 20, the test signal meets the USB signal transmission protocol, and the test signal is transmitted from the DATA- and DATA+ of the USB interface 11 to the RC4 end and the RC5 end of the micro-control chip U1; It can be understood that when the PC host 120 needs to send a test signal to the microprocessor module 20 through the UART interface 12, the test signal meets the serial signal transmission protocol. The microprocessor module 20 first unpacks the received test signal, and then converts the test signal into an SGPIO signal according to the SGPIO communication protocol, and the SGPIO signal is transmitted from the RB0 end and the RD7 end of the micro-control chip U1 to The third end and the fourth end of the J1 interface; then, the SGPIO signal is transmitted to the HDD backplane 110 through the SGPIO bus 40, and the plurality of LED lights 111 display the test result according to the test signal. After the display state of the LED lights 111 is fed back to the microprocessor module 20, the display state of each LED light 111 is compared with the test signal, and if the display state corresponds to the test signal, it means that the HDD backplane 110 is qualified; Otherwise, it is not qualified. It can be understood that the display state of the LED lamp 111 can also be observed manually, and the observation result can be manually compared with the test signal.

The microprocessor module provided by the present invention converts the signal received from the PC communication interface module into an SGPIO signal, so that the common PC host connected to the PC communication interface module can directly test the HDD backplane, effectively reducing the HDD backplane. cost of testing.

It can be understood that, for those skilled in the art, various other corresponding changes and deformations can be made according to the technical concept of the present invention, and all these changes and deformations should belong to the protection scope of the claims of the present invention .

Claims (7)

1. HDD rear-panel testing system, it is used for the HDD backboard is tested; Described HDD rear-panel testing system comprises a PC communication interface modules, a microprocessor module, a SGPIO communication interface modules and a SGPIO bus; One end of described PC communication interface modules is connected with microprocessor module, and the other end receives the test signal that a PC main frame is sent; Described microprocessor module becomes the SGPIO signal with the test signal of described reception according to the communication Protocol Conversion of SGPIO; One end of described SGPIO communication interface modules is connected with microprocessor module, and the other end is to SGPIO bus output SGPIO signal; Described SGPIO bus is connected between SGPIO communication interface modules and the described HDD backboard; Described SGPIO signal is sent to the HDD backboard through the SGPIO bus, so that the HDD backboard is tested.

2. HDD rear-panel testing system as claimed in claim 1 is characterized in that: described PC communication interface modules comprises a USB interface and a UART interface.

3. HDD rear-panel testing system as claimed in claim 2 is characterized in that: described microprocessor module is a microcontroller chip, and described USB interface is connected with described microcontroller chip respectively with the UART interface.

4. HDD rear-panel testing system as claimed in claim 3 is characterized in that: described UART interface comprises the COM1 interface that an interface chip and is connected with interface chip, and described interface chip is connected with described microcontroller chip.

5. HDD rear-panel testing system as claimed in claim 1 is characterized in that: described microprocessor module is before being converted into the SGPIO signal with test signal, and described microprocessor is unpacked to the test signal that is received.

6. HDD rear-panel testing system as claimed in claim 1 is characterized in that: described HDD backboard is provided with a plurality of LED lamps, described LED lamp according to test signal to show test results.

7. HDD rear-panel testing system as claimed in claim 6 is characterized in that: if the show state of LED lamp is corresponding with test signal, illustrate that then the HDD backboard is qualified; Otherwise, then defective.

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