CN102208813A - Artificial Neutral Point (ANP) power factor correction circuit - Google Patents

Abstract

The invention discloses a virtual neutral line power factor correction circuit, which comprises: an AC output module outputs at least two-phase AC voltage; the virtual neutral line module receives the AC voltage output by the AC output module, generates a virtual neutral line, and provides a common voltage for the power factor correction module Midpoint; power factor correction module, including several identical power factor correction units; each power factor correction unit is respectively connected to one-phase AC voltage output by the AC output module, and performs step-down and power conversion on the received single-phase AC voltage Factor correction: the midpoints of each power factor correction unit are short-circuited, as the common midpoint of the power factor correction module, and connected to the output end of the virtual neutral line module. By adopting the present invention, a virtual neutral line can be constructed without increasing the front-end power frequency transformer, so that the circuit can adapt to the fluctuation of the power grid, and at the same time, it can well suppress the influence of the unbalanced phase voltage of the power grid, and has a strong power grid adaptability.

Description

A Virtual Neutral Power Factor Correction Circuit

technical field

The invention relates to the technical field of power factor correction, in particular to a virtual neutral line power factor correction circuit.

Background technique

Using high-voltage DC UPS (Uninterruptible Power Supply, uninterruptible power supply) to replace the traditional AC UPS can significantly improve the efficiency and reliability of the entire system, while reducing the cost of the system, so it has a bright market prospect.

At this stage, the buck+boost circuit is generally used to realize step-up/step-down. The buck+boost circuit has a good power factor correction function, and can realize free parallel connection at the same time, and has been widely used in the field of high-voltage DC UPS.

However, for the application of this buck+boost circuit on high-voltage DC UPS, there is a typical technical problem: the grid needs to provide a neutral line to achieve better power factor correction and parallel connection.

In the prior art, there are mainly two ways to solve the above problems.

The first one: add a power frequency transformer to the front end of the high-voltage DC UPS to generate a neutral line. However, this solution needs to add an additional high-power power frequency transformer, which increases the equipment cost and occupies the equipment space.

The second method: inside the high-voltage DC UPS, add a virtual neutral line through a capacitor. This scheme can save the bulky power frequency transformer, and only needs to increase the cost of a small capacitor. However, this solution also has a serious disadvantage: it can operate normally when the grid fluctuations are small and the phase voltages of the grid are balanced; but when the grid fluctuations are large and the phase voltages are unbalanced, normal operation cannot be guaranteed. Therefore, the ability of this scheme to adapt to the grid is very weak.

Contents of the invention

In view of this, the purpose of the present invention is to provide a virtual neutral line power factor correction circuit, which can construct a virtual neutral line without increasing the power frequency transformer at the front end, so that the circuit can adapt to the fluctuation of the power grid, and at the same time can be easily It can well suppress the influence of grid phase voltage imbalance and has strong grid adaptability.

An embodiment of the present invention provides a virtual neutral line power factor correction circuit, the circuit comprising: an AC output module, a virtual neutral line module, and a power factor correction module;

The AC output module is used to output at least two-phase AC voltage;

The virtual neutral line module is used to receive the AC voltage output by the AC output module, generate a virtual neutral line, and provide a common midpoint for the power factor correction module;

The power factor correction module includes several identical power factor correction units; each power factor correction unit is respectively connected to the one-phase AC voltage output by the AC output module, and is used to raise and lower the received single-phase AC voltage voltage and power factor correction;

The positive output ends of each power factor correction unit are short-circuited; the negative output ends of each power factor correction unit are short-circuited; the midpoints of each power factor correction unit are short-circuited, as the common midpoint of the power factor correction module, connected to the The output terminal of the virtual neutral line module.

Preferably, the virtual neutral module is: a virtual neutral network composed of several inductive couplings;

The input terminal of the virtual neutral line network is connected to the output terminal of the AC output module, and the output terminal of the virtual neutral line network is connected to the common midpoint of the power factor correction module.

Preferably, when the AC output module outputs a three-phase AC voltage,

The virtual neutral network includes: a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, and three magnetic cores;

The first inductor and the second inductor share a magnetic core; the third inductor and the fourth inductor share a magnetic core; the fifth inductor and the sixth inductor share a magnetic core;

The first inductance, the third inductance, and the fifth inductance are connected in star form; the opposite end of the first inductance, the third inductance, and the fifth inductance are respectively connected to the AC output One-phase output voltage of the module, the terminal with the same name of the first inductor, the terminal with the same name of the third inductor, and the terminal with the same name of the fifth inductor are short-circuited as the output terminal of the virtual neutral network;

The second inductance, the fourth inductance, and the sixth inductance are connected in a delta manner.

Preferably, when the AC output module outputs a three-phase AC voltage,

The virtual neutral network includes: a seventh inductor, an eighth inductor, a ninth inductor, a tenth inductor, an eleventh inductor, a twelfth inductor, and three magnetic cores;

The seventh inductance and the eighth inductance share a magnetic core; the ninth inductance and the tenth inductance share a magnetic core; the eleventh inductance and the twelfth inductance share a magnetic core;

The opposite end of the seventh inductance, the opposite end of the eighth inductor, and the opposite end of the ninth inductance are respectively connected to the one-phase output voltage of the AC output module;

The terminal with the same name of the seventh inductor is connected with the terminal with the same name of the twelfth inductor, the terminal with the same name of the ninth inductor is connected with the terminal with the same name of the eighth resistor, and the terminal with the same name of the eleventh inductor is connected with the terminal with the same name of the twelfth inductor. The opposite end of the tenth inductance;

The terminal with the same name of the eighth inductor, the terminal with the same name of the tenth inductor, and the terminal with the same name of the twelfth inductor are short-circuited as the output terminal of the virtual neutral line network.

Preferably, when the AC output module outputs a three-phase AC voltage,

The virtual neutral line network includes: a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, and a magnetic core; the thirteenth inductor, the fourteenth inductor, and the fifteenth inductor are respectively wound on the magnetic on a stem of the core;

The thirteenth inductance, the fourteenth inductance, and the fifteenth inductance adopt a star connection mode; the same-named end of the thirteenth inductance, the fourteenth inductance The one-phase output voltage of the AC output module;

The opposite end of the thirteenth inductor, the opposite end of the fourteenth inductor, and the opposite end of the fifteenth inductor are short-circuited to serve as the output end of the virtual neutral network.

Preferably, when the AC output module outputs a three-phase AC voltage,

The virtual neutral network includes: a sixteenth inductor, a seventeenth inductor, an eighteenth inductor, a nineteenth inductor, a twentieth inductor, a twenty-first inductor, and a magnetic core;

The sixteenth inductor and the seventeenth inductor share a pillar of the magnetic core, the eighteenth inductor and the nineteenth inductor share a pillar of the magnetic core, and the twentieth inductor and the twenty an inductor sharing a leg of the magnetic core;

The sixteenth inductance, the eighteenth inductance, and the twentieth inductance adopt a star connection; the end of the sixteenth inductance, the end of the eighteenth inductance, and the end of the twentieth inductance are respectively connected to The one-phase output voltage of the AC output module, the opposite end of the sixteenth inductance, the opposite end of the eighteenth inductance, and the opposite end of the twentieth inductance are shorted as the output end of the virtual neutral network ;

The seventeenth inductance, the nineteenth inductance, and the twenty-first inductance are connected in a delta manner.

Preferably, when the AC output module outputs two-phase AC voltage,

The virtual neutral network includes: a twenty-second inductor, a twenty-third inductor, a twenty-fourth inductor, a twenty-fifth inductor, and two magnetic cores;

The twenty-second inductor and the twenty-third inductor share a magnetic core; the twenty-fourth inductor and the twenty-fifth inductor share a magnetic core;

The same-name end of the twenty-second inductor and the different-name end of the twenty-fourth inductor are respectively connected to the one-phase output voltage of the AC output module, and the opposite-name end of the twenty-second inductor and the twenty-fourth inductor The terminal with the same name is short-circuited as the output terminal of the virtual neutral line network;

The same-named end of the twenty-third inductor is connected to the same-named end of the twenty-fifth inductor, and the different-named end of the twenty-fifth inductor is connected to the different-named end of the twenty-third inductor.

Preferably, when the AC output module outputs two-phase AC voltage,

The virtual neutral network includes: a twenty-sixth inductor, a twenty-seventh inductor, and a magnetic core; the twenty-sixth inductor and the twenty-seventh inductor share the magnetic core;

The same-named end of the twenty-sixth inductance and the different-named end of the twenty-seventh inductance are respectively connected to the one-phase output voltage of the AC output module;

The opposite end of the twenty-sixth inductor and the same end of the twenty-seventh inductor are short-circuited to serve as the output end of the virtual neutral network.

Preferably, the power factor correction unit includes: a rectification circuit and a buck-boost circuit;

The rectification circuit has an input terminal, a first output terminal and a second output terminal; the input terminal of the rectification circuit serves as the input terminal of the power factor correction unit, and is connected to a phase AC voltage output by the AC output module , for rectifying the received single-phase AC voltage and outputting it to the buck-boost circuit;

The buck-boost circuit has a first input terminal and a second input terminal, respectively connected to the first output terminal and the second output terminal of the rectification circuit; the buck-boost circuit also has a first output terminal, a second output terminal two output terminals, and a third output terminal;

The first output end of the buck-boost circuit of each power factor correction unit is short-circuited as the positive output end of the power factor correction module; the second output end of the buck-boost circuit of each power factor correction unit is short-circuited, As the negative output terminal of the power factor correction module; the third output terminal of the buck-boost circuit of each power factor correction unit is short-circuited as the common midpoint of the power factor correction module;

The buck-boost circuit is used to perform buck-boost and power factor correction on the single-phase voltage rectified by the rectifier circuit.

Preferably, the rectification circuit includes: a first diode and a second diode; the anode of the first diode is short-circuited with the cathode of the second diode as the input of the rectification circuit terminal; the cathode of the first diode is used as the first output terminal of the rectifier circuit, and the anode of the second diode is used as the second output terminal of the rectifier circuit;

or,

The rectifier circuit includes: a first power tube and a second power tube; the source of the first power tube and the drain of the second power tube are short-circuited as the input end of the rectifier circuit; the first power tube The drain of the tube is used as the first output terminal of the rectification circuit, and the source of the second power tube is used as the second output terminal of the rectification circuit.

Preferably, the buck-boost circuit includes:

The drain of the thirteenth switching tube is short-circuited with the drain of the first switching tube as the first input end of the buck-boost circuit;

The source of the thirteenth switching tube is connected to the cathode of the eighth diode and one end of the first and first inductors, and the source of the first switching tube is connected to the cathode of the seventh diode and one end of the first and second inductors ;

After the other end of the first inductance and the other end of the first and second inductance are short-circuited, they are jointly connected to the drain of the fourth switching tube and the anode of the eleventh diode; the cathode of the eleventh diode As the first output end of the buck-boost circuit;

The source of the fourteenth switch tube is short-circuited with the source of the second switch tube as the second input terminal of the buck-boost circuit;

The drain of the fourteenth switch tube is connected to the anode of the tenth diode and one end of the first four inductors, and the drain of the second switch tube is connected to the anode of the ninth diode and one end of the first three inductors ; After the other end of the first four inductors and the other end of the first three inductors are short-circuited, they are jointly connected to the source of the third switching tube and the cathode of the twelfth diode; The anode serves as the second output end of the buck-boost circuit;

The anode of the eighth diode, the anode of the seventh diode, the source of the fourth switch tube, the cathode of the ninth diode, the cathode of the tenth diode, and the drain of the third switch tube Short circuit, as the third output terminal of the buck-boost circuit;

The first capacitor is connected in parallel between the first output end and the third output end of the buck-boost circuit; the second capacitor is connected in parallel between the third output end and the second output end of the buck-boost circuit

According to the specific embodiments provided by the invention, the invention discloses the following technical effects:

The virtual neutral line power factor correction circuit in the embodiment of the present invention adds a virtual neutral line module inside the high-voltage DC UPS to generate a virtual neutral line to provide a common midpoint for the power factor correction module, so that it can be used without increasing the power factor correction circuit. On the premise of the front-end power frequency transformer, a virtual neutral line is constructed, so that the circuit can adapt to the fluctuation of the power grid, and at the same time, it can well suppress the influence of the unbalanced phase voltage of the power grid, and has a strong adaptability to the power grid.

Description of drawings

FIG. 1 is a structural diagram of a virtual neutral line power factor correction circuit according to Embodiment 1 of the present invention;

FIG. 2 is a structural diagram of a first implementation of a virtual neutral module in an embodiment of the present invention;

FIG. 3 is a structural diagram of a second implementation mode of the virtual neutral line module according to an embodiment of the present invention;

FIG. 4 is a structural diagram of a third implementation mode of a virtual neutral line module according to an embodiment of the present invention;

FIG. 5 is a structural diagram of a fourth implementation mode of the virtual midline module according to an embodiment of the present invention;

FIG. 6 is a structural diagram of a fifth implementation mode of the virtual neutral line module according to the embodiment of the present invention;

FIG. 7 is a structural diagram of a sixth implementation mode of the virtual neutral line module according to an embodiment of the present invention;

FIG. 8 is a circuit diagram of a virtual neutral power factor correction circuit according to Embodiment 2 of the present invention;

FIG. 9 is a circuit structure diagram of a power factor correction unit according to an embodiment of the present invention;

Fig. 10a is a schematic diagram of the first mode of operation of a power factor correction unit according to an embodiment of the present invention;

Fig. 10b is a schematic diagram of the second mode of operation of a power factor correction unit according to an embodiment of the present invention;

Fig. 10c is a schematic diagram of the third mode of operation of a power factor correction unit according to an embodiment of the present invention;

11a to 11e are waveform diagrams of the power factor correction module shown in FIG. 8;

FIG. 12 is a circuit diagram of a virtual neutral line power factor correction circuit according to Embodiment 3 of the present invention;

FIG. 13 is a circuit diagram of a virtual neutral power factor correction circuit according to Embodiment 4 of the present invention;

Fig. 14 is a circuit diagram of a virtual neutral line power factor correction according to Embodiment 5 of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

In view of this, the purpose of the present invention is to provide a virtual neutral line power factor correction circuit, which can construct a virtual neutral line without increasing the power frequency transformer at the front end, so that the circuit can adapt to the fluctuation of the power grid, and at the same time can be easily It can well suppress the influence of grid phase voltage imbalance and has strong grid adaptability.

Referring to FIG. 1 , it is a structural diagram of a virtual neutral line power factor correction circuit provided by Embodiment 1 of the present invention. The circuit includes: an AC output module 10 , a virtual neutral line module 20 , and a power factor correction module 30 .

Wherein, the AC output module 10 is used to output at least two-phase AC voltage.

It should be noted that the AC output module 10 can output two-phase, three-phase, or more than three-phase AC voltages. The AC output module 10 may include at least two single-phase power supplies, each of which outputs a phase of AC voltage.

The input terminal of the virtual neutral line module 20 is connected to the output terminal of the AC output module 10, and the output terminal of the virtual neutral line module 20 is connected to the common midpoint of the power factor correction module 30; the virtual neutral line module 20 uses After receiving the AC voltage output by the AC output module 10 , a virtual neutral line is generated to provide a common neutral point for the power factor correction module 30 .

The power factor correction module 30 includes several identical power factor correction units, and each power factor correction unit is respectively connected to the one-phase AC voltage output by the AC output module 10, and is used to perform the single-phase AC voltage received. Buck-boost and power factor correction; after the midpoints of the power factor correction units are short-circuited, they are connected to the output end of the virtual neutral line module 20 as the common midpoint of the power factor correction module 30 .

It should be noted that the number of power factor correction units included in the power factor correction module 30 is the same as the number of phases of the AC voltage output by the AC output module 10 .

The virtual neutral line power factor correction circuit in the embodiment of the present invention adds a virtual neutral line module 20 inside the high-voltage DC UPS to generate a virtual neutral line to provide a common midpoint for the power factor correction module 30, thereby being able to On the premise of not increasing the front-end power frequency transformer, a virtual neutral line is constructed, so that the circuit can adapt to the fluctuation of the power grid, and at the same time, it can well suppress the influence of the unbalanced phase voltage of the power grid, and has a strong adaptability to the power grid.

In the embodiment of the present invention, the virtual neutral line module 20 may be: a virtual neutral line (ANP: Artificial Neutral Point) network composed of several inductive couplings. The input end of the virtual neutral line network receives the AC voltages of each phase output by the AC output module 10, and its output end is connected to the common midpoint of the power factor correction module 30 to provide a common midpoint for the power factor correction module 30 .

The following describes in detail several specific implementations of the virtual neutral module 20 given in the embodiments of the present invention.

Referring to FIG. 2 , it is a structural diagram of a first implementation mode of the virtual neutral line module 20 provided by the embodiment of the present invention. The virtual neutral module 20 shown in FIG. 2 is used in the case where the AC output module 10 outputs three-phase AC voltage.

As shown in FIG. 2 , the virtual neutral line module 20 includes six inductors and three magnetic cores, and two of the six inductors share one magnetic core.

Specifically, the virtual neutral line module 20 includes: a first inductor L1, a second inductor L2, a third inductor L3, a fourth inductor L4, a fifth inductor L5, a sixth inductor L6, and three magnetic cores. Wherein, the first inductor L1 and the second inductor L2 share a magnetic core; the third inductor L3 and the fourth inductor L4 share a magnetic core; the fifth inductor L5 and the sixth inductor L6 share a magnetic core.

The first inductance L1, the third inductance L3, and the fifth inductance L5 adopt a star connection manner. Specifically, the opposite end of the first inductor L1, the third inductor L3, and the fifth inductor L5 are respectively connected to the one-phase output voltage of the AC output module 10, and the first inductor The terminal with the same name of L1, the terminal with the same name of the third inductor L3 and the terminal with the same name of the fifth inductor L5 are short-circuited as the output terminal of the virtual neutral line module 20 and connected to the common midpoint of the power factor correction module 30 .

The second inductance L2, the fourth inductance L4, and the sixth inductance L6 are connected in a delta manner. Specifically, the opposite name terminal of the second inductor L2 is connected to the same name terminal of the fourth inductor L4; the different name terminal of the fourth inductor L4 is connected to the same name terminal of the sixth inductor L6; the sixth inductor The opposite terminal of L6 is connected to the same terminal of the second inductor L2.

The virtual neutral line module 20 is used to generate a virtual neutral line to provide a common neutral point for the power factor correction module 30 . The common midpoint is the center of gravity of the three-phase voltage vector, and its potential is equal to the potential of point N of the remote power plant, which is a virtual neutral line inside the high-voltage DC UPS.

Referring to FIG. 3 , it is a structural diagram of a second implementation manner of the virtual neutral line module 20 provided by the embodiment of the present invention. The virtual neutral module 20 shown in FIG. 3 is suitable for the case where the AC output module 10 outputs three-phase AC voltage.

As shown in FIG. 3 , the virtual neutral line module 20 is the same as the implementation shown in FIG. 2 in that it also includes six inductors and three magnetic cores, and the six inductors share one magnetic core in pairs.

Specifically, the virtual neutral line module 20 includes: a seventh inductor L7, an eighth inductor L8, a ninth inductor L9, a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, and three magnetic cores. Wherein, the seventh inductor L7 and the eighth inductor L8 share a magnetic core; the ninth inductor L9 and the tenth inductor L10 share a magnetic core; the eleventh inductor L11 and the twelfth inductor L12 share a magnetic core.

The difference between the implementation shown in Fig. 3 and that shown in Fig. 2 is that: the opposite end of the seventh inductor L7, the opposite end of the eighth inductor L8, and the opposite end of the ninth inductor L9 are respectively connected to the AC output module One-phase output voltage of 10; the same-named end of the seventh inductance L7 is connected to the different-named end of the twelfth inductance L12, the same-named end of the ninth inductance L9 is connected to the different-named end of the eighth resistor L8, The end with the same name of the eleventh inductor L11 is connected to the end with the same name of the tenth inductor L10; the end with the same name of the eighth inductor L8, the end with the same name of the tenth inductor L10, and the end with the same name of the twelfth inductor L12 are short-circuited , as the output terminal of the virtual neutral line module 20, connected to the common neutral point of the power factor correction module 30.

Referring to FIG. 4 , it is a structural diagram of a third implementation manner of the virtual neutral module 20 provided by the embodiment of the present invention. The virtual neutral line module 20 shown in FIG. 4 is suitable for the case where the AC output module 10 outputs three-phase AC voltage.

As shown in Figure 4, the virtual neutral module 20 includes: a magnetic core and three inductors, the three inductors share the one magnetic core, and the three inductors are respectively wound on three cores of the EI magnetic core column.

Specifically, the virtual neutral line module 20 includes: a thirteenth inductor L13, a fourteenth inductor L14, a fifteenth inductor L15, and a magnetic core. The thirteenth inductor L13 , the fourteenth inductor L14 , and the fifteenth inductor L15 are respectively wound on a leg of the magnetic core.

The thirteenth inductance L13, the fourteenth inductance L14, and the fifteenth inductance L15 are connected in star form. Specifically, the end with the same name of the thirteenth inductance L13, the end with the same name of the fourteenth inductance L14, and the end with the same name of the fifteenth inductance L15 are respectively connected to the one-phase output voltage of the AC output module 10; the thirteenth The opposite end of the inductance L13, the opposite end of the fourteenth inductance L14, and the fifteenth inductance L15 are short-circuited, and used as the output end of the virtual neutral line module 20, connected to the common terminal of the power factor correction module 30 midpoint.

Referring to FIG. 5 , it is a structural diagram of a fourth implementation manner of the virtual neutral line module 20 provided by the embodiment of the present invention. The virtual neutral line module 20 shown in FIG. 5 is suitable for the case where the AC output module 10 outputs three-phase AC voltage.

As shown in FIG. 5 , the virtual neutral module 20 includes: a magnetic core and six inductors, and two of the six inductors share one leg of the magnetic core.

Specifically, the virtual neutral module 20 includes: a sixteenth inductance L16, a seventeenth inductance L17, an eighteenth inductance L18, a nineteenth inductance L19, a twentieth inductance L20, a twenty-first inductance L21, and a magnetic core. The sixteenth inductance L16 and the seventeenth inductance L17 share a pillar of the magnetic core, the eighteenth inductance L18 and the nineteenth inductance L19 share a pillar of the magnetic core, the twentieth inductance L20 and The twenty-first inductor L21 shares a leg of the magnetic core.

The sixteenth inductance L16, the eighteenth inductance L18, and the twentieth inductance L20 are connected in star form. Specifically, the end with the same name of the sixteenth inductance L16, the end with the same name of the eighteenth inductance L18, and the end with the same name of the twentieth inductance L20 are respectively connected to the one-phase output voltage of the AC output module 10, and the sixteenth The opposite end of the inductance L16, the opposite end of the eighteenth inductance L18, and the opposite end of the twentieth inductance L20 are short-circuited, as the output end of the virtual neutral line module 20, connected to the common terminal of the power factor correction module 30 midpoint.

The seventeenth inductor L17, the nineteenth inductor L19, and the twenty-first inductor L21 are connected in a delta manner. Specifically, the opposite end of the seventeenth inductor L17 is connected to the same end of the nineteenth inductor L19; the opposite end of the nineteenth inductor L19 is connected to the same end of the twenty-first inductor L21; The opposite terminal of the twenty-first inductor L21 is connected to the same terminal of the seventeenth inductor L17.

Referring to FIG. 6 , it is a structural diagram of a fifth implementation manner of the virtual neutral module 20 provided by the embodiment of the present invention. The virtual neutral module 20 shown in FIG. 6 is used in the case where the AC output module 10 outputs two AC voltages.

As shown in FIG. 6 , the virtual neutral line module 20 includes four inductors and two magnetic cores, and two of the four inductors share one magnetic core.

Specifically, the virtual neutral line module 20 includes: a twenty-second inductor L22, a twenty-third inductor L23, a twenty-fourth inductor L24, a twenty-fifth inductor L25, and two magnetic cores. Wherein, the twenty-second inductor L22 and the twenty-third inductor L23 share a magnetic core; the twenty-fourth inductor L24 and the twenty-fifth inductor L25 share a magnetic core.

The same-name end of the twenty-second inductor L22 and the different-name end of the twenty-fourth inductor L24 are respectively connected to the one-phase output voltage of the AC output module 10, and the opposite-name end of the twenty-second inductor L22 is connected to the first The terminals with the same name of the twenty-fourth inductance L24 are short-circuited, as the output terminal of the virtual neutral line module 20 , connected to the common neutral point of the power factor correction module 30 .

The same-named end of the twenty-third inductor L23 is connected to the same-named end of the twenty-fifth inductor L25, and the different-named end of the twenty-fifth inductor L25 is connected to the different-named end of the twenty-third inductor L23.

Referring to FIG. 7 , it is a structural diagram of a sixth implementation manner of the virtual neutral line module 20 provided by the embodiment of the present invention. The virtual neutral module 20 shown in FIG. 7 is used in the case where the AC output module 10 outputs two AC voltages.

As shown in FIG. 7 , the virtual neutral module 20 includes two inductors and one magnetic core, and the two inductors share the one magnetic core.

Specifically, the virtual neutral line module 20 includes: a twenty-sixth inductor L26, a twenty-seventh inductor L27, and a magnetic core. The twenty-sixth inductor L26 and the twenty-seventh inductor L27 share the magnetic core. The same-named end of the twenty-sixth inductor L26 and the different-named end of the twenty-seventh inductor L27 are respectively connected to the one-phase output voltage of the AC output module 10, and the different-named end of the twenty-sixth inductor L26 is It is short-circuited with the terminal of the same name of the twenty-seventh inductor L27, and is used as the output terminal of the virtual neutral line module 20, and connected to the common neutral point of the power factor correction module 30.

The above embodiments of the present invention are described by taking the AC output module 10 outputting two-phase or three-phase AC voltage as an example. When the AC output module 10 outputs multi-phase (more than three-phase) AC voltages, the structure of the virtual neutral module 20 can be the same as that of the various implementations introduced in the above-mentioned embodiments, only need to increase the inductance and magnetic The number of cores is sufficient.

The power factor correction module 30 provided by the embodiment of the present invention will be described in detail below.

Referring to FIG. 8 , it is a circuit diagram of a virtual neutral line power factor correction provided by Embodiment 2 of the present invention. As shown in FIG. 8 , in Embodiment 2 of the present invention, a case where the AC output module 10 provides a three-phase AC output is taken as an example for description.

As shown in FIG. 8, the AC output module 10 may include three single-phase power supplies U1, U2, and U3. The single-phase power supplies U1, U2, and U3 are respectively different single-phase output terminals of a multi-phase AC power supply. Specifically , the three single-phase power sources U1, U2, and U3 of the AC output module 10 respectively output U, V, and W three-phase voltages.

The input terminal of the virtual neutral line module 20 is connected to the three-phase output terminal of the AC output module 10, as shown in FIG. The output terminal of the virtual neutral line module 20 is connected to the common neutral point of the power factor correction module 30 .

As shown in FIG. 8 , correspondingly, the power factor correction module 30 includes three identical power factor correction units S1, S2, and S3, respectively realizing step-down and step-down and power Factor correction while implementing a three-level circuit.

The input terminals of each power factor correction unit are respectively connected to the one-phase output of the AC output module 10; the positive output terminals of each power factor correction unit are short-circuited, and the negative output terminals of each power factor correction unit are short-circuited; each power factor correction unit After the midpoint of the virtual neutral line module 20 is short-circuited, it is used as the common midpoint of the virtual neutral line module 20 and connected to the output terminal of the virtual neutral line module 20 .

For example, the input terminal of the power factor correction unit S1 is connected to the output terminal of the single-phase power supply U1 to receive the U-phase voltage output by the AC output module 10; the input terminal of the power factor correction unit S2 is connected to the output terminal of the single-phase power supply U2 to receive the AC output The V-phase voltage output by the module 10; the input terminal of the power factor correction unit S3 is connected to the output terminal of the single-phase power supply U3 to receive the W-phase voltage output by the AC output module 10 .

As shown in FIG. 8 , in Embodiment 1 of the present invention, the circuit structures of the three power factor correction units S1 , S2 , and S3 are the same. Therefore, only the power factor correction unit S1 is taken as an example for description.

Referring to FIG. 9 , it is a circuit structure diagram of a power factor correction unit provided by an embodiment of the present invention. The power factor correction unit S1 includes: a rectification circuit 310 and a buck-boost circuit 320 .

The rectification circuit 310 has an input terminal, a first output terminal and a second output terminal; the input terminal of the rectification circuit 310 serves as the input terminal of the power factor correction unit S1, and is connected to an output terminal of the AC output module 10. Phase AC voltage.

The buck-boost circuit 320 has a first input terminal and a second input terminal, respectively connected to the first output terminal and the second output terminal of the rectification circuit 310; the buck-boost circuit 320 also has a first output terminal terminal, a second output terminal, and a third output terminal, the first output terminal of the buck-boost circuit 320 is used as the first output terminal of the power factor correction unit S1, and the second output terminal of the buck-boost circuit 320 terminal as the second output terminal of the power factor correction unit S1, and the third output terminal of the buck-boost circuit 320 as the midpoint of the power factor correction unit S1.

The first output end of each power factor correction unit is short-circuited as the positive output end of the power factor correction module 30; the second output end of each power factor correction unit is short-circuited as the positive output end of the power factor correction module 30 Negative output terminal; the midpoint of each power factor correction unit is short-circuited, serving as the common midpoint of the power factor correction module 30 .

The rectification circuit 310 is configured to rectify the received single-phase AC voltage output by the AC output module 10 and output it to the buck-boost circuit 320 .

The buck-boost circuit 320 is used to perform buck-boost and power factor correction on the received rectified single-phase voltage.

The rectification circuit 310 may include: a first diode D1 and a second diode D2.

The anode of the first diode D1 is short-circuited with the cathode of the second diode D2 as the input end of the rectification circuit 310, that is, the input end of the power factor correction unit S1, connected to the One-phase output of the AC output module 10; the cathode of the first diode D1 is used as the first output terminal of the rectification circuit 310, and the anode of the second diode D2 is used as the second output terminal of the rectification circuit 310. output.

The buck-boost circuit 320 can be divided into upper and lower parts.

Wherein, the upper half of the buck-boost circuit 320 may include: a thirteenth switch tube Q13, a first switch tube Q1, a first inductor L1', a first inductor L2', a seventh diode D7 , the eighth diode D8, the fourth switch tube Q4, the eleventh diode D11, and the first capacitor C1.

Specifically: the drain of the thirteenth switching transistor Q13 is short-circuited with the drain of the first switching transistor Q1, and used as the first input terminal of the buck-boost circuit 320, connected to the first input terminal of the rectifier circuit 310 An output terminal; the source of the thirteenth switching tube Q13 is connected to the cathode of the eighth diode D8 and one end of the first inductor L1', and the source of the first switching tube Q1 is connected to the first The cathode of the seven diode D7 and one end of the first and second inductance L2'; the other end of the first and second inductance L1' and the other end of the first and second inductance L2' are short-circuited, and are jointly connected to the fourth switching tube The drain of Q4 and the anode of the eleventh diode D11; the cathode of the eleventh diode D11 serves as the first output terminal of the buck-boost circuit 320, that is, the power factor correction The positive output terminal of the unit S1; the anode of the eighth diode D8, the anode of the seventh diode D7, and the source of the fourth switching transistor Q4 are short-circuited, as the buck-boost circuit The third output terminal of 320 is the midpoint of the power factor correction unit S1; the first capacitor C1 is connected in parallel between the first output terminal and the third output terminal of the buck-boost circuit 320, That is, it is connected between the positive output terminal of the power factor correction unit S1 and the midpoint.

It should be noted that the upper half of the buck-boost circuit 320 adopts an interleaved parallel structure, the switching currents in the first and first inductors L1' and the first and second inductors L2' have a phase difference of 180°, and the first and second inductors L2' have a phase difference of 180°. The sum of the currents of the inductor L1' and the first and second inductors L2' is the input line current, and the current continuity is good.

The lower circuit of the buck-boost circuit 320 may include: the second switching tube Q2, the fourteenth switching tube Q14, the first third inductor L3', the first fourth inductor L4', the ninth diode D9, the tenth The diode D10, the third switch tube Q3, the twelfth diode D12, and the second capacitor C2.

Specifically: the source of the fourteenth switching transistor Q14 is short-circuited with the source of the second switching transistor Q2, and used as the second input terminal of the buck-boost circuit 320, connected to the first input terminal of the rectifier circuit 310 Two output terminals; the drain of the fourteenth switching tube Q14 is connected to the anode of the tenth diode D10 and one end of the first fourth inductance L4', and the drain of the second switching tube Q2 is connected to the first fourth inductance L4'. The anode of the nine diodes D9 and one end of the first third inductance L3'; after the other end of the first fourth inductance L4' and the other end of the first third inductance L3' are short-circuited, they are jointly connected to the third switching tube The source of Q3 and the cathode of the twelfth diode D12; the anode of the twelfth diode D12 is used as the second output terminal of the buck-boost circuit 320, that is, the power factor correction The negative output terminal of the unit S1; the cathode of the ninth diode D9, the cathode of the tenth diode D10, and the drain of the third switching transistor Q3 are short-circuited, connected to the buck-boost circuit The third output terminal of 320 is the midpoint of the power factor correction unit S1; the second capacitor C2 is connected in parallel between the second output terminal and the third output terminal of the buck-boost circuit 320, that is, It is connected between the midpoint and the negative output terminal of the power factor correction unit S1.

It should be noted that the lower half of the buck-boost circuit 320 adopts an interleaved parallel structure, and the phase difference between the switching currents in the first third inductor L3' and the first fourth inductor L4' is 180°. The sum of the currents of the first and third inductors L3' and the first and fourth inductors L4' is the input line current, and the current continuity is good.

The circuit structures and principles of the power factor correction unit S2 and the power factor correction unit S3 are the same as those of the power factor correction unit S1 , and will not be repeated here.

The boost diodes of each power factor correction unit, such as diodes D11 and D12 of S1 in Figure 9, diodes D17 and D18 of S2, and D23 and D24 of S3, as natural parallel diodes, can realize the positive output terminals of each power factor correction unit The short circuit and the negative output terminal are short circuited; and the midpoint of each power factor correction unit is short circuited, as the common midpoint of the power factor correction module 30 , connected to the output terminal of the virtual neutral line module 20 .

The working principle of the power factor correction module 30 according to the embodiment of the present invention will be described in detail below. The power factor correction module 30 adopts a sliding mode control method to realize power factor correction and output buck-boost. The power factor correction module 30 has 6 modes. Here, the power factor correction unit S1 is still taken as an example for illustration.

Referring to Figures 10a to 10c, it is a schematic diagram of the first mode, the second mode and the third mode of operation of a power factor correction unit according to an embodiment of the present invention.

The working process of the first mode shown in Fig. 10a is as follows: at the time t0, the input of phase A crosses zero in the forward direction, the upper half circuit of the power factor correction unit S1 works, and the lower half circuit stops; at the time t>t0 , the power factor correction unit S1 works in boost mode, the first switching tube Q1 and the thirteenth switching tube Q13 are continuously turned on, and the switching tube Q4 performs SPM (Self-phase Modulation, self-phase) pulse width modulation, When the fourth switching tube Q4 is turned on, the current loop is the first diode D1 → the first switching tube Q1 (the thirteenth switching tube Q13) → the first and first inductance L1' (the first and second inductance L2') → the fourth Switching tube Q4; when the fourth switching tube Q4 is turned off, the current loop is the first diode D1 → the first switching tube Q1 (the thirteenth switching tube Q13) → the first and first inductors L1' (the first and second inductors L2 ')→eleventh diode D11→first capacitor C1. The power factor correction unit S1 implements voltage boost in the first mode to reach the target bus voltage Vbus. When the input instantaneous voltage increases to the critical value V1, the first mode ends, and the corresponding time is t1.

The working process of the second mode shown in Fig. 10b is as follows: at the time t>t1, the power factor correction unit S1 works in the buck mode, the fourth switching tube Q4 is continuously turned off, and the first switching tubes Q1, The thirteenth switch tube Q13 performs SPM pulse width modulation respectively, and their driving phase difference is 180°. When the first switching tube Q1 (or the thirteenth switching tube Q13) is turned on, the current loop is the first diode D1→the first switching tube Q1 (the thirteenth switching tube Q13)→the first inductor L1′( First and second inductance L2′)→eleventh diode D11→first capacitor C1; when the first switching tube Q1 (or the thirteenth switching tube Q13) is turned off, the current loop is the seventh diode D7 ( Eighth diode D8) → first first inductor L1' (first second inductor L2') → eleventh diode D11 → first capacitor C1. The power factor correction unit S1 implements voltage reduction in the second mode to reach the target bus voltage Vbus. When the input instantaneous voltage increases to the maximum value and then decreases to the critical value V1, the second mode ends, and the corresponding time is t2.

The working process of the third mode shown in Fig. 10c is as follows: at the moment t>t2, the power factor correction unit S1 works in the boost mode again, and the first switching tube Q1 and the thirteenth switching tube Q13 are continuously turned on, so The fourth switching tube Q4 performs SPM pulse width modulation. When the fourth switching tube Q4 is turned on, the current loop is the first diode D1 → the first switching tube Q1 (the thirteenth switching tube Q13) → the first and first inductor L1' (the first and second inductors L2') → the first Four switching tubes Q4; when the fourth switching tube Q4 is turned off, the current loop is the first diode D1 → the first switching tube Q1 (the thirteenth switching tube Q13) → the first one inductor L1′ (the first two Inductor L2′)→eleventh diode D11→first capacitor C1. The power factor correction unit S1 implements voltage boost in the third mode to reach the target bus voltage Vbus. When the input instantaneous voltage decreases from the critical value V1 to 0, the third mode ends, and the corresponding time is t3.

At time t3, the phase A input crosses zero in the negative direction, the upper half of the circuit of the power factor correction unit S1 stops, and the lower half of the circuit works. The power factor correction unit works in the fourth mode, the fifth mode and the sixth mode, which are respectively symmetrical to the above process, and will not be repeated one by one.

Referring to FIGS. 11 a to 11 e , they are respectively waveform diagrams of the power factor correction module 30 shown in FIG. 8 .

As shown in FIG. 11 a , CH1 to CH4 are respectively the driving waveforms of the first switching tube Q1 , the fourth switching tube Q4 , the second switching tube Q2 and the third switching tube Q3 measured by four channels, and pulse width modulation is adopted.

As shown in FIG. 11 b , CH1 is the measured current of the first switching tube Q1 , CH2 is the measured current of the fourth switching tube Q4 , and the driving waveforms of other channels are correlated.

As shown in FIG. 11c, CH1 is the current of the seventh diode D7, and CH2 is the current of the eleventh diode D11.

As shown in Fig. 11d, CH1 to CH3 are the A, B and C phase currents of the three-phase AC power supply respectively.

As shown in FIG. 11 e , CH1 is the voltage waveform of the bus (ie, both ends of the first capacitor C1 and the second capacitor C2 ). It can be seen that the bus voltage rises steadily, reaches and continues to maintain a stable voltage value at 90ms.

The power factor correction module 30 provided by the embodiment of the present invention does not need to add an input filter or an anti-blocking diode, and cleverly realizes the parallel connection of multiple modules and the continuity of the input current; and the stress of the device used in the embodiment of the present invention is small , low cost, high machine efficiency.

Referring to FIG. 12 , it is a circuit diagram of a virtual neutral line power factor correction provided by Embodiment 3 of the present invention. The difference between the circuit shown in FIG. 12 and the circuit shown in FIG. 8 is that the rectification circuit of the power factor correction unit is realized by synchronous rectification of switching tubes. Specifically, the rectification circuit of each power factor correction unit uses a switch tube instead of a diode.

Specifically, the power factor correction unit S1 is still taken as an example for illustration. As shown in FIG. 12 , the rectification circuit 310 may include: a first power transistor SW1 and a second power transistor SW2.

The source of the first power transistor SW1 and the drain of the second power transistor SW2 are short-circuited, and used as the input terminal of the power factor correction unit S1, connected to the one-phase output of the AC output module 10; the first The drain of the power transistor SW1 serves as the first output terminal of the rectifier circuit 310 , and the source of the second power transistor SW2 serves as the second output terminal of the rectifier circuit 310 .

The buck-boost circuit 320 of the power factor correction unit S1 is the same as the circuit shown in FIG. 8 .

The principle of the circuit of the third embodiment shown in FIG. 12 is the same as the circuit principle of the second embodiment shown in FIG. 8 and will not be repeated here.

Referring to FIG. 13 , it is a circuit diagram of a virtual neutral line power factor correction provided by Embodiment 4 of the present invention. The difference between the circuit shown in FIG. 13 and the circuit shown in FIG. 8 is that the AC output module 10 provides two-phase AC output.

As shown in Figure 13, the AC output module 10 may include two single-phase power supplies U1, U2, the single-phase power supplies U1, U2 are respectively different single-phase output terminals of a multi-phase AC power supply, specifically, the AC The two single-phase power supplies U1 and U2 of the output module 10 respectively output U and V two-phase voltages.

Correspondingly, the power factor correction module 30 includes two identical power factor correction units S1 and S2, which respectively implement buck-boost and power factor correction for the single-phase voltage output by each single-phase power supply, and simultaneously realize two-level circuit.

The circuit structure and working principle of the power factor correction unit of Embodiment 4 shown in FIG. 13 are the same as those shown in FIG. 8 , and will not be repeated here.

Referring to FIG. 14 , it is a circuit diagram of a virtual neutral line power factor correction provided by Embodiment 5 of the present invention. The difference between the circuit of the fifth embodiment shown in FIG. 14 and the third embodiment shown in FIG. 12 is that the AC output module 10 provides a two-phase AC output.

The circuit structure and working principle of the power factor correction unit of the fifth embodiment shown in FIG. 14 are the same as those shown in FIG. 12 , and will not be repeated here.

The above embodiments of the present invention are described by taking the AC output module 10 outputting two-phase or three-phase AC voltage as an example. When the AC output module 10 outputs multi-phase (more than three-phase) AC voltages, the structure of the power factor correction module 30 can be the same as that of the various implementations introduced in the above embodiments, only need to increase the corresponding The number of power factor correction units included in the power factor correction module 30 is sufficient. Specifically, the number of power factor correction units included in the power factor correction module 30 is equal to the number of phases of the AC voltage output by the AC output module 10 .

The power factor correction circuit provided by the embodiment of the present invention does not need to add an input filter or an anti-blocking diode, and cleverly realizes the parallel connection of multiple modules and the continuity of the input current; and the device used in the embodiment of the present invention has small stress, Low cost and high overall efficiency.

A virtual neutral power factor correction circuit provided by the present invention has been introduced in detail above. In this paper, specific examples are used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only used to help understand the present invention. method and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation and application scope. In summary, the contents of this specification should not be construed as limiting the present invention.

Claims (11)

1. A virtual neutral line power factor correction circuit, characterized in that the circuit comprises: an AC output module, a virtual neutral line module, and a power factor correction module; The AC output module is used to output at least two-phase AC voltage; The virtual neutral line module is used to receive the AC voltage output by the AC output module, generate a virtual neutral line, and provide a common midpoint for the power factor correction module; The power factor correction module includes several identical power factor correction units; each power factor correction unit is respectively connected to the one-phase AC voltage output by the AC output module, and is used to raise and lower the received single-phase AC voltage pressure and power factor correction; The positive output ends of each power factor correction unit are short-circuited; the negative output ends of each power factor correction unit are short-circuited; the midpoints of each power factor correction unit are short-circuited, as the common midpoint of the power factor correction module, connected to the The output terminal of the virtual neutral line module. 2. The virtual neutral line power factor correction circuit according to claim 1, wherein the virtual neutral line module is: a virtual neutral line network composed of several inductive couplings; The input terminal of the virtual neutral line network is connected to the output terminal of the AC output module, and the output terminal of the virtual neutral line network is connected to the common midpoint of the power factor correction module. 3. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs a three-phase AC voltage, The virtual neutral network includes: a first inductor, a second inductor, a third inductor, a fourth inductor, a fifth inductor, a sixth inductor, and three magnetic cores; The first inductor and the second inductor share a magnetic core; the third inductor and the fourth inductor share a magnetic core; the fifth inductor and the sixth inductor share a magnetic core; The first inductance, the third inductance, and the fifth inductance are connected in star form; the opposite end of the first inductance, the third inductance, and the fifth inductance are respectively connected to the AC output One-phase output voltage of the module, the terminal with the same name of the first inductor, the terminal with the same name of the third inductor, and the terminal with the same name of the fifth inductor are short-circuited as the output terminal of the virtual neutral network; The second inductance, the fourth inductance, and the sixth inductance are connected in a delta manner. 4. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs a three-phase AC voltage, The virtual neutral network includes: a seventh inductor, an eighth inductor, a ninth inductor, a tenth inductor, an eleventh inductor, a twelfth inductor, and three magnetic cores; The seventh inductance and the eighth inductance share a magnetic core; the ninth inductance and the tenth inductance share a magnetic core; the eleventh inductance and the twelfth inductance share a magnetic core; The opposite end of the seventh inductance, the opposite end of the eighth inductor, and the opposite end of the ninth inductance are respectively connected to the one-phase output voltage of the AC output module; The terminal with the same name of the seventh inductor is connected with the terminal with the same name of the twelfth inductor, the terminal with the same name of the ninth inductor is connected with the terminal with the same name of the eighth resistor, and the terminal with the same name of the eleventh inductor is connected with the terminal with the same name of the twelfth inductor. The opposite end of the tenth inductance; The terminal with the same name of the eighth inductor, the terminal with the same name of the tenth inductor, and the terminal with the same name of the twelfth inductor are short-circuited as the output terminal of the virtual neutral line network. 5. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs a three-phase AC voltage, The virtual neutral line network includes: a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, and a magnetic core; the thirteenth inductor, the fourteenth inductor, and the fifteenth inductor are respectively wound on the magnetic on a stem of the core; The thirteenth inductance, the fourteenth inductance, and the fifteenth inductance adopt a star connection mode; the same-named end of the thirteenth inductance, the fourteenth inductance The one-phase output voltage of the AC output module; The opposite end of the thirteenth inductor, the opposite end of the fourteenth inductor, and the opposite end of the fifteenth inductor are short-circuited to serve as the output end of the virtual neutral network. 6. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs a three-phase AC voltage, The virtual neutral network includes: a sixteenth inductor, a seventeenth inductor, an eighteenth inductor, a nineteenth inductor, a twentieth inductor, a twenty-first inductor, and a magnetic core; The sixteenth inductor and the seventeenth inductor share a pillar of the magnetic core, the eighteenth inductor and the nineteenth inductor share a pillar of the magnetic core, and the twentieth inductor and the twenty an inductor sharing a leg of the magnetic core; The sixteenth inductance, the eighteenth inductance, and the twentieth inductance adopt a star connection; the end of the sixteenth inductance, the end of the eighteenth inductance, and the end of the twentieth inductance are respectively connected to The one-phase output voltage of the AC output module, the opposite end of the sixteenth inductance, the opposite end of the eighteenth inductance, and the opposite end of the twentieth inductance are shorted as the output end of the virtual neutral network ; The seventeenth inductance, the nineteenth inductance, and the twenty-first inductance are connected in a delta manner. 7. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs two-phase AC voltage, The virtual neutral network includes: a twenty-second inductor, a twenty-third inductor, a twenty-fourth inductor, a twenty-fifth inductor, and two magnetic cores; The twenty-second inductor and the twenty-third inductor share a magnetic core; the twenty-fourth inductor and the twenty-fifth inductor share a magnetic core; The same-name end of the twenty-second inductor and the different-name end of the twenty-fourth inductor are respectively connected to the one-phase output voltage of the AC output module, and the opposite-name end of the twenty-second inductor and the twenty-fourth inductor The terminal with the same name is short-circuited as the output terminal of the virtual neutral line network; The same-named end of the twenty-third inductor is connected to the same-named end of the twenty-fifth inductor, and the different-named end of the twenty-fifth inductor is connected to the different-named end of the twenty-third inductor. 8. The virtual neutral power factor correction circuit according to claim 2, wherein when the AC output module outputs two-phase AC voltage, The virtual neutral network includes: a twenty-sixth inductor, a twenty-seventh inductor, and a magnetic core; the twenty-sixth inductor and the twenty-seventh inductor share the magnetic core; The same-named end of the twenty-sixth inductance and the different-named end of the twenty-seventh inductance are respectively connected to the one-phase output voltage of the AC output module; The opposite end of the twenty-sixth inductor and the same end of the twenty-seventh inductor are short-circuited to serve as the output end of the virtual neutral network. 9. The virtual neutral power factor correction circuit according to any one of claims 1 to 8, wherein the power factor correction unit comprises: a rectifier circuit and a buck-boost circuit; The rectification circuit has an input terminal, a first output terminal and a second output terminal; the input terminal of the rectification circuit serves as the input terminal of the power factor correction unit, and is connected to a phase AC voltage output by the AC output module , for rectifying the received single-phase AC voltage and outputting it to the buck-boost circuit; The buck-boost circuit has a first input terminal and a second input terminal, respectively connected to the first output terminal and the second output terminal of the rectification circuit; the buck-boost circuit also has a first output terminal, a second output terminal two output terminals, and a third output terminal; The first output end of the buck-boost circuit of each power factor correction unit is short-circuited as the positive output end of the power factor correction module; the second output end of the buck-boost circuit of each power factor correction unit is short-circuited, As the negative output terminal of the power factor correction module; the third output terminal of the buck-boost circuit of each power factor correction unit is short-circuited as the common midpoint of the power factor correction module; The buck-boost circuit is used to perform buck-boost and power factor correction on the single-phase voltage rectified by the rectifier circuit. 10. The virtual neutral line power factor correction circuit according to claim 9, characterized in that, The rectification circuit includes: a first diode and a second diode; the anode of the first diode is short-circuited with the cathode of the second diode as the input end of the rectification circuit; The cathode of the first diode is used as the first output end of the rectification circuit, and the anode of the second diode is used as the second output end of the rectification circuit; or, The rectifier circuit includes: a first power tube and a second power tube; the source of the first power tube and the drain of the second power tube are short-circuited as the input end of the rectifier circuit; the first power tube The drain of the tube is used as the first output terminal of the rectification circuit, and the source of the second power tube is used as the second output terminal of the rectification circuit. 11. The virtual neutral power factor correction circuit according to claim 9, wherein the buck-boost circuit comprises: The drain of the thirteenth switching tube is short-circuited with the drain of the first switching tube as the first input end of the buck-boost circuit; The source of the thirteenth switching tube is connected to the cathode of the eighth diode and one end of the first and first inductors, and the source of the first switching tube is connected to the cathode of the seventh diode and one end of the first and second inductors ; After the other end of the first inductance and the other end of the first and second inductance are short-circuited, they are jointly connected to the drain of the fourth switching tube and the anode of the eleventh diode; the cathode of the eleventh diode As the first output end of the buck-boost circuit; The source of the fourteenth switch tube is short-circuited with the source of the second switch tube as the second input terminal of the buck-boost circuit; The drain of the fourteenth switch tube is connected to the anode of the tenth diode and one end of the first four inductors, and the drain of the second switch tube is connected to the anode of the ninth diode and one end of the first three inductors ; After the other end of the first four inductors and the other end of the first three inductors are short-circuited, they are jointly connected to the source of the third switching tube and the cathode of the twelfth diode; The anode serves as the second output end of the buck-boost circuit; The anode of the eighth diode, the anode of the seventh diode, the source of the fourth switch tube, the cathode of the ninth diode, the cathode of the tenth diode, and the drain of the third switch tube Short circuit, as the third output terminal of the buck-boost circuit; The first capacitor is connected in parallel between the first output terminal and the third output terminal of the buck-boost circuit; the second capacitor is connected in parallel between the third output terminal and the second output terminal of the buck-boost circuit.

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