CN102194703A - Circuit substrate and manufacturing method thereof - Google Patents

Abstract

A circuit substrate and a manufacturing method thereof. The method includes the following steps: joining the peripheries of two metal layers to form a tight sealing area; forming at least one through hole penetrating the tight sealing area; forming two insulating layers on the two metal layers to form Two conductive layers are placed on two insulating layers; the two insulating layers and the two conductive layers are pressed onto the two metal layers, the two joined metal layers are buried in the two insulating layers, and the two insulating layers are filled in the through holes; Separate the adhesion areas of the two metal layers to form two separate circuit substrates. In this way, thinner substrates can be processed in subsequent patterning processes and electroplating processes. In addition, this method can be used to produce a circuit substrate with an odd number of layers or an even number of layers.

Description

Circuit substrate and manufacturing method thereof

technical field

The invention relates to a circuit substrate and a manufacturing method thereof, and in particular to a coreless circuit substrate and a manufacturing method thereof.

Background technique

Currently, in the semiconductor process, the chip package carrier is one of the frequently used package components. The chip packaging carrier is, for example, a multilayer circuit board, which is mainly composed of multiple circuit layers and multiple dielectric layers alternately laminated, wherein the dielectric layer is arranged between two adjacent circuit layers, and the circuit layer can be They are electrically connected to each other through a plated through hole (Platating Through Hole, PTH) or a conductive hole (via) penetrating the dielectric layer. Since the chip package substrate has the advantages of fine wiring, compact assembly and good performance, it has become the mainstream of the chip package structure.

Generally speaking, the circuit structure of multilayer circuit boards is mostly made by build up or laminated, so it has the characteristics of high circuit density and narrow circuit spacing. Due to the lack of rigidity of the ultra-thin substrate, it is necessary to provide a substrate with a certain thickness as a supporting carrier. Then, sequentially coating a large amount of colloid and forming multi-layer circuit layers and multi-layer dielectric layers alternately arranged with the circuit layers on the two opposite surfaces of the substrate. Finally, the colloid is removed to separate the circuit layer and dielectric layer on the colloid from the substrate to form two separate multilayer circuit boards. In addition, if it is desired to form a via hole or a conductive hole, after forming a dielectric layer, a blind hole may be formed first to expose the circuit layer under the dielectric layer. Afterwards, the copper layer is electroplated in the blind hole and on the dielectric layer by means of electroplating, so as to form another circuit layer and a via hole or a conductive hole.

Since it is known that a substrate with a certain thickness must be provided as a support carrier for the copper foil layer, and if the substrate is made of metal material, the material cost itself will be high, so the manufacturing cost required for the multilayer circuit board will also increase. In addition, a large amount of glue must be used to fix the copper foil layer and the substrate, so the step of removing the glue is difficult, and the process yield cannot be improved. In addition, the uniformity of the copper thickness of the circuit layer formed by electroplating is not good. Therefore, when the required thickness of the circuit layer is relatively thin, a thinning process (such as an etching process) is required to reduce the thickness of the circuit layer. In this way, not only will the manufacturing steps of the multilayer circuit board be increased, but also the process yield of the multilayer circuit board will be reduced.

Contents of the invention

The invention provides a circuit substrate and a manufacturing method thereof, which can reduce process steps, reduce production costs, improve process yield, and further increase product reliability.

The invention proposes a manufacturing method of a circuit substrate, which includes the following steps: bonding the peripheries of two metal layers to form a bonding area. At least one through hole is formed through the bonding area. Two insulating layers are formed on the two metal layers, and two conductive layers are formed on the two insulating layers. Pressing the two insulating layers and the two conductive layers onto the two metal layers, wherein the two metal layers connected to each other are embedded in the two insulating layers, and the two insulating layers are filled in the through holes. The bonding regions of the two metal layers are separated to form two separate circuit substrates.

In an embodiment of the present invention, the above-mentioned method for joining the peripheries of the two metal layers includes electric welding, spot welding or adhesive, wherein the material of the adhesive includes cyanoacrylate or polypropylene resin.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit board further includes: after laminating the second insulating layer and the second conductive layer on the two metal layers, removing part of the second insulating layer and part of the second conductive layer to form A plurality of blind vias exposing two metal layers. A conductive material is formed in the blind hole and on the two conductive layers that have not been removed. After separating the bonding area of the two metal layers, the conductive material, the metal layer and the conductive layer are patterned.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit board further includes: after laminating the second insulating layer and the second conductive layer on the two metal layers, removing part of the second insulating layer and part of the second conductive layer to form A plurality of blind vias exposing two metal layers. Thinning the second conductive layer. Forming a second electroplating seed layer on the thinned second conductive layer and in the blind hole. After separating the bonding area of the two metal layers, the metal layer is exposed. A patterned photoresist layer is formed on the electroplating seed layer and on the exposed metal layer respectively. The electroplating seed layer is electroplated using the patterned photoresist layer as a mask. The patterned photoresist layer and the portion of the plating seed layer covered by the patterned photoresist layer are removed.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit substrate further includes: after laminating the two insulating layers and the two conductive layers on the two metal layers, patterning the two conductive layers to form a second patterned conductive layer. Another two insulating layers are formed on the two patterned conductive layers, and another two conductive layers are formed on the other two insulating layers. The insulating layer and the other two conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layer. After separating the bonding area of the two metal layers, part of the insulating layer, part of the metal layer and part of another conductive layer are removed to form a plurality of blind holes exposing the patterned conductive layer. A conductive material is formed in the blind hole and on the unremoved metal layer and another conductive layer. Patterning the conductive material, the metal layer and another conductive layer.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit substrate further includes: after laminating the two insulating layers and the two conductive layers on the two metal layers, patterning the two conductive layers to form a second patterned conductive layer. Another two insulating layers are formed on the two patterned conductive layers, and another two conductive layers are formed on the other two insulating layers. The insulating layer and the other two conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layer. After separating the bonding area of the two metal layers, part of the insulating layer, part of the metal layer and part of another conductive layer are removed to form a plurality of blind holes exposing the patterned conductive layer. The other conductive layer and the metal layer are removed to expose the insulating layer. Forming two electroplating seed layers on the insulating layer and in the blind hole. Forming two patterned photoresist layers on the two electroplating seed layers. The electroplating seed layer is electroplated using the patterned photoresist layer as a mask. The patterned photoresist layer and the portion of the plating seed layer covered by the patterned photoresist layer are removed.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit board further includes: after laminating the second insulating layer and the second conductive layer on the two metal layers, removing part of the second insulating layer and part of the second conductive layer to form A plurality of first blind holes exposing two metal layers. The two conductive layers are removed to expose the two insulating layers. Forming two electroplating seed layers on the second insulating layer and in the first blind hole. Forming two patterned photoresist layers on the electroplating seed layer. The electroplating seed layer is electroplated using the patterned photoresist layer as a mask. The patterned photoresist layer and the part of the electroplating seed layer covered by the patterned photoresist layer are removed to form two patterned conductive layers and a plurality of conductive via structures on the two insulating layers. Another two insulating layers are formed on the two patterned conductive layers, and another two conductive layers are formed on the other two insulating layers. The insulating layer and the other two conductive layers are laminated, and the two patterned conductive layers are embedded in the insulating layer. After separating the bonding area of the two metal layers, part of the insulating layer, the metal layer and another conductive layer are removed to form a plurality of second blind holes exposing the patterned conductive layer. Another two electroplating seed layers are formed on the other two insulating layers, one end of the first blind hole and inside the second blind hole. Another two patterned photoresist layers are formed on the other two electroplating seed layers. Electroplating is performed on the other two electroplating seed layers by using the other two patterned photoresist layers as masks. The other two patterned photoresist layers and the portion of the other two electroplating seed layers covered by the other two patterned photoresist layers are removed.

In an embodiment of the present invention, the above two metal layers respectively include a first copper foil layer and a second copper foil layer, and the thickness of each second copper foil layer is substantially greater than the thickness of each first copper foil layer, The second copper foil layers are bonded to each other.

In an embodiment of the present invention, the above-mentioned method for manufacturing a circuit substrate further includes: after laminating the two insulating layers and the two conductive layers on the two metal layers, patterning the two conductive layers to form a first patterned conductive layer and the second patterned conductive layer. A plurality of first through holes extending from the first patterned conductive layer to the second patterned conductive layer are formed. After separating the bonding area of the two metal layers, the second copper foil layer is removed. A first insulating layer is formed on the first patterned conductive layer, and a first conductive layer is formed on the first insulating layer. The first insulating layer and the first conductive layer are pressed together, and the first patterned conductive layer is buried in the insulating layer and the first insulating layer. Part of the insulating layer, the first insulating layer, part of the first copper foil layer and part of the first conductive layer are removed to form a plurality of first blind holes exposing the first patterned conductive layer. An electroplating seed layer is respectively formed on the unremoved first copper foil layer and in the first blind hole, and on the unremoved first conductive layer and in the first blind hole. Forming two patterned photoresist layers on the electroplating seed layer. Using the patterned photoresist layer as a mask, the electroplating seed layer is electroplated to form a plurality of conductive blind hole structures in the first blind hole. The patterned photoresist layer and the portion of the plating seed layer covered by the patterned photoresist layer are removed.

In an embodiment of the present invention, the formation of the first insulating layer on the first patterned conductive layer and the formation of the first conductive layer on the first insulating layer are performed after separating the adhesive regions of the two metal layers.

In an embodiment of the present invention, the formation of the first insulating layer on the first patterned conductive layer and the formation of the first conductive layer on the first insulating layer are before separating the adhesive regions of the two metal layers.

In an embodiment of the present invention, the above-mentioned method for manufacturing a circuit substrate further includes: forming a first insulating layer on the first patterned conductive layer, and forming a second insulating layer when forming the first conductive layer on the first insulating layer. The insulating layer is on the second patterned conductive layer, and the second conductive layer is formed on the second insulating layer.

In an embodiment of the present invention, the above-mentioned method for manufacturing a circuit substrate further includes: after removing the patterned photoresist layer and the part of the electroplating seed layer covered by the patterned photoresist layer, forming a first The protection layer is on the first insulation layer, and the second protection layer is formed on the insulation layer, wherein the first protection layer and the second protection layer cover the conductive blind hole structure. A grinding process is performed to remove part of the first passivation layer and part of the second passivation layer to expose the conductive blind hole structure. The remaining first protective layer and second protective layer are removed.

In an embodiment of the present invention, the above-mentioned method for manufacturing a circuit substrate further includes removing the patterned photoresist layer and the part of the electroplating seed layer covered by the patterned photoresist layer, and then forming a first anti-corrosion layer. A solder layer is formed on the first insulating layer, and a second solder resist layer is formed on the insulating layer, wherein the first solder resist layer has a plurality of first openings, the second solder resist layer has a plurality of second openings, and the first opening and The second opening exposes part of the conductive blind via structure.

The invention provides a circuit substrate, which includes a patterned metal layer, a patterned conductive layer, an insulating layer and a conductive material. The insulating layer is located between the patterned metal layer and the patterned conductive layer. The conductive material is located in a plurality of blind holes, wherein the blind holes penetrate the insulating layer, and the conductive material is electrically connected to the patterned metal layer and the patterned conductive layer.

The invention provides a circuit substrate, which includes a patterned metal layer, a patterned conductive layer, a patterned conductive layer, two insulating layers and a conductive material. The patterned conductive layer is located between the patterned metal layer and the patterned conductive layer. The insulation layer is respectively located between the patterned metal layer and the patterned conductive layer and between the patterned conductive layer and the patterned conductive layer. The conductive material is located in a plurality of blind holes, wherein the blind holes penetrate the insulating layer, and the conductive material is electrically connected between the patterned metal layer and the patterned conductive layer and between the patterned conductive layer and the patterned conductive layer.

Based on the above, the present invention firstly bonds the surroundings of the two metal layers to form a sealing area. After the lamination step of the insulating layer on both sides and the conductive layer on both sides is completed, the two metal layers are separated. Therefore, compared with the known technology, the manufacturing method of the circuit substrate of the present invention does not need to use a metal substrate as a supporting carrier, which means that it is a coreless circuit substrate structure, which can effectively reduce the production of circuit substrates. cost, and can improve the reliability of the circuit substrate and effectively reduce the time schedule for manufacturing the circuit substrate.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1A to 1H are schematic cross-sectional views of a manufacturing method of a circuit substrate according to an embodiment of the present invention.

1A to 1E and 1F' to 1J' are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention.

2A to 2I are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention.

2A to 2G and 2H' to 2K' are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention.

FIGS. 2A to 2C and FIGS. 2D″ to 2M″ are schematic cross-sectional views of a manufacturing method of a circuit substrate according to another embodiment of the present invention.

3A to 3P are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention.

4A to 4B are schematic cross-sectional views of a manufacturing method of a circuit substrate according to another embodiment of the present invention.

Explanation of reference signs

100a, 100a', 100b: circuit substrate 102: metal layer

104: Closed area 112: Insulation layer

112a: upper surface 112b: lower surface

122, 122': conductive layer 124, 124': conductive material

124a: first patterned conductive material 124b: second patterned conductive material

124c: Conductive blind hole structure 132: Electroplating seed layer

134: Patterned photoresist layer

200a, 200a', 200b, 200c, 200c': Circuit board

202: Metal layer 204: Closed area

232, 212, 234: insulating layer 212b: lower surface

222: Conductive layer 222a: Patterned conductive layer

232a: upper surface 242, 248: conductive layer

244, 244': conductive material 244a: first patterned conductive material layer

244b: second patterned conductive material layer 244c: conductive blind hole structure

246: Conductive material 246a: Patterned conductive material layer

246b: Conductive Blind Via Structure 249: Conductive Materials

249a: Patterned conductive material layer 249b: Conductive blind via structure

252, 256: Electroplating seed layer 254, 258: Patterned photoresist layer

300: circuit substrate 310’, 310”: metal layer

310a: the first copper foil layer 310b: the second copper foil layer

310c: the third copper foil layer 310d: the fourth copper foil layer

310e: fifth copper foil layer 310f: sixth copper foil layer

320: Adhesive 332: First through hole

334: Second through hole 342: First conductive layer

342a: The first circuit layer 344: The second conductive layer

344a: The second circuit layer 350a: The first insulation layer

350b: Second insulating layer 350c: Third insulating layer

350d: The fourth insulation layer 360a: The first circuit substrate

360b: the second circuit substrate 400a: the first circuit substrate

400c: The third circuit substrate 400d: The fourth circuit substrate

412: The first blind hole 412a: The first conductive blind hole structure

414: Second blind hole 414a: Second conductive blind hole structure

420: chemical copper layer

432: First patterned dry film photoresist layer

434: Second patterned dry film photoresist layer

440: electroplated copper layer 452: first protective layer

454: Second protective layer 462: First solder mask

462a: first opening 464: second solder mask

464a: second opening

H: Through hole V: Blind hole

V1: The first blind hole V2: The second blind hole

Detailed ways

1A to 1H are schematic cross-sectional views of a manufacturing method of a circuit substrate according to an embodiment of the present invention. Please refer to FIG. 1A and FIG. 1B at the same time. Regarding the manufacturing method of the circuit substrate of this embodiment, first, two metal layers 102 are provided, wherein these metal layers 102 are, for example, copper foil or other metal foils, and these metal layers 102 are bonded. to form a close contact area 104. In this embodiment, the method of joining the peripheries of the metal layers 102 includes electric welding or spot welding, so that the metal layers 102 are temporarily joined together, so as to prevent the chemicals used in subsequent processes from penetrating into the metal layers 102 . Of course, in addition to electric welding or spot welding, adhesives, such as cyanoacrylate or polypropylene resin, or other colloids can also be used to temporarily join the peripheries of the metal layers 102 together. It is worth mentioning that the metal layers 102 described herein can be regarded as coreless structural layers.

In addition, please refer to FIG. 1B again. In this embodiment, after the peripheral edges of the metal layers 102 are bonded, at least one through hole H (only two are schematically shown in FIG. 1B ) can be formed through the bonding area. The methods for forming these through holes H include laser drilling or mechanical drilling. Since the diameter of these through holes H is smaller than that of the bonding area 104 , the sealing performance of the bonding area 104 will not be damaged by these through holes H.

Next, please refer to FIG. 1C and FIG. 1D at the same time, form two insulating layers 112 on these metal layers 102, form two conductive layers 122 on these insulating layers 112, and press these insulating layers 112 and these conductive layers 122, and The bonded metal layers 102 are embedded between the insulating layers 112 . At the same time, the insulating layers 112 can also be filled in the through holes H in the bonding area 104 during the bonding. Since the size of the insulating layers 112 is larger than that of the metal layers 102 , the metal layers 102 can be completely covered in the insulating layers 112 without being polluted by external impurities or chemicals.

Next, referring to FIG. 1E , part of the insulating layers 112 and part of the conductive layers 122 are removed to form a plurality of blind holes V exposing the metal layers 102 . In this embodiment, the method of forming the blind holes V includes laser forming, and the method of removing part of the conductive layers 122 includes laser etching or photolithography etching.

Next, referring to FIG. 1F , a conductive material 124 is formed in the blind holes V and on the conductive layers 122 that have not been removed. Wherein, the method of forming the conductive material 124 includes electroplating, and the conductive material 124 is, for example, copper or other metals. It must be noted here that since these metal layers 102 can be completely covered in these insulating layers 112 without being polluted by external impurities or chemicals, when the conductive material 124 is formed on these blind layers through an electroplating process, When the holes V are on the conductive layers 122 that are not removed, the original size and thickness of the metal layers 102 embedded in the insulating layers 112 will not be affected.

Next, referring to FIG. 1F and FIG. 1G at the same time, the bonding regions 104 of these metal layers 102 are separated to form two separated circuit substrates 100a'. In this embodiment, the metal layers 102 can be completely separated by removing the bonding area 104 covering the metal layers 102 by using the through holes H as reference points by using a forming machine or other tools. Of course, separating the metal layers 102 is not limited to the above-mentioned method.

Afterwards, referring to FIG. 1H , the conductive material 124, the metal layers 102, and the conductive layers 122 are patterned to form required circuits on the respective circuit substrates 100a' to form two circuit substrates 100a. In short, each circuit substrate 100a of this embodiment includes a patterned metal layer 102, a patterned conductive layer 122, an insulating layer 112, and a conductive material 124, wherein the insulating layer 112 is located between the patterned metal layer 102 and the patterned Between the conductive layer 122. The conductive material 124 is located in a plurality of blind holes V, wherein the blind holes V penetrate the insulating layer 112 , and the conductive material 124 is electrically connected to the patterned metal layer 102 and the patterned conductive layer 122 . So far, the fabrication of the coreless circuit substrate 100a has been completed.

It must be noted here that the following embodiments use the component numbers and part of the content of the previous embodiments, wherein the same numbers are used to denote the same or similar components, and descriptions of the same technical content are omitted. For the description of omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

1A to 1E and 1F' to 1J' are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention. The fabrication method of the circuit substrate 100b of this embodiment is similar to the fabrication method of the existing circuit substrate 100a, the difference being that after the step in FIG. A plurality of blind holes V exposing the metal layers 102 and the conductive layers 122 are formed. Afterwards, please refer to FIG. 1E and FIG. 1F' at the same time, these conductive layers 122 are thinned to form a plurality of conductive layers 122', and two electroplating seed layers 132 are formed on these conductive layers 122' and in these blind holes V, wherein these The electroplating seed layer 132 completely covers the conductive layers 122 ′, the inner walls of the blind holes V and part of the metal layers 102 . Next, referring to FIG. 1G', the bonding regions 104 of the metal layers 102 are separated to expose the metal layers 102. Referring to FIG. Next, referring to FIG. 1H′, a patterned photoresist layer 134 is formed on the electroplating seed layer 132 and on the exposed metal layer 102 respectively. Afterwards, referring to FIG. 1I', using the patterned photoresist layer 134 as a mask, the plating seed layer 132 and the metal layer 102 are electroplated to form the conductive material 124'. Finally, please refer to FIG. 1J ', remove the patterned photoresist layer 134, the plating seed layer 132 covered by the patterned photoresist layer 134 and the metal layer 102 covered by the patterned photoresist. layer 134 to expose part of the upper surface 112a and part of the lower surface 112b of the insulating layer 112 to form the first patterned conductive material layer 124a, the second patterned conductive material layer 124b and the conductive blind hole structure 124c, wherein The conductive blind hole structure 124c is electrically connected to the first patterned conductive material layer 124a and the second patterned conductive material layer 124b. So far, the fabrication of the circuit substrate 100b has been completed.

The above embodiment is to form two layers of circuit substrates 100a, 100b, but in another embodiment, the two layers of circuit substrates 100a, 100b can be used as the core layer, and four-layer, six-layer or more than six-layer circuits can be completed in sequence. The method of the substrate is a general circuit substrate process, which will not be repeated here. In addition, in order to fabricate circuits with odd layers, the present invention provides another method for fabricating a circuit substrate.

2A to 2I are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention. Please refer to FIG. 2A and FIG. 2B at the same time. Regarding the manufacturing method of the circuit substrate of this embodiment, first, two metal layers 202 are provided, such as copper foil or other metal foils, and the peripheral edges of these metal layers 202 are bonded to form Closed area 204 . Wherein, the method for joining the peripheries of the metal layers 202 includes electric welding or spot welding, so that the metal layers 202 are temporarily joined together, so as to prevent chemicals used in subsequent processes from penetrating between the metal layers 202 . Of course, in addition to electric welding or spot welding, adhesives, such as cyanoacrylate or polypropylene resin, or other colloids can also be used to temporarily join the peripheries of the metal layers 202 together. It is worth mentioning that the metal layers 202 described here can be regarded as coreless structural layers.

Please refer to FIG. 2B again. In this embodiment, after the peripheral edges of the metal layers 202 are bonded, at least one through hole H (only two are schematically shown in FIG. 2B ) can be formed through the bonding area 204 . Wherein, the method of forming these through holes H includes laser forming or mechanical drilling.

Next, referring to FIG. 2C to FIG. 2E , two insulating layers 212 are formed on the metal layers 202 , and two conductive layers 222 are formed on the insulating layers 212 . The conductive layers 222 can be patterned at the same time while the metal layers 202 are still in the bonded state, so as to form the second patterned conductive layer 222a. Next, another two insulating layers 232 are formed on the patterned conductive layers 222 a, and another two conductive layers 242 are formed on the insulating layers 232 . In FIG. 2C , the insulating layers 212 and the conductive layers 222 are laminated, and the joined metal layers 202 are embedded in the insulating layers 212 . In addition, in FIG. 2E , the insulating layers 232 , 212 and the conductive layers 242 are laminated, and the patterned conductive layers 222 a are embedded in the insulating layers 232 , 212 . At the same time, the insulating layers 212 can also be filled in the through holes H in the bonding area 204 during the bonding. Since the size of the insulating layers 212 is larger than that of the metal layers 202 , the metal layers 202 can be completely covered in the insulating layers 212 without being polluted by external impurities or chemicals.

Next, referring to FIG. 2F , the bonding regions 204 of the metal layers 202 are separated to form two separate circuit substrates 200a'. Here, these circuit substrates 200a' respectively have three layers of circuits. In this embodiment, a molding machine or other tools can be used to remove the areas of the metal layers 202 covered by the bonding area 204 with these through holes H (please refer to FIG. 2E ) as reference points, so that these metal layers 202 can be completely separate. Of course, the separation of these metal layers 202 is not limited to the above-mentioned manner.

Next, please refer to FIG. 2G , which only shows one of the circuit substrates 200a'. Parts of the insulating layers 212, 232, part of the metal layer 202 and part of the conductive layer 242 are removed to form a plurality of blind holes V exposing the patterned conductive layer 222a. Among them, the method of forming these blind holes V includes laser hole forming. After that, referring to FIG. 2H , a conductive material 244 is formed in the blind holes V and on the unremoved metal layer 202 and the conductive layer 242 . Wherein, the method of forming the conductive material 244 includes electroplating, and the conductive material 244 is, for example, copper or other metals. Finally, referring to FIG. 2I , the conductive material 244, the metal layer 202 and the conductive layer 242 are patterned to form required circuits on the respective circuit substrates 200a', and the fabrication of the circuit substrate 200a is completed.

In short, as shown in FIG. 2I, a circuit substrate 200a' having a three-layer circuit includes a patterned metal layer 202, a patterned conductive layer 242, a patterned conductive layer 222a, two insulating layers 212, 232 and a conductive Materials 244. The patterned conductive layer 222 a is located between the patterned metal layer 202 and the patterned conductive layer 242 . The insulating layers 212 and 232 are respectively located between the patterned metal layer 202 and the patterned conductive layer 222a and between the patterned conductive layer 242 and the patterned conductive layer 222a. The conductive material 244 is located in a plurality of blind holes V, these blind holes V penetrate the insulating layers 212, 232, and the conductive material 244 is electrically connected between the patterned metal layer 202 and the patterned conductive layer 222a and the patterned conductive layer 222a. layer 242 and the patterned conductive layer 222a.

2A to 2G and 2H' to 2K' are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention. The fabrication method of the circuit substrate 200b of this embodiment is similar to the fabrication method of the existing circuit substrate 200a, the difference is that after the step in FIG. After part of the conductive layer 242 is formed to expose the blind holes V of the patterned conductive layer 222a, please refer to FIG. The seed layer 252 is on the insulating layers 212 , 232 and in the blind holes V. As shown in FIG. Next, referring to FIG. 2I′, two patterned photoresist layers 254 are formed on the electroplating seed layers 252 . After that, please refer to FIG. 2J', using the patterned photoresist layer 254 as a mask, the electroplating seed layers 252 are electroplated to form the conductive material 244'. Finally, referring to FIG. 2K′, remove the patterned photoresist layer 254 and the plating seed layer 252 covered by the patterned photoresist layer 254 to expose the insulating layer 232. The surface 232a and part of the lower surface 212b of the insulating layer 212 form a first patterned conductive material layer 244a, a second patterned conductive material layer 244b and a plurality of conductive blind hole structures 244c, wherein these conductive blind hole structures 224c are electrically connected The first patterned conductive material layer 244a and the patterned conductive layer 222a and the patterned conductive layer 222a and the second patterned conductive material layer 244b. So far, the fabrication of the circuit substrate 200b has been completed.

FIGS. 2A to 2C and FIGS. 2D″ to 2M″ are schematic cross-sectional views of a manufacturing method of a circuit substrate according to another embodiment of the present invention. The fabrication method of the circuit substrate 200c of this embodiment is similar to the fabrication method of the existing circuit substrate 200a, the difference is that after the step in FIG. 2C, the insulating layers 212 and the conductive layers 222 are pressed to the metal layers. 202, please refer to FIG. 2D ″, remove some of these insulating layers 212 and some of these conductive layers 222 to form a plurality of first blind holes V1 exposing these metal layers 202. Next, please refer to FIG. 2E″, move The conductive layers 222 are removed to expose the insulating layers 212, and two plating seed layers 252 are formed on the insulating layers 212 and in the first blind holes V1. Then, please refer to FIG. 2F ", form two patterned photoresist layers 254 on these electroplating seed layers 252. Next, please refer to Fig. 2G ", with these patterned photoresist layers 254 as a mask, These plating seed layers 252 are plated to form conductive material 246 . Next, please refer to FIG. 2H ", remove these patterned photoresist layers 254 and the parts of these plating seed layers 252 covered by these patterned photoresist layers 254, to form two layers on these insulating layers 252 The conductive material layer 246a and the plurality of conductive via structures 246b are patterned.

Then, please refer to FIG. 2I ", form another two insulating layers 234 on these patterned conductive layers 246a, and form another two conductive layers 248 on these insulating layers 234. Then, press these insulating layers 234 and these conductive layers 248 , and these patterned conductive layers 246a are buried in these insulating layers 212, 234. Next, please refer to FIG. It must be noted here that only one of the circuit substrates 200c' is shown in FIG. 2J″. Next, please refer to FIG. The second blind hole V2 of the patterned conductive layer 246a is formed. Then, please refer to FIG. 2K ", form another two electroplating seed layers 256 on these insulating layers 212, 234, one end of the first blind hole V1 and in the second blind hole V2. Then, please refer to Fig. 2L ", form another two A patterned photoresist layer 258 is formed on the electroplating seed layers 256 , and the electroplating seed layers 256 are electroplated using the patterned photoresist layer 258 as a mask to form the conductive material 249 . Finally, please refer to FIG. 2M ", remove these patterned photoresist layers 258 and the parts of these plating seed layers 256 covered by these patterned photoresist layers 258, so that on these insulating layers 212,234 Two patterned conductive material layers 249a and a plurality of conductive via structures 249b are formed. Here, these conductive via structures 246b, 249b are electrically connected to the patterned conductive layer 246a and these patterned conductive material layers 249a. So far, to complete the Fabrication of a circuit substrate 200c with three layers of circuits.

It is worth mentioning that the above embodiments are circuit substrates 200a, 200b, 200c formed with three-layer circuits, but in other unillustrated embodiments, the circuit substrates 200a, 200b, 200c with three-layer circuits can be used as the core Layers, and sequentially complete five-layer, seven-layer or more than seven-layer circuit substrates. The method is a general circuit substrate process. Those skilled in the art can refer to the descriptions of the foregoing embodiments and select the foregoing components according to actual needs. , in order to achieve the required technical effect, so it will not be repeated here.

From the above description, it can be known that no matter whether it is an odd-numbered layer circuit or an even-numbered layer circuit, it can be completed by using the above-mentioned manufacturing method of the circuit substrate 100a, 100b, 200a, 200b, 200c, not only can the two circuit substrates 100a be completed within the same production time , 100b, 200a, 200b, 200c, so as to speed up the production schedule of the multilayer circuit board, and also avoid the problem of warpage of the circuit substrate 100a, 100b, 200a, 200b, 200c. In addition, compared with the known technology, the manufacturing method of the circuit substrates 100a, 100b, 200a, 200b, and 200c in this embodiment does not need to use a metal substrate as a supporting carrier, that is, a coreless circuit substrate, which can effectively Reduce the production cost of circuit substrates 100a, 100b, 200a, 200b, 200c, and can improve the reliability of circuit substrates 100a, 100b, 200a, 200b, 200c and effectively reduce the time for producing circuit substrates 100a, 100b, 200a, 200b, 200c Procedure.

It is worth mentioning that the present invention does not limit the shape of these metal layers 102, 202, although the metal layers 102, 202 mentioned here are embodied in the shape of a single metal layer, but in other embodiments, These metal layers 102 , 202 may also be metal layers composed of multi-layer copper foil layers, which still belong to the applicable technical solutions of the present invention and do not depart from the protection scope of the present invention.

In detail, FIGS. 3A to 3P are schematic cross-sectional views of a method for fabricating a circuit substrate according to another embodiment of the present invention. Please refer to FIG. 3A first, regarding the manufacturing method of the circuit substrate of this embodiment, first, provide two metal layers 310', 310", wherein the metal layer 310' is formed by the first copper foil layer 310a, located on the first copper foil layer 310a The metal layer 310" is composed of the third copper foil layer 310c and the fourth copper foil layer 310d on the third copper foil layer 310c. Wherein, the second copper foil layer 310b is partially bonded to the fourth copper foil layer 310d through an adhesive 320 . That is to say, the adhesive 320 is located between the second copper foil layer 310b and the fourth copper foil layer 310d, and only partially bonds the second copper foil layer 310b and the fourth copper foil layer 310d. In addition, the first copper foil layer 310 a and the second copper foil layer 310 b described herein can be regarded as a coreless structure layer. Similarly, the third copper foil layer 310c and the fourth copper foil layer 310d thereon can be regarded as a core-less structure layer.

In this embodiment, the thickness of the second copper foil layer 310b is substantially greater than the thickness of the first copper foil layer 310a, wherein the thickness of the first copper foil layer 310a is, for example, 3 microns (μm), and the second copper foil layer 310b The thickness is, for example, 12 microns (μm). The thickness of the first copper foil layer 310a is substantially the same as that of the third copper foil layer 310c, which means that the thickness of the third copper foil layer 310c is also, for example, 3 microns (μm). The thickness of the second copper foil layer 310b is substantially the same as the thickness of the fourth copper foil layer 110d, that is, the thickness of the fourth copper foil layer 310d is also, for example, 12 micrometers (μm). Wherein, the second copper foil layer 310b in this embodiment can be used to support the first copper foil layer 310a, and similarly, the fourth copper foil layer 310d can be used to support the third copper foil layer 310c. Therefore, this embodiment does not need to use a metal substrate as a supporting carrier as known, which can effectively reduce the manufacturing cost. In addition, the adhesive 320 of this embodiment is, for example, cyanoacrylate (commonly known as three-second glue), polypropylene resin (ie, PP glue). It is worth mentioning that although the adhesive 320 is used to join the second copper foil layer 310b and the fourth copper foil layer 310d in this embodiment, in other unillustrated embodiments, the copper foil can also be welded The second copper foil layer 310b and the fourth copper foil layer 310d are bonded together in a manner, and the adhesive 320 at this time is molten copper foil. Here, the above-mentioned joining methods should still belong to the examples covered by the present invention.

Next, please refer to FIG. 3B , forming a plurality of first through holes 332 extending from the first copper foil layer 310 a to the third copper foil layer 310 c. That is, the first through hole 332 at least penetrates through the first copper foil layer 310a, the second copper foil layer 310b, the fourth copper foil layer 310d and the third copper foil layer 310c. In this embodiment, the method of forming the first through hole 332 includes mechanical drilling.

Next, please refer to FIG. 3C , press the first insulating layer 350a and the first conductive layer 342 on the first insulating layer 350a on the first copper foil layer 310a, and press the second insulating layer 350b and the second insulating layer 350b at the same time. The second conductive layer 344 on the insulating layer 350b is on the third copper foil layer 310c. In this embodiment, the first insulating layer 350a and the second insulating layer 350b face the first copper foil layer 310a and the third copper foil layer 310c respectively, wherein when pressing, part of the first insulating layer 350a and the second The insulating layer 350b is filled in the first through hole 332 to fill up the first through hole 332 . In addition, the material of the first conductive layer 342 and the second conductive layer 344 is copper, for example.

In particular, in this embodiment, the thickness of the first insulating layer 350a plus the thickness of the first conductive layer 342 is greater than the thickness of the first copper foil layer 310a plus the thickness of the second copper foil layer 310b. Wherein, the thickness of the first insulating layer 350 a is, for example, 40 micrometers (μm), and the thickness of the first conductive layer 342 is, for example, 18 micrometers (μm). Similarly, the thickness of the second insulating layer 350b plus the thickness of the second conductive layer 344 is greater than the thickness of the third copper foil layer 310c plus the thickness of the fourth copper foil layer 310d. Wherein, the thickness of the second insulating layer 350b is substantially the same as that of the first insulating layer 350a, which is, for example, 40 micrometers (μm). The thickness of the second conductive layer 344 is substantially the same as that of the first conductive layer 342 , which is, for example, 18 micrometers (μm).

Next, referring to FIG. 3D , a plurality of second through holes 334 extending from the first conductive layer 342 to the second conductive layer 344 are formed, wherein the second through holes 334 at least penetrate through the first conductive layer 342 , the first insulating layer 350a, The first copper foil layer 310 a , the second copper foil layer 310 b , the fourth copper foil layer 310 d and the third copper foil layer 310 c , the second insulating layer 350 b and the second conductive layer 344 . In addition, the second through hole 334 can be used to assist in the subsequent removal of the adhesive 320 , that is, to remove the area where the second thin copper layer 310b and the fourth copper foil layer 310d are combined. In general, a plurality of metal patterns (not shown) are usually formed on the first conductive layer 342 and the second conductive layer 344 , and the purpose of the metal patterns is to serve as reference points for positioning and alignment in the process. That is to say, the metal pattern on the first conductive layer 342 and the second conductive layer 344 can be used as a reference for positioning and aligning with the first copper foil layer 310a and the third copper foil layer 310c, and can also be used as a reference for matching with the subsequent fifth copper foil layer 310a and the third copper foil layer 310c. The positioning and alignment reference of the foil layer 310e (please refer to FIG. 3G ).

Next, referring to FIG. 3E , the first conductive layer 342 and the second conductive layer 344 are patterned to form a first wiring layer 342 a and a second wiring layer 344 a. Wherein, the method for patterning the first conductive layer 342 and the second conductive layer 344 includes a photolithographic etching process. In particular, since the first conductive layer 342 and the second conductive layer 344 of this embodiment are respectively pressed on the first insulating layer 350a and the second insulating layer 350b by means of pressing, and are patterned And the first circuit layer 342a and the second circuit layer 344a are formed. Therefore, compared with known circuit layers formed by electroplating, the first circuit layer 342a and the second circuit layer 344a of this embodiment have better copper thickness uniformity. In addition, since the first copper foil layer 310a, the second copper foil layer 310b, the third copper foil layer 310 and the fourth copper foil layer 310d in this embodiment are all embedded in the first insulating layer 350a and the second insulating layer 350a due to thermocompression. In the insulating layer 350b, therefore, when the first conductive layer 342 and the second conductive layer 344 are patterned, external impurities or chemical contamination can be avoided, and the first copper foil layer 310a, the second copper foil layer 310b, and the third copper foil layer 310a can be maintained. The size and thickness of the copper foil layer 310 and the fourth copper foil layer 310d.

Next, referring to FIG. 3F , the adhesive 320 is removed to form a first circuit substrate 360 a and a second circuit substrate 360 b which are separated from each other. In this embodiment, the aforementioned second through hole 334 can be used to assist in removing the adhesive 320 . That is to say, the formation of the second through hole 334 can destroy the adhesive force between the adhesive 320 and the second copper foil layer 310b and the fourth copper foil layer 310d, so the adhesive 320 can be easily removed. In addition, the method of removing the adhesive 320 is, for example, mechanical drilling or milling. It is worth mentioning that in this embodiment, since the adhesive 320 is only partially bonded between the second copper foil layer 310b and the fourth copper foil layer 310d, compared with the known method of removing the circuit layer and the metal substrate, For a large amount of colloid, the step of removing the adhesive 320 in this embodiment is relatively simple and the process difficulty is relatively low, which can improve the process yield.

In this embodiment, the first circuit substrate 360 a and the second circuit substrate 360 b formed after removing the adhesive 320 are symmetrical structures. Wherein, the first circuit substrate 360a sequentially includes a first circuit layer 342a, a first insulating layer 350a, a first copper foil layer 310a and a second copper foil layer 310b. The second circuit substrate 360b sequentially includes a second circuit layer 344a, a second insulating layer 350b, a third copper foil layer 310c, and a fourth copper foil layer 310d. In the following, for the convenience of description, only the first circuit substrate 360a is taken as an example to carry out subsequent fabrication of the circuit substrate.

Next, referring to FIG. 3G , the second copper foil layer 310b is removed, and the third insulating layer 350c and the fifth copper foil layer 310e on the third insulating layer 350c are pressed onto the first wiring layer 342a. In this embodiment, the method of removing the second copper foil layer 310b is, for example, a lift-off method, which means that the second copper foil layer 310b is peeled off the first copper foil layer 310a by means of lift-off. In addition, the third insulating layer 350c and the fifth copper foil layer 310e are laminated on the first circuit layer 342a, so that the first circuit layer 342a becomes an internal circuit layer. That is, the first circuit layer 342a is a circuit layer buried between the third insulating layer 350c and the first insulating layer 350a. In addition, laminating the fifth copper foil layer 310e on the first circuit layer 342a is based on the metal pattern (not shown) on the first circuit layer 342a (the original first conductive layer 342), which can ensure that the first copper foil The foil layer 310a, the first circuit layer 342a and the fifth copper foil layer 310e have a preferred alignment accuracy.

Generally speaking, the thickness of the fifth copper foil layer 310e is relatively thin, for example, 3 micrometers (μm), so when the fifth copper foil layer 310e is to be laminated, it is usually added on the fifth copper foil layer 310e. Another thicker copper foil layer (not shown), the thickness of which is, for example, 12 micrometers (μm), can prevent the bending phenomenon of the fifth copper foil layer 310e after lamination, so as to keep the first lamination after lamination. Fifth, the surface flatness of the copper foil layer 310e. Afterwards, after lamination, the thicker copper foil layer is peeled off, leaving the thinner fifth copper foil layer 310e for subsequent processes.

In short, the third insulating layer 350c and the fifth copper foil layer 310e located on the third insulating layer 350c in this embodiment are laminated on the first wiring layer 342a after the adhesive 320 is removed. However, the present invention does not limit the order of the steps of laminating the third insulating layer 350 c and the fifth copper foil layer 310 e thereon and removing the adhesive 320 . In other embodiments, the third insulating layer 350c and the fifth copper foil layer 310e on the third insulating layer 350c may also be laminated on the first circuit layer 342a before removing the adhesive 320 .

In detail, as shown in FIG. 4A , the third insulating layer 350c and the fifth copper foil layer 310e located on the third insulating layer 350c can be pressed first on the first circuit layer 342a, and the fourth insulating layer can be pressed simultaneously. 350d and the sixth copper foil layer 310f on the fourth insulating layer 350d are on the second circuit layer 344a. Next, as shown in FIG. 4B , the adhesive 320 , the second copper foil layer 310 b and the fourth copper foil layer 310 d are removed to form a third circuit substrate 400 c and a fourth circuit substrate 400 d separated from each other. Wherein, the third circuit substrate 400c and the fourth circuit substrate 400d formed after removing the adhesive 320, the second copper foil layer 310b and the fourth copper foil layer 310d have a symmetrical structure, and the third circuit substrate 400c is sequentially It includes the fifth copper foil layer 310e, the third insulating layer 350c, the first circuit layer 342a, the first insulating layer 350a and the first copper foil layer 310a. Similarly, the fourth circuit substrate 400d sequentially includes the sixth copper foil layer 310f, the fourth insulating layer 350d, the second circuit layer 344a, the second insulating layer 350b and the third copper foil layer 310c. In other words, the steps of laminating the insulating layer and the copper foil layer thereon on the circuit layer and removing the adhesive 320 can be selectively adjusted according to the process requirements. Therefore, the above-mentioned FIG. 3F to FIG. This is the limit.

So far, the fabrication of the first circuit substrate 400a has been completed, wherein the first circuit substrate 400a sequentially includes the fifth copper foil layer 310e, the third insulating layer 350c, the first circuit layer 342a, the first insulating layer 350a and the first copper foil Layer 310a.

Next, referring to FIG. 3H , a drilling process is performed on the fifth copper foil layer 310e and the first copper foil layer 310a to form a plurality of first blind holes 412 extending from the fifth copper foil layer 310e to the first wiring layer 342a. , and a plurality of second blind holes 414 extending from the first copper foil layer 310a to the first wiring layer 342a. Wherein, the first blind hole 412 and the second blind hole 414 expose part of the first circuit layer 342a. In this embodiment, the drilling process is, for example, laser drilling, which means that the first blind hole 412 and the second blind hole 414 are formed by laser ablation.

Next, please refer to FIG. 3I, forming a chemical copper layer 420 in the first blind hole 412 and the second blind hole 414, wherein the chemical copper layer 420 connects the fifth copper foil layer 310e and the first wiring layer 342a and connects the first copper foil layer 310a and the first circuit layer 342a. Specifically, in this embodiment, the chemical copper layer 420 covers the fifth copper foil layer 310e, the first blind hole 412, the first copper foil layer 310a and the second blind hole 414, and the fifth copper foil layer 310e passes through The chemical copper layer 420 is electrically connected to the first circuit layer 342a, and the first copper foil layer 310a is electrically connected to the first circuit layer 342a through the chemical copper layer 420 . In addition, the method of forming the chemical copper layer 420 is, for example, performing an electroless plating process.

Next, please refer to FIG. 3J, form a first patterned dry film photoresist layer 432 on the fifth copper foil layer 310e, and form a second patterned dry film photoresist layer 434 on the first copper foil layer 310a. Wherein, the first patterned dry film photoresist layer 432 at least exposes the first blind hole 412 , and the second patterned dry film photoresist layer 434 at least exposes the second blind hole 414 . Specifically, in this embodiment, the first patterned dry film photoresist layer 432 exposes the chemical copper layer 420 located in the first blind hole 412 and the chemical copper layer 420 located on a part of the fifth copper foil layer 310e Layer 420. The second patterned dry film photoresist layer 434 exposes the chemical copper layer 420 in the second blind hole 414 and the chemical copper layer 420 on a portion of the first copper foil layer 310e.

Next, please refer to FIG. 3K, an electroplated copper layer 440 is formed at least in the first blind hole 412 and the second blind hole 414, wherein the electroplated copper layer 440 fills the first blind hole 412 and the second blind hole 414, and covers the part Chemical copper layer 420 . In this embodiment, the first patterned dry film photoresist layer 432 and the second patterned dry film photoresist layer 434 are used as masks for electroplating to adopt via filling plating ) to form an electroplated copper layer 440 in the first blind hole 412, in the second blind hole 414 and not covering the first patterned dry film photoresist layer 432 and the second patterned dry film photoresist layer 434 on the chemical copper layer 420 .

Next, please refer to FIG. 3L, remove the first patterned dry film photoresist layer 432 and the part of the chemical copper layer 420 and part of the fifth copper located under the first patterned dry film photoresist layer 432 Foil layer 310e, and removal of the second patterned dry film photoresist layer 434 and part of the chemical copper layer 420 and part of the first copper foil layer located under the second patterned dry film photoresist layer 434 310a. In this way, part of the third insulating layer 350c and part of the first insulating layer 350a are exposed, and the first conductive blind hole structure 412a is formed in the first blind hole 412, and the second conductive blind hole structure is formed in the second blind hole 414. 414a. In this embodiment, the first patterned dry film photoresist layer 432, part of the chemical copper layer 420 and part of the fifth copper foil located under the first patterned dry film photoresist layer 432 are removed. layer 310e, the second patterned dry film photoresist layer 434, and a portion of the chemical copper layer 420 and the first copper foil layer 310a below the second patterned dry film photoresist layer 434, for example is the etching process. So far, the first conductive blind hole structure 412 a and the second conductive blind hole structure 414 a electrically connected to the first circuit layer 342 a have been formed.

Next, referring to FIG. 3M , a first protective layer 452 is formed on the third insulating layer 350c, and a second protective layer 454 is formed on the first insulating layer 350a. In this embodiment, the first protective layer 452 covers the third insulating layer 350c and the first conductive blind via structure 412a exposed on the third insulating layer 350c, so as to protect the pattern integrity of the first conductive blind via structure 412a. Similarly, the second protection layer 454 covers the first insulating layer 350a and the second conductive blind via structure 414a exposed on the first insulating layer 350a to protect the pattern integrity of the second conductive blind via structure 414a. In addition, the method of forming the first protection layer 452 and the second protection layer 454 is, for example, screen printing, and the material of the first protection layer 452 and the second protection layer 454 is, for example, ink.

Next, referring to FIG. 3N , a grinding process is performed to remove part of the first protective layer 452 to expose the surface of the first conductive blind via structure 412a, and remove part of the second protective layer 454 to expose the first conductive blind via. The surface of structure 412a. At this time, the surface of the first passivation layer 452 is substantially aligned with the surface of the first conductive blind via structure 412a, and the surface of the second passivation layer 454 is substantially flush with the surface of the second conductive blind via structure 414a.

Next, please refer to FIG. 3O , remove the remaining first protective layer 452 and second protective layer 454 to expose a part of the third insulating layer 350c, the first conductive blind hole structure 412a exposed on the third insulating layer 350c, Part of the first insulating layer 350a and the second conductive blind hole structure 414a exposed on the first insulating layer 350a. In this embodiment, the purpose of forming the first protective layer 452 and the second protective layer 454, performing the grinding process, and removing the first protective layer 452 and the second protective layer 454 is to make the first conductive blind via The surface of the structure 412a and the surface of the second conductive blind via structure 414a have a preferred surface flatness, which is beneficial to the subsequent chip packaging process.

Next, referring to FIG. 3P , a first solder resist layer 462 is formed on the third insulating layer 350c, and a second solder resist layer 464 is formed on the first insulating layer 350a. In this embodiment, the first solder resist layer 462 has a plurality of first openings 462a, wherein the first openings 462a expose a part of the first conductive blind via structure 412a, which can be used as bonding pads. The second solder resist layer 464 has a plurality of second openings 464a, wherein the second openings 464a expose part of the second conductive blind via structure 414a, which can be used as bonding pads. So far, the fabrication of the circuit substrate 300 has been completed.

The part of the first conductive blind hole structure 412a exposed by the first opening 462a of the first solder resist layer 462 can be used as a bonding pad, while the part of the second conductive blind hole structure 412a exposed by the second opening 464a of the second solder resist layer 464 The blind hole structure 414a can be used as a bonding pad. In this way, when the chip (not shown) is electrically connected to the bonding pad by wire bonding or flip-chip bonding, and the chip is covered in the glue (not shown) by the glue filling mold, the chip packaging process can be completed . In other words, the circuit substrate 300 of this embodiment is suitable as a chip package carrier.

In short, since the first copper foil layer 310a and the third copper foil layer 310c do not need to be supported by the metal substrate in this embodiment, compared with the known technology, the manufacturing method of the circuit substrate 300 in this embodiment can be effectively Reduce production costs. In addition, in this embodiment, the first circuit layer 342a and the second circuit layer are formed by laminating the first conductive layer 342 and the second conductive layer 344, and then patterning the first conductive layer 342 and the second conductive layer 344. 344a. Compared with known circuit layers formed by electroplating, the first circuit layer 342a and the second circuit layer 344a of this embodiment have better copper thickness uniformity. In addition, in this embodiment, the first circuit layer 342a (the original first conductive layer 342 ) is used as the positioning and alignment reference of the first copper foil layer 310a and the fifth copper foil layer 310e. In this way, the alignment accuracy of the circuit substrate 300 can be effectively improved, so that the formed circuit substrate 300 has optimal production yield and reliability.

To sum up, in the present invention, the surroundings of the two metal layers are bonded to form a sealing area. After the lamination step of the insulating layer on both sides and the conductive layer on both sides is completed, the two metal layers are separated. Therefore, compared with the known technology, the manufacturing method of the circuit substrate of the present invention does not need to use a metal substrate as a supporting carrier, which means that there is no core circuit substrate, which can effectively reduce the production cost of the circuit substrate and improve the circuit performance. increase the reliability of the substrate and effectively reduce the time for making circuit substrates. In addition, the present invention does not need to use a large amount of colloid to fix the metal substrate and the circuit layer, so the circuit substrate manufacturing method of the present invention does not need to face the problem of removing a large amount of colloid layer, which can effectively reduce the process difficulty and process steps. In addition, due to the present invention, the conductive layer can also be pressed by pressing, and then the circuit layer is formed by patterning the conductive layer.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the claims.

Claims (16)

1. A method for manufacturing a circuit substrate, comprising: bonding the peripheries of the two metal layers to form a bonding area; forming at least one through hole passing through the bonding area; forming two insulating layers on the two metal layers, and forming two conductive layers on the two insulating layers; pressing the two insulating layers and the two conductive layers onto the two metal layers, wherein the two metal layers joined together are embedded in the two insulating layers, and the two insulating layers are filled in the through holes; and The bonding regions of the two metal layers are separated to form two separate circuit substrates. 2. The manufacturing method of the circuit substrate as claimed in claim 1, wherein the method for joining the peripheries of the two metal layers comprises electric welding, spot welding or passing through an adhesive, and the material of the adhesive includes cyanoacrylate or polypropylene resin. 3. The manufacturing method of circuit substrate as claimed in claim 1, further comprising: After laminating the two insulating layers and the two conductive layers on the two metal layers, removing part of the two insulating layers and part of the two conductive layers to form a plurality of blind holes exposing the two metal layers; forming conductive material in the plurality of blind holes and on the two conductive layers that have not been removed; and After separating the bonding area of the two metal layers, the conductive material, the metal layer and the conductive layer are patterned. 4. The manufacturing method of circuit substrate as claimed in claim 1, further comprising: After laminating the two insulating layers and the two conductive layers on the two metal layers, removing part of the two insulating layers and part of the two conductive layers to form a plurality of blind holes exposing the two metal layers; thinning the two conductive layers; forming two electroplating seed layers on the thinned two conductive layers and in the plurality of blind holes; exposing the metal layer after separating the bonding area of the two metal layers; respectively forming a patterned photoresist layer on the electroplating seed layer and on the exposed metal layer; electroplating the plurality of electroplating seed layers using the plurality of patterned photoresist layers as a mask; and The plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers are removed. 5. The manufacturing method of circuit substrate as claimed in claim 1, further comprising: After laminating the two insulating layers and the two conductive layers onto the two metal layers, patterning the two conductive layers to form the two patterned conductive layers; forming another two insulating layers on the two patterned conductive layers, and forming another two conductive layers on the other two insulating layers; pressing the plurality of insulating layers and the other two conductive layers, and the two patterned conductive layers are embedded in the plurality of insulating layers; After separating the bonding area of the two metal layers, removing part of the plurality of insulating layers, part of the metal layer and part of the other conductive layer to form a plurality of blind holes exposing the patterned conductive layer; forming conductive material in the plurality of blind holes and on the metal layer and the other conductive layer that were not removed; and patterning the conductive material, the metal layer and the other conductive layer. 6. The manufacturing method of circuit substrate as claimed in claim 1, further comprising: After laminating the two insulating layers and the two conductive layers onto the two metal layers, patterning the two conductive layers to form the two patterned conductive layers; forming another two insulating layers on the two patterned conductive layers, and forming another two conductive layers on the other two insulating layers; pressing the plurality of insulating layers and the other two conductive layers, and the two patterned conductive layers are embedded in the plurality of insulating layers; After separating the bonding area of the two metal layers, removing part of the plurality of insulating layers, part of the metal layer and part of the other conductive layer to form a plurality of blind holes exposing the patterned conductive layer; removing the other conductive layer and the metal layer to expose the plurality of insulating layers; forming two electroplating seed layers on the plurality of insulating layers and in the plurality of blind holes; forming two patterned photoresist layers on the two electroplating seed layers; electroplating the plurality of electroplating seed layers using the plurality of patterned photoresist layers as a mask; and The plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers are removed. 7. The manufacturing method of circuit substrate as claimed in claim 1, further comprising: After laminating the two insulating layers and the two conducting layers onto the two metal layers, removing part of the two insulating layers and part of the two conducting layers to form a plurality of first blind holes exposing the two metal layers; removing the two conductive layers to expose the two insulating layers; forming two electroplating seed layers on the two insulating layers and in the plurality of first blind holes; forming two patterned photoresist layers on the plurality of electroplating seed layers; Electroplating the plurality of electroplating seed layers using the plurality of patterned photoresist layers as a mask; removing the plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers to form two patterned conductive layers on the two insulating layers and Multiple conductive via structures; forming another two insulating layers on the two patterned conductive layers, and forming another two conductive layers on the other two insulating layers; pressing the plurality of insulating layers and the other two conductive layers, and the two patterned conductive layers are embedded in the plurality of insulating layers; After separating the bonding area of the two metal layers, removing part of the plurality of insulating layers, the metal layer and the other conductive layer to form a plurality of second blind holes exposing the patterned conductive layer; forming another two electroplating seed layers on the other two insulating layers, one end of the plurality of first blind holes and in the plurality of second blind holes; forming another two patterned photoresist layers on the other two electroplating seed layers; Using the other two patterned photoresist layers as a mask, electroplating the other two electroplating seed layers; and The other two patterned photoresist layers and the portion of the other two electroplating seed layers covered by the other two patterned photoresist layers are removed. 8. The manufacturing method of a circuit substrate as claimed in claim 1, wherein the two metal layers respectively comprise a first copper foil layer and a second copper foil layer, and the thickness of each second copper foil layer is substantially greater than that of each of the first copper foil layers. The thickness of a copper foil layer, the plurality of second copper foil layers are bonded to each other. 9. The manufacturing method of circuit substrate as claimed in claim 8, further comprising: After laminating the two insulating layers and the two conductive layers on the two metal layers, patterning the two conductive layers to form a first patterned conductive layer and a second patterned conductive layer; forming a plurality of first through holes extending from the first patterned conductive layer to the second patterned conductive layer; removing the second copper foil layer after separating the bonding area of the two metal layers; forming a first insulating layer on the first patterned conductive layer, and forming a first conductive layer on the first insulating layer; pressing the first insulating layer and the first conductive layer, and the first patterned conductive layer is embedded in the insulating layer and the first insulating layer; removing part of the insulating layer, the first insulating layer, part of the first copper foil layer and part of the first conductive layer to form a plurality of first blind holes exposing the first patterned conductive layer; respectively forming an electroplating seed layer on the unremoved first copper foil layer and in the plurality of first blind holes and on the unremoved first conductive layer and in the plurality of first blind holes; forming two patterned photoresist layers on the plurality of electroplating seed layers; Using the plurality of patterned photoresist layers as a mask, electroplating the plurality of electroplating seed layers to form a plurality of conductive blind hole structures in the plurality of first blind holes; and The plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers are removed. 10. The manufacturing method of a circuit substrate as claimed in claim 9, wherein forming the first insulating layer on the first patterned conductive layer, and forming the first conductive layer on the first insulating layer are separating the After the bonding area of the second metal layer. 11. The manufacturing method of a circuit substrate as claimed in claim 9, wherein forming the first insulating layer on the first patterned conductive layer, and forming the first conductive layer on the first insulating layer are separating the before the bonding area of the second metal layer. 12. The manufacturing method of circuit substrate as claimed in claim 11, further comprising: Forming the first insulating layer on the first patterned conductive layer, and forming the first insulating layer on the first insulating layer, forming a second insulating layer on the second patterned conductive layer, and forming the first Two conductive layers are on the second insulating layer. 13. The manufacturing method of circuit substrate as claimed in claim 9, further comprising: After removing the plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers, forming a first protective layer on the first insulating layer, and forming a second protection layer on the insulating layer, wherein the first protection layer and the second protection layer cover the plurality of conductive blind via structures; performing a grinding process to remove part of the first passivation layer and part of the second passivation layer to expose the plurality of conductive blind via structures; The remaining first protection layer and the second protection layer are removed. 14. The manufacturing method of the circuit substrate as claimed in claim 9, further comprising: After removing the plurality of patterned photoresist layers and the portions of the plurality of electroplating seed layers covered by the plurality of patterned photoresist layers, a first solder resist layer is formed on the first insulating layer , and forming a second solder resist layer on the insulating layer, wherein the first solder resist layer has a plurality of first openings, the second solder resist layer has a plurality of second openings, the plurality of first openings and the plurality of first openings A second opening exposes part of the conductive blind via structure. 15. A circuit substrate manufactured by the method for manufacturing a circuit substrate according to claim 3, comprising: patterned metal layer; patterned conductive layer; an insulating layer located between the patterned metal layer and the patterned conductive layer; and The conductive material is located in the blind holes, the blind holes penetrate the insulating layers, and the conductive material is electrically connected to the patterned metal layer and the patterned conductive layer. 16. A circuit substrate manufactured by the method for manufacturing a circuit substrate according to claim 5, comprising: patterned metal layer; patterned conductive layer; a patterned conductive layer located between the patterned metal layer and the patterned conductive layer; two insulating layers, respectively located between the patterned metal layer and the patterned conductive layer and between the patterned conductive layer and the patterned conductive layer; and The conductive material is located in a plurality of blind holes, the plurality of blind holes penetrate the plurality of insulating layers, and the conductive material is electrically connected between the patterned metal layer and the patterned conductive layer and the patterned conductive layer. layer and the patterned conductive layer.

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