CN102176186A - Current mirror evaluation dynamic circuit - Google Patents
Current mirror evaluation dynamic circuit Download PDFInfo
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- CN102176186A CN102176186A CN2011100666907A CN201110066690A CN102176186A CN 102176186 A CN102176186 A CN 102176186A CN 2011100666907 A CN2011100666907 A CN 2011100666907A CN 201110066690 A CN201110066690 A CN 201110066690A CN 102176186 A CN102176186 A CN 102176186A
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Abstract
本发明公开了一种电流镜求值动态电路，包括：输入网络、一级电流镜子电路、二级电流镜子电路，所述输入网络通过所述一级电流镜子电路连接保持管，所述保持管的栅极直接连接二级电流镜子电路，保持管的漏极通过连接反相器作为整个电路的输出端；输入网络的电源端直接连接工作电压VDD。本发明提高了求值速度；省去输入级中的预充管可以增大输入级的下拉电流，避免电流过小而影响电路的工作。
The invention discloses a current mirror evaluation dynamic circuit, comprising: an input network, a primary current mirror circuit, and a secondary current mirror circuit, the input network is connected to a holding tube through the primary current mirror circuit, and the holding tube The gate of the gate is directly connected to the secondary current mirror circuit, and the drain of the holding tube is connected to the inverter as the output terminal of the whole circuit; the power supply terminal of the input network is directly connected to the working voltage VDD. The present invention improves the evaluation speed; omits the pre-charge tube in the input stage, can increase the pull-down current of the input stage, and avoids the circuit operation being affected by the current being too small.
Description
Technical field
The present invention relates to the dynamic circuit technical field in the cmos circuit, particularly a kind of current mirror evaluation dynamic circuit.
Background technology
Traditional CMOS static circuit is wanted driving N MOS and PMOS transistor simultaneously because of input signal, and has intrinsic speed defective.The input signal of CMOS dynamic circuit only needs driving N MOS (or PMOS) transistor, so have great advantage with respect to static circuit on speed and area
[1]Yet, for big fan-in or the door, as shown in Figure 1, the conventional dynamic circuit
[2]Dynamic node (DYN) electric capacity can increase along with the increase of fan-in, so just reduced the speed of the drop-down dynamic node of fan-in network, it can't be pulled down to effective low level when situation is serious.Simultaneously, serious Leakage Current requires bigger holding tube (Keeper)
[3], so also increased the competition electric current when drop-down, further reduced speed.
Tamer Cakici and Kaushik Roy have proposed a kind of current mirror evaluation dynamic circuit structure at big fan-in or door
[4]As shown in Figure 2, traditional dynamic node is separated, and the two-stage current mirror determines whether output node is charged by the pull-down current that detects fan-in network.
This structure has kept preliminary filling pipe and the input evaluation network in the conventional dynamic circuit, and holding tube (Keeper) then no longer needs.After dynamic node was separated, N2 can regard the dynamic node (output dynamic node) relevant with output as.Its concrete course of work is as follows:
During preliminary filling, the input and output dynamic node all is charged to high level in advance, and the N1 node is charged to low level in advance with the close current mirror.Like this, promptly require input signal must keep low level, otherwise can cause direct-current short circuit in the preliminary filling stage.
During evaluation, if in the input signal high level is arranged, then current mirror can detect pull-down current (this electric current may be very little).Mirror by first order current mirror (M1 and M2) is to amplification, and output dynamic node N2 is by drop-down, and second level current mirror (M3 and M4) can directly be given output node (OUT) charging simultaneously, finally makes to export to become high level.M6 closes the series arm of M2 and M3 after output uprises.
During evaluation, if input signal is a low level all, then current mirror is not worked.This moment, M6 often opened, and the feedback that M6 and M3 constitute has guaranteed that N2 is always high level.
In order to guarantee that current mirror can operate as normal change to output fully when drop-down, it is zero metal-oxide-semiconductor (otherwise the N1 node voltage causes M1 to close after dropping to certain level) that M1 should adopt threshold voltage
[5]The M1 pipe should be got minimum widith, and M2 then should be suitably big, to improve the pull-down current to N2.
The reduction of output dynamic node electric capacity has improved evaluation speed.And when the evaluate phase input signal all was low level, the leakage current of fan-in network made the N1 node voltage rise to a certain intermediate level, had so just improved the threshold voltage of NMOS pipe in the fan-in network, thereby had improved noise margin.
In this current mirror evaluation dynamic circuit structure, still there are some problems:
1, closing of the drop-down and M6 pipe of N2 point successively carried out, because in evaluate phase, closing of M6 pipe is that feedback by to output node obtains, and this feedback can reduce power consumption to a certain extent, but has reduced evaluation speed.
2, be the electric current of fan-in network owing to what determine output state, so the input dynamic node has not had necessity of existence, preliminary filling Mpre1 pipe in the current mirror evaluation structure can save, and the existence of preliminary filling Mpre1 pipe can make the too small circuit operate as normal that influences of pull-down current of fan-in network.
List of references cited above is as follows:
[1]K.Bernstein，K.Carrig，C.Durham，P.Hansen，D.Hogenmiller，E.Nowak，and?N.Rohrer，High?Speed?CMOS?Design?Styles.Boston，MA：Kluwer，1998.
[2]A.S.Sedra?and?K.C.Smith，Microelectronic?Circuits，Fourth?Edition，New?York：Oxford，1998.
[3]A.Alvandpour?et.al.A?Conditional?Keeper?Technique?for?Sub-0.13μ?Wide?Dynamic?Gates，Symp.on?VLSI?Circuits，pp.29-30，2001.
[4]Tamer?Cakici?and?Kaushik?Roy，Current?Mirror?Evaluation?Logic：A?New?Circuit?Style?for?High?Fan-in?Dynamic?Gates.Solid-State?CircuitsConference，2002.
[5]Sherif?M.Sharroush，Yasser?S.Abdalla，Ahmed?A.Dessouki，and?El-Sayed?A.El-Badawy.A?Novel?Technique?for?Speeding?up?Domino?CMOS?Circuits?Containing?a?Long?Chain?of?NMOS?Transistors.2008International?Conference?on?Electronic?Design，Malaysia，2008.
Summary of the invention
(1) technical matters that will solve
The technical problem to be solved in the present invention is: how to improve the evaluation speed of current mirror evaluation dynamic circuit, and the situation that can avoid influencing the circuit operate as normal owing to the pull-down current of fan-in network is too small takes place.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of current mirror evaluation dynamic circuit, comprise: fan-in network, one-level current mirror electronic circuit, secondary current mirror electronic circuit, described fan-in network connects holding tube by described one-level current mirror electronic circuit, the grid of described holding tube directly connects secondary current mirror electronic circuit, and the drain electrode of holding tube is by connecting the output terminal of phase inverter as entire circuit;
Described one-level current mirror electronic circuit comprises: three NMOS pipes: M1, M5 and M2, the output terminal of described fan-in network connects the drain terminal of described M1, the drain terminal of described M5 is as dynamic node, the drain terminal that connects described holding tube, the drain terminal of M2 connects described secondary current mirror electronic circuit, and described one-level current mirror electronic circuit also connects the drain terminal of the first preliminary filling pipe;
Described secondary current mirror electronic circuit comprises: two PMOS pipes: M3 and M4, the drain terminal of described M3 connects the drain terminal of M2, the source end of M3 connects the drain terminal of M6, the grid of described holding tube connects the drain terminal of M4, the drain terminal of the connection second preliminary filling pipe, the grid that connects M6, and being connected to output terminal by NMOS transfer tube M7, described two preliminary filling pipes are the NMOS pipe;
The source end ground connection of described M1, M2, M5, the first preliminary filling pipe and the second preliminary filling pipe;
The grid of the described first preliminary filling pipe, the second preliminary filling pipe and M7 is a clock signal terminal;
The source termination operating voltage VDD of described holding tube, M4 and M6.
Wherein, the power end of described fan-in network directly connects operating voltage VDD.
(3) beneficial effect
In the current mirror evaluation dynamic circuit structure of the present invention, fan-in network is directly controlled holding tube by current mirror.When input signal decision dynamic node (DYN) will be when drop-down, closing of the drop-down and holding tube of DYN is synchronous (rather than DYN earlier drop-down close Keeper by feedback again), so just avoid the competition electric current between Keeper and the M5, improved evaluation speed; Save the pull-down current that preliminary filling pipe in the input stage can increase input stage, avoid electric current too small and influence the work of circuit.
Description of drawings
Fig. 1 is big fan-in of tradition or door dynamic circuit structural drawing;
Fig. 2 is existing a kind of current mirror evaluation dynamic circuit structural drawing;
Fig. 3 is a kind of current mirror evaluation dynamic circuit structural drawing of the embodiment of the invention;
Fig. 4 is that horizontal ordinate is the time at the output delay comparative graph of two kinds of current mirror evaluation circuits among Fig. 2 of 8 inputs or door and Fig. 3, and unit is ns, and ordinate is a voltage, and unit is V;
Fig. 5 is that horizontal ordinate is the time at the output delay comparative graph of two kinds of current mirror evaluation circuits among Fig. 2 of 16 inputs or door and Fig. 3, and unit is ns, and ordinate is a voltage, and unit is V.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
The structure of current mirror evaluation circuit of the present invention as shown in Figure 3,
Comprise: fan-in network, one-level current mirror electronic circuit, secondary current mirror electronic circuit, described fan-in network connects holding tube by described one-level current mirror electronic circuit, the grid of described holding tube directly connects secondary current mirror electronic circuit, and the drain electrode of holding tube is by connecting the output terminal of phase inverter as entire circuit.
Described one-level current mirror electronic circuit comprises: three NMOS pipes: M1, M5 and M2, the output terminal of described fan-in network connects the drain terminal of described M1, the drain terminal of described M5 is as dynamic node, the drain terminal that connects described holding tube, the drain terminal of M2 connects secondary current mirror electronic circuit, and one-level current mirror electronic circuit also connects the drain terminal of the first preliminary filling pipe.
Described secondary current mirror electronic circuit comprises: two PMOS pipes: M3 and M4, the drain terminal of described M3 connects the drain terminal of M2, the source end of M3 connects the drain terminal of M6, the grid of described holding tube connects the drain terminal of M4, the drain terminal of the connection second preliminary filling pipe, the grid that connects M6, and being connected to output terminal by NMOS transfer tube M7, described two preliminary filling pipes are the NMOS pipe.
The source end ground connection of described M1, M2, M5, the first preliminary filling pipe and the second preliminary filling pipe.
The grid of the described first preliminary filling pipe, the second preliminary filling pipe and M7 is a clock signal terminal.
The source termination operating voltage VDD of described holding tube, M4 and M6.Wherein, the power end of described fan-in network directly connects operating voltage VDD.
The present invention and circuit shown in Figure 2 have that following some is different:
1, be the electric current of fan-in network owing to what determine output state, so the input dynamic node has not had necessity of existence, the preliminary filling pipe Mpre1 (among Fig. 2) in the primary current mirror evaluation structure has omitted at this, can increase the pull-down current of M1 pipe when evaluation simultaneously.
2, the circuit left side be many inputs or logics, M1, M2 and M5 form first order current mirror, are used to amplify the electric current that flows through M1, dynamic node DYN at this moment can be by directly drop-down, rather than by second level current mirror.
3, the grid N3 of Keeper pipe directly links to each other with second level current mirror (M2, M3, M4), make its need not realize drop-down by the feedback of output node or on draw.
Because dynamic node changes, output node need increase a phase inverter make logically true.
The concrete course of work of entire circuit is as follows:
During preliminary filling, Mpre1 closes current mirror fully, to avoid short-circuit current.Mpre2 is pulled low to low level to the grid of Keeper, and Keeper is charged to DYN, and Keeper reality has also played the preliminary filling effect to the output dynamic node like this.
During evaluation, if in the input signal high level is arranged, then current mirror can detect a less pull-down current, and the mirror by one-level current mirror (M1 and M5) is to amplifying drop-down DYN; Simultaneously, charge for the grid N3 of Keeper by the two-stage current mirror, so that it is closed as early as possible.M6 can close the series arm of M2 and M3 after N3 is charged to high level, to reduce power consumption.
During evaluation, if input signal is a low level all, then current mirror is not worked.This moment, feedback pipe M7 can guarantee that the grid of Keeper is in low level, thereby maintained the high level of DYN.
This new structure is compared with original structure, has further reduced the electric capacity (the N2 node among Fig. 2 and the DYN node among Fig. 3) on the output dynamic node, and DYN make when drop-down Keeper close morning more, thereby improved evaluation speed.Simultaneously, the improvement to noise margin has obtained succession in the original structure.
Identical with primary current mirror evaluation circuit, for guaranteeing that current mirror can operate as normal change to output fully when drop-down, it is zero metal-oxide-semiconductor that M1 should adopt threshold voltage; And M1 should get minimum widith, and M5 should suitably strengthen, to improve the pull-down current to DYN.
Improvement effect is analyzed
Adopt 0.13um technology Hspice emulation primary current mirror evaluation circuit and New type of current mirror evaluation circuit, supply voltage is 1.2V.Input signal simulation worst case promptly has only an input signal for high, and all the other are low.At 8 inputs or door and 16 inputs or door, their output delay situation respectively as shown in Figure 4 and Figure 5.
Two kinds of circuit adopt identical device size: the NMOS pipe (M2 among Fig. 2 and the M5 among Fig. 3) of drop-down output dynamic node is got 3 times of minimum widiths, PMOS pipe (corresponding to M4 among Fig. 2) in the output phase inverter is got 2 times of minimum widiths, and all the other metal-oxide-semiconductors are all got minimum widith.
Quantitative comparison for two kinds or door performance sees Table 1.
The quantitative comparison of two kinds in table 1 or door performance
For 8 inputs or door, new-type circuit can improve 57.1% with speed, on the basis that increases certain power consumption the power consumption lagged product is reduced by 31.6%; For 16 inputs or door, new-type circuit can improve 25.4% with speed, but the power consumption lagged product also can rise 24.2%.As seen, this new structure is to medium scale big fan-in or the door effect that has greatly improved.
Above embodiment only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110066690 CN102176186B (en) | 2011-03-18 | 2011-03-18 | Current mirror evaluation dynamic circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201110066690 CN102176186B (en) | 2011-03-18 | 2011-03-18 | Current mirror evaluation dynamic circuit |
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| CN102176186B CN102176186B (en) | 2013-02-06 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385901A (en) * | 2011-09-20 | 2012-03-21 | 北京大学 | Low power consumption avalanche photo diode (APD) sensitive amplifier |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068070A1 (en) * | 2003-09-26 | 2005-03-31 | Artisan Components, Inc. | I/O buffer with wide range voltage translator |
| US20060214695A1 (en) * | 2005-03-25 | 2006-09-28 | Yolin Lih | Keeper circuits having dynamic leakage compensation |
| CN101276229A (en) * | 2007-03-30 | 2008-10-01 | 奇景光电股份有限公司 | Current Mode Receiver |
| CN101789765A (en) * | 2009-11-25 | 2010-07-28 | 天津南大强芯半导体芯片设计有限公司 | Low power consumption high efficiency operational amplifier circuit and operating method thereof |
-
2011
- 2011-03-18 CN CN 201110066690 patent/CN102176186B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068070A1 (en) * | 2003-09-26 | 2005-03-31 | Artisan Components, Inc. | I/O buffer with wide range voltage translator |
| US20060214695A1 (en) * | 2005-03-25 | 2006-09-28 | Yolin Lih | Keeper circuits having dynamic leakage compensation |
| CN101276229A (en) * | 2007-03-30 | 2008-10-01 | 奇景光电股份有限公司 | Current Mode Receiver |
| CN101789765A (en) * | 2009-11-25 | 2010-07-28 | 天津南大强芯半导体芯片设计有限公司 | Low power consumption high efficiency operational amplifier circuit and operating method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385901A (en) * | 2011-09-20 | 2012-03-21 | 北京大学 | Low power consumption avalanche photo diode (APD) sensitive amplifier |
| CN102385901B (en) * | 2011-09-20 | 2013-10-02 | 北京大学 | Low power consumption avalanche photo diode (APD) sensitive amplifier |
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| CN102176186B (en) | 2013-02-06 |
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