CN102176094A - Liquid crystal display panel and liquid crystal display array substrate - Google Patents

Abstract

The invention discloses a liquid crystal display panel and a liquid crystal display array substrate, wherein the liquid crystal display array substrate comprises a plurality of scanning lines, a plurality of data lines, a plurality of first row pixel units and a plurality of second row pixel units. The second row of pixel units and the first row of pixel units are alternately arranged, and each first row of pixel units is provided with a plurality of first pixel structures which are arranged along a row direction and are respectively and electrically connected with the corresponding scanning lines and the corresponding data lines. Each second row pixel unit is provided with a plurality of second pixel structures which are arranged along the row direction and are respectively and electrically connected with the corresponding scanning lines and the corresponding data lines, wherein the first storage capacitance value of the first storage capacitor of each first pixel structure is larger than the second storage capacitance value of the second storage capacitor of each second pixel structure.

Description

Liquid crystal display panel and liquid crystal display array substrate

technical field

The invention relates to a display device, and in particular to a liquid crystal display panel and a liquid crystal display array substrate.

Background technique

Liquid crystal display, or LCD (Liquid Crystal Display), is a flat and ultra-thin display device, which consists of a certain number of color or black and white pixels, placed in front of the light source or reflective surface. Liquid crystal displays have very low power consumption, so they are favored by the industry and suitable for electronic equipment.

In liquid crystal displays, 2H inversion is a driving method to improve the flickering problem of dot inversion under the dot mask screen. However, on high-resolution panels, the grid delay (Gate delay) causes insufficient charging time, so when the data enters, the gate must be turned on in advance, but when the data line has undergone positive and negative polarity conversion, the charging status of the pixel is very different, so it is easy to cause insufficient charging The problem of display grid or bright and dark lines caused by both.

This shows that above-mentioned existing technology obviously still has inconvenience and defective, and needs to be further improved. In order to solve the above-mentioned problems, related fields have tried their best to seek a solution, but no applicable method has been developed for a long time. Therefore, how to improve the problem of display grids or bright and dark lines is indeed one of the current important research and development topics, and has also become an urgent need for improvement in related fields.

Contents of the invention

Therefore, an aspect of the present invention is to provide a liquid crystal display panel and a liquid crystal display array substrate.

According to an embodiment of the present invention, a liquid crystal display panel includes a first substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel units in a first column, a plurality of pixel units in a second column, a second substrate, and a liquid crystal layer. A plurality of scan lines and a plurality of data lines are arranged on the first substrate, and the data lines and the scan lines are interlaced. A plurality of pixel units in the first column are arranged in parallel on the first substrate, and each pixel unit in the first column has a plurality of first pixel structures arranged along a column direction and electrically connected to corresponding scanning lines and data lines respectively. The pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; a plurality of pixel units in the second row are arranged in parallel on the first substrate, and are arranged alternately with the pixel units in the first row, and each pixel unit in the second row Two rows of pixel units have a plurality of second pixel structures arranged along the column direction and electrically connected to corresponding scanning lines and data lines respectively. Each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitor. storing a capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value. The second substrate is arranged opposite to the first substrate, and the liquid crystal layer is arranged between the first substrate and the second substrate.

According to another embodiment of the present invention, a liquid crystal display array substrate includes a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of pixel units in a first row, and a plurality of pixel units in a second row. A plurality of scanning lines and a plurality of data lines are arranged on the substrate, and the data lines and the scanning lines are interlaced. A plurality of pixel units in the first column are arranged in parallel on the substrate. Each pixel unit in the first column has a plurality of first pixel structures arranged along a column direction and electrically connected to corresponding scanning lines and data lines. Each first pixel structure There is a first storage capacitor, and the first storage capacitor has a first storage capacitance value; a plurality of pixel units in the second row are arranged in parallel on the substrate, and are arranged alternately with these pixel units in the first row, and each pixel unit in the second row There are a plurality of second pixel structures arranged along the column direction and electrically connected to corresponding scanning lines and data lines respectively, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, Wherein the second storage capacitor value is smaller than the first storage capacitor value.

According to yet another embodiment of the present invention, a liquid crystal display panel includes a first substrate, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of pixel units in a first row, a plurality of second A row of pixel units, a second substrate and a liquid crystal layer. The first scanning lines and the second scanning lines are alternately arranged on the first substrate in parallel. The data lines are arranged on the first substrate and intersect with the scan lines. A plurality of pixel units in the first row are arranged in parallel on the first substrate, and each pixel unit in the first row has a plurality of first pixel structures arranged along a row direction and electrically connected to corresponding first scanning lines and data lines, each The first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; a plurality of pixel units in the second row are arranged in parallel on the first substrate and arranged alternately with the pixel units in the first row, Each second row of pixel units has a plurality of second pixel structures, arranged along the row direction, electrically connected to the corresponding second scanning line and data line, each second pixel structure has a second storage capacitor, the second storage The capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value. The second substrate is arranged opposite to the first substrate, and the liquid crystal layer is arranged between the first substrate and the second substrate.

According to yet another embodiment of the present invention, a liquid crystal display array substrate includes a substrate, a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, a plurality of first column pixel units, and a plurality of second column pixel unit. The first scanning lines and the second scanning lines are alternately arranged on the substrate in parallel. The data lines are arranged on the substrate and intersect with the scan lines. A plurality of pixel units in the first row are arranged in parallel on the substrate, each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, electrically connected to the corresponding first scanning line and data line respectively, each first row The pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitance value; a plurality of pixel units in the second row are arranged in parallel on the substrate, and are arranged alternately with the pixel units in the first row, and each second row The pixel unit has a plurality of second pixel structures arranged along the row direction and electrically connected to the corresponding second scanning line and data line respectively. Each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitor. storing a capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value.

According to still another embodiment of the present invention, a liquid crystal display panel includes a first substrate, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of first row pixel units, a plurality of second Two rows of pixel units, a second substrate and a liquid crystal layer. The first scanning lines and the second scanning lines are alternately arranged on the first substrate in parallel. The data lines are arranged on the first substrate and intersect with the scan lines. A plurality of pixel units in the first row are arranged in parallel on the first substrate, and each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, and electrically connected to the corresponding second scanning line and data line respectively, each A first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value. A plurality of pixel units in the second row are arranged in parallel on the first substrate and arranged alternately with the pixel units in the first row. Each pixel unit in the second row has a plurality of second pixel structures arranged in the row direction, respectively electrically The corresponding first scan lines and data lines are connected, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value. The second substrate is arranged opposite to the first substrate, and the liquid crystal layer is arranged between the first substrate and the second substrate.

According to yet another embodiment of the present invention, a liquid crystal display panel liquid crystal display array substrate includes a substrate, a plurality of first scanning lines, a plurality of second scanning lines, a plurality of data lines, a plurality of pixel units in a first row, and a plurality of second row of pixel units. The first scanning lines and the second scanning lines are alternately arranged on the substrate in parallel. The data lines are arranged on the substrate and intersect with the scan lines. A plurality of pixel units in the first row are arranged in parallel on the substrate, each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, electrically connected to the corresponding second scanning line and data line respectively, and each pixel unit in the first row A pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value. A plurality of pixel units in the second row are arranged in parallel on the substrate and arranged alternately with the pixel units in the first row. Each pixel unit in the second row has a plurality of second pixel structures arranged along the row direction and electrically connected to the corresponding The first scan line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitor value, wherein the second storage capacitor value is smaller than the first storage capacitor value.

In summary, compared with the prior art, the technical solution of the present invention has obvious advantages and beneficial effects. Through the above technical solution, considerable technological progress can be achieved, and it has wide industrial application value, which at least has the following characteristics:

1. Adopt the above-mentioned compensation mechanism that the second storage capacitance value is smaller than the first storage capacitance value, so that the holding voltage (holding voltage) of adjacent pixels after being charged through the feedthrough voltage drop is very close, or even the same, thereby improving the display grid questions; and

2. In the case of keeping the voltage the same or very close, naturally there is no problem of bright and dark lines.

Description of drawings

In order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the accompanying drawings are described as follows:

FIG. 1 is a schematic diagram of a liquid crystal display panel according to an embodiment of the present invention;

FIG. 2 is a partial circuit diagram of the pixel array shown in FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a layout diagram of two adjacent pixel structures in FIG. 2;

FIG. 4 is the 2H conversion driving mode matched with the pixel array in FIG. 2;

Fig. 5 shows the display effect when the pixel array in Fig. 4 is driven in a 2H conversion mode;

FIG. 6A is a timing diagram when the pixel array in FIG. 2 is driven in a 2H switching mode according to an embodiment of the present invention;

6B is a timing diagram when the pixel array of the comparative example is driven in a 2H switching mode;

FIG. 7A is a timing diagram when the pixel array in FIG. 2 is driven in a 2H switching mode according to another embodiment of the present invention;

7B is a timing diagram when the pixel array of the comparative example is driven in a 2H switching mode;

FIG. 8 is a partial circuit diagram of the pixel array in FIG. 1 and its matching 3H conversion drive according to another embodiment of the present invention;

FIG. 9 shows the display effect when the pixel array in FIG. 8 is driven in a 3H conversion mode;

FIG. 10 is a partial circuit diagram of the pixel array in FIG. 1 and its matching 2H conversion drive according to yet another embodiment of the present invention;

FIG. 11 shows the display effect of 2V conversion when the pixel array in FIG. 10 is driven in 2H conversion mode.

FIG. 12 is a partial circuit diagram of the pixel array in FIG. 1 and its matched (2H+1) conversion drive according to yet another embodiment of the present invention;

FIG. 13 shows the display effect of dot conversion when the pixel array in FIG. 10 is driven in the (2H+1) conversion mode.

Among them, reference signs

100: Liquid crystal display panel 110: First substrate

120: second substrate 130: liquid crystal layer

200: pixel array 202, 204, 206, 208: scan line

212, 214, 216: data lines 220: first column of pixel units

222: The first pixel structure 230, 250: The second column of pixel units

232: The second pixel structure 240: The first or third column of pixel units

242: The third pixel structure 312: The first storage capacitor

314: The first thin film transistor 316: The first liquid crystal capacitor

322: second storage capacitor 324: second thin film transistor

326: Second liquid crystal capacitor 328: Pixel electrode

332: The third storage capacitor 334: The third thin film transistor

336: the third liquid crystal capacitor 402, 802, 1110, 1300: pixel data signal

412～418, 812～814, 1112～1118, 1312～1318: scanning signal

601, 602, 603, 604, 605, 606, 607, 608: Voltage

920: The first row of pixel units 922: The first pixel structure

930: The second row of pixel units 932: The second pixel structure

1012: the first storage capacitor 1014: the first thin film transistor

1016: the first liquid crystal capacitor 1022: the second storage capacitor

1024: The second thin film transistor 1026: The second liquid crystal capacitor

1102, 1104, 1202: high potential 1103, 1203: low potential

Detailed ways

In order to make the description of the present invention more detailed and complete, reference may be made to the attached drawings and various embodiments described below, and the same numbers in the drawings represent the same or similar elements. On the other hand, well-known elements and steps have not been described in the embodiments in order to avoid unnecessarily limiting the invention.

In the embodiments and scope of the patent application, "a" and "the" may generally refer to a single or a plurality, unless the article is specifically limited in the context.

As used herein, "about," "approximately," or "approximately" is used to modify any quantity that may vary slightly, but which does not alter its essence. Unless otherwise specified in the embodiments, it means that the error range of the numerical value modified by "about", "approximately" or "approximately" is generally allowed within 20%, preferably within 10%. Within , and more preferably within 5%.

FIG. 1 is a schematic diagram of a liquid crystal display panel 100 according to an embodiment of the invention. As shown in FIG. 1 , the liquid crystal display panel 100 includes a first substrate 110 , a second substrate 120 , a liquid crystal layer 130 and a pixel array 200 .

Structurally, the second substrate 120 is disposed opposite to the first substrate 110 , the liquid crystal layer 130 is disposed between the first substrate 110 and the second substrate 120 , and the pixel array 200 is disposed on the first substrate 110 .

Wherein, the first substrate 110 is, for example, a thin film transistor array substrate, and the second substrate is, for example, a color filter substrate. Regarding the specific structure of the second substrate 120 , for example, the second substrate 120 may include an upper substrate, an upper polarizer, a color filter, and a common electrode. On the other hand, regarding the pixel array 200 on the first substrate 110 , the specific structures of various pixel arrays 200 will be described below with multiple embodiments and different drawings.

FIG. 2 is a partial circuit diagram of a pixel array 200 according to an embodiment of the present invention. As shown in FIG. 2, the pixel array 200 includes a plurality of scanning lines 202-208, a plurality of data lines 212-216, a plurality of pixel units 220, 240 in the first column and a plurality of pixel units 230, 250 in the second column. on the first substrate 110 as shown in FIG. 1 .

Structurally, the data lines 212-216 are interleaved with the scan lines 202-208. The first row of pixel units 220 , 240 and the second row of pixel units 230 , 250 are arranged in parallel on the first substrate 110 , and the second row of pixel units 230 , 250 are alternately arranged with the first row of pixel units 220 , 240 .

Each first column of pixel units 220 has a plurality of first pixel structures 222 arranged along a column direction and electrically connected to the corresponding scanning lines 202, 206 and data lines 212, 214 respectively. Each first pixel structure 222 has a first memory The capacitor 312, the first storage capacitor 312 has a first storage capacitor value. Each second column of pixel units 230 has a plurality of second pixel structures 232 arranged along the column direction and electrically connected to the corresponding scanning lines 204, 208 and data lines 212, 214 respectively. Each second pixel structure 232 has a second The storage capacitor 322. The second storage capacitor 322 has a second storage capacitor value, wherein the second storage capacitor value is smaller than the first storage capacitor value.

Regarding the difference in structure between the first storage capacitor 312 and the second storage capacitor 322, for example, the area of the second storage capacitor 322 is smaller than the area of the first storage capacitor 312, or the thickness of the second storage capacitor 322 is larger than that of the first storage capacitor. The thickness of the capacitor 312 or the dielectric constant of the second storage capacitor 322 is smaller than the dielectric constant of the first storage capacitor 312 . By any of the above methods, the second storage capacitance value can be made smaller than the first storage capacitance value. Here, the difference in area is used for illustration.

Moreover, each first pixel structure 222 includes a first thin film transistor 314, and the first thin film transistor 314 is connected to the scan lines 202, 206, the data lines 212, 214 and the first storage capacitor 312; and each second pixel structure 232 includes The second thin film transistor 324 is connected to the scan lines 204 , 208 , the data lines 212 , 214 and the second storage capacitor 322 .

In addition, each first pixel structure 222 includes a first liquid crystal capacitor 316 connected to the first thin film transistor 314; and each second pixel structure 232 includes a second liquid crystal capacitor 326 connected to the second liquid crystal capacitor 326 Two thin film transistors 324 . The similar pixel structures of other columns can be deduced by analogy, which will not be described here again.

FIG. 3 is a schematic top view of two adjacent pixel structures 232 in FIG. 2 . As shown in FIG. 3 , the second thin film transistor 324 is connected to the pixel electrode 328 , and the pixel electrode 328 can be used as an electrode plate of the above-mentioned second storage capacitor 322 . In addition, the first thin film transistor is also connected to a pixel electrode (not shown), and the pixel electrode can be used as an electrode plate of the above-mentioned first storage capacitor. In use, the polarities of the left and right pixel electrodes 328 are different to generate a fringe electric field to cause the rotation of the liquid crystal molecules in the liquid crystal layer 130 as shown in FIG. 1 . The driving method will be described in detail below with FIG. .

FIG. 4 is a 2H switching driving mode matched with the pixel array 200 in FIG. 2 . In the 2H conversion mode, for example, the data driving circuit can provide the pixel data signal 402 to the data line 212, and the pixel data signal can represent red, green, and blue gray scales. During the period when the pixel data signal 402 is at a high potential, the scanning driving circuit can first provide a scanning signal 412 to the scanning line 202 to turn on the first thin film transistor 314, so that the first storage capacitor 312 can be charged; then, the scanning driving circuit can provide scanning The signal 414 is sent to the scan line 204 to turn on the second thin film transistor 324 to charge the second storage capacitor 322 , and so on for other similar pixel structures.

On the other hand, a fixed voltage is provided to the common electrode, and the voltage difference between the common electrode and the pixel electrode generates an electric field, causing rotation of liquid crystal molecules and a specific gray scale. During the period when the pixel data signal 402 is at low potential, the scan driving circuit can successively provide scan signals 416, 418 to the scan lines 206, 208 respectively, while the corresponding first and second storage capacitors are not charged, while other similar pixel structures and so on for scans.

In general, the pixel data signal has positive or negative polarity according to whether its voltage is higher or lower than the common electrode voltage. When the voltage of the pixel data signal is lower than the voltage of the common electrode, the pixel data signal is negative. In addition, when the voltage of the pixel data signal is higher than the voltage of the common electrode, the pixel data signal is positive. FIG. 5 shows the display effect when the pixel array 200 in FIG. 4 is driven in a 2H switching mode. In FIG. 5 , “+” represents positive polarity, and “-” represents negative polarity, and the part surrounded by a thick black frame corresponds to the pixel array in FIG. 4 .

FIG. 6A is a timing diagram when the pixel array 200 in FIG. 2 is driven in a 2H conversion mode and the gray scale is 0 according to an embodiment of the present invention. In FIG. 6A, taking a twisted nematic liquid crystal (Twisted nematic liquid crystal; TN) display structure as an example, the second storage capacitance value (0.207pF) of the second storage capacitor 322 is smaller than the first storage capacitance value of the first storage capacitor 312. (0.247pF). When the pixel data signal 402 represents a grayscale of level 0 (L0), since the scanning signal 412 is provided a period of time earlier than the pixel data signal 402, the pixel data signal 402 cannot be introduced into the The first storage capacitor 312, so adopt the compensation mechanism that the second storage capacitance value (0.207pF) of the second storage capacitance 322 is smaller than the first storage capacitance value (0.247pF) of the first storage capacitance 312, through feed-through (Feed-through ) after the voltage drop, the holding voltage 601 of the first storage capacitor 312 and the holding voltage 602 of the second storage capacitor 322 are both 11.055V, and the holding voltages of the two are roughly the same (ΔV'=0), thus solving the problem of display grid problem.

FIG. 6B is a timing diagram when the pixel array of the comparative example is driven in a 2H conversion mode and the gray scale is 0. FIG. In the control experiment, except that the second storage capacitance value (0.247pF) of the second storage capacitor 322 is equal to the first storage capacitance value (0.247pF) of the first storage capacitor 312, other parameters and hardware architecture are basically the same as those shown in FIG. 6A same. Due to the lack of compensation mechanism, after the feed-through voltage drop, the holding voltage 603 of the first storage capacitor 312 is 11.055V, and the holding voltage 604 of the second storage capacitor 322 is 11.153V. The difference between the two holding voltages is very large (ΔV=0.098 volts), which causes display grid issues.

FIG. 7A is a timing diagram when the pixel array 200 in FIG. 2 is driven in a 2H conversion mode and the gray scale is 32 according to an embodiment of the present invention. In FIG. 7A , the second storage capacitance value (0.207pF) of the second storage capacitor 322 is smaller than the first storage capacitance value (0.247pF) of the first storage capacitor 312 . When the pixel data signal 402 represents a gray scale of 32 (L32), since the scan signal 412 is provided a period of time earlier than the pixel data signal 402, the pixel data signal 402 cannot be introduced into the The first storage capacitor 312, so adopt the compensation mechanism that the second storage capacitance value (0.207pF) of the second storage capacitor 322 is smaller than the first storage capacitance value (0.247pF) of the first storage capacitor 312, after the feed-through voltage drop, The holding voltage 605 of the first storage capacitor 312 is 10.094V, and the holding voltage 606 of the second storage capacitor 322 is 10.127V. The holding voltages of the two are very close (ΔV"=0.033 volts), thereby reducing the display grid problem.

FIG. 7B is a timing diagram when the pixel array of the comparative example is driven in a 2H conversion mode and the gray scale is 32. FIG. In the control experiment, except that the second storage capacitor value (0.247pF) of the second storage capacitor 322 is equal to the first storage capacitor value (0.247pF) of the first storage capacitor 312 and the pixel data signal 402 represents gray scales of 32, Other parameters and hardware architecture are basically the same as those in FIG. 7B. Due to the lack of compensation mechanism, after the feed-through voltage drop, the holding voltage difference between the voltage 607 of the first storage capacitor 312 and the voltage 608 of the second storage capacitor 322 is very large (ΔV=0.098 volts), which leads to display grid problems .

In practice, as long as the second storage capacitor value of the second storage capacitor 322 is smaller than the first storage capacitor value of the first storage capacitor 312, the effect of improving the display grid can be achieved. Preferably, the value of the second storage capacitor is 30%-99.9% of the value of the first storage capacitor, so that the user will hardly notice the grid. It is more preferable that the second storage capacitor value is 50%-95% of the first storage capacitor value, and it is difficult for the user to see the grid when looking closely; and the best is that the second storage capacitor value is the first storage capacitor value 70%-90% of the display grid can be more effectively eliminated.

In summary, the substrate 110 combined with the pixel array 200 shown in FIG. 2 can be used as a liquid crystal display array substrate. The liquid crystal display array substrate includes a substrate 110 , a plurality of scan lines 202 - 208 , a plurality of data lines 212 - 216 , a plurality of first column pixel units 220 and a plurality of second column pixel units 230 . The scan lines 202-208 and the data lines 212-216 are all disposed on the substrate 110, and the data lines 212-216 are intersected with the scan lines 202-208. The pixel units 220 in the first column are arranged in parallel on the substrate 110, and each pixel unit 220 in the first column has a plurality of first pixel structures 222, arranged along a column direction, and electrically connected to the corresponding scanning lines 202, 206 and the data lines 212, 206, respectively. 214 , each first pixel structure 222 has a first storage capacitor 312 , and the first storage capacitor 312 has a first storage capacitance value. The second row of pixel units 232 are arranged in parallel on the substrate 110, and are arranged alternately with these first row of pixel units 222. Each second row of pixel units 230 has a plurality of second pixel structures 232, arranged along the column direction, respectively electrically Connecting the corresponding scanning lines 204, 208 and data lines 212, 214, each second pixel structure 232 has a second storage capacitor 322, and the second storage capacitor 322 has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value A storage capacitor value.

FIG. 8 is a partial circuit diagram of the pixel array 200 in FIG. 1 according to another embodiment of the present invention and its associated 3H switching driving. As shown in FIG. 8 , except that the first row of pixel units 220 , the second row of pixel units 230 and the third row of pixel units 240 are used as repeated driving units, the rest of the circuit structure is basically the same as that of the pixel array 200 shown in FIG. 2 . The number of pixel units 240 in the third column may be multiple, arranged in parallel on the first substrate 110, and each pixel unit 240 in the third column is arranged behind the adjacent pixel unit 230 in the second column, and each pixel unit in the third column The unit 240 has a plurality of third pixel structures 242 arranged along the column direction and electrically connected to the corresponding scanning lines 203 and data lines 212 and 214 respectively. Each third pixel structure 242 has a third storage capacitor, and the third storage capacitor has The third storage capacitor value, wherein the third storage capacitor value is equal to the second storage capacitor value.

Furthermore, each third pixel structure 242 includes a third thin film transistor 334 connected to the scan line 203 , the data lines 212 , 214 and the third storage capacitor 332 .

In addition, each third pixel structure 242 includes a third liquid crystal capacitor 336 , and the third liquid crystal capacitor 336 is connected to the third thin film transistor 334 .

In the 3H conversion mode, for example, the data driving circuit can provide a pixel data signal 802 to the data line 212, and the pixel data signal can represent red, green, and blue gray scales. During the period when the pixel data signal 802 is at a high potential, the scan driving circuit can first provide a scan signal 812 to the scan line 202 to turn on the first thin film transistor 314, so that the first storage capacitor 312 can be charged; then, provide a scan signal 813 to the scan line line 203 to turn on the second thin film transistor 324, so that the second storage capacitor 322 can be charged; then, the scan driving circuit can provide a scan signal 814 to the scan line 204 to turn on the third thin film transistor 334, so that the third storage capacitor 332 can be charging, and the scanning of other similar pixel structures can be deduced by analogy. In this way, the display effect when driving in the 3H conversion mode is shown in FIG. 9 , and the part surrounded by the thick black frame corresponds to the pixel array in FIG. 8 . Similarly, the present invention can also be applied to driving in nH conversion mode, wherein n is a positive integer.

FIG. 10 is a partial circuit diagram of the pixel array 200 shown in FIG. 1 and its associated 2H conversion driving according to another embodiment of the present invention. In FIG. 10, the pixel array 200 is arranged in a 2G1D manner, including multiple first scan lines 902, 904, second scan lines 903, 905, multiple data lines 912-914, multiple first row pixel units 920 and A plurality of pixel units 930 in the second row are all disposed on the first substrate 110 as shown in FIG. 1 .

Structurally, the first scan lines 902 , 904 and the second scan lines 903 , 905 are alternately arranged on the first substrate 110 in parallel. The data lines 912 - 914 are disposed on the first substrate 110 and intersect with the scan lines 902 - 905 . The first row of pixel units 920 and the second row of pixel units 930 are arranged in parallel on the first substrate 110 , and the second row of pixel units 930 and the first row of pixel units 920 are alternately arranged.

Each first row of pixel units 920 has a plurality of first pixel structures 922 arranged along a row and electrically connected to the corresponding first scanning lines 902, 903 and data lines 912. Each first pixel structure 922 has a first Storage capacitor 1012, the first storage capacitor 1012 has a first storage capacitance value; each second row of pixel units 930 has a plurality of second pixel structures 932, arranged along the row direction, electrically connected to the corresponding second scan line 904 respectively , 905 and data line 912, each second pixel structure 932 has a second storage capacitor 1022, and the second storage capacitor 1022 has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value.

Regarding the structural difference between the first storage capacitor 1012 and the second storage capacitor 1022, for example, the area of the second storage capacitor 1022 is smaller than the area of the first storage capacitor 1012, or the thickness of the second storage capacitor 1022 is greater than that of the first storage capacitor 1022. The thickness of the storage capacitor 1012 , or the dielectric constant of the second storage capacitor 1022 is smaller than the dielectric constant of the first storage capacitor 1012 . By any of the above methods, the second storage capacitance value can be made smaller than the first storage capacitance value.

Moreover, each first pixel structure 922 includes a first thin film transistor 1014, and the first thin film transistor 1014 is connected to the first scan line 902, the data line 912 and the first storage capacitor 1012; and each second pixel structure 932 includes a second The thin film transistor 1024 , the second thin film transistor 1024 is connected to the second scan line 903 , the data line 912 and the second storage capacitor 1022 .

In addition, each first pixel structure 922 includes a first liquid crystal capacitor 1016 connected to the first thin film transistor 1014; and each second pixel structure 932 includes a second liquid crystal capacitor 1026 connected to the second liquid crystal capacitor 1026 Two thin film transistors 1024 .

In the 2H conversion mode, for example, the data driving circuit can provide the pixel data signal 1300 to the data line 912, and the pixel data signal can represent red, green, and blue gray scales. During the period when the pixel data signal 1300 is at a high potential 1202 , the scan driving circuit can first provide a scan signal 1312 to the scan line 902 to turn on the corresponding first thin film transistor 1014 to charge the first storage capacitor 1012 . Next, during the period when the pixel data signal 1300 is at the low potential 1203 , the scan driving circuit can successively provide the scan signal 1314 to the scan line 903 to turn on the corresponding second thin film transistor 1024 to charge the second storage capacitor 1022 . The scanning of other similar pixel structures can be deduced by analogy. In this way, the display effect of 2V conversion as shown in FIG. 11 is achieved when driven in the 2H conversion mode, and the part surrounded by the thick black frame corresponds to the pixel array in FIG. 12 .

FIG. 12 is a partial circuit diagram of the pixel array in FIG. 1 and its matching (2H+1) conversion driving according to another embodiment of the present invention. In FIG. 12, the pixel array 200 is arranged in a 2G1D manner, including multiple first scan lines 902, 904, second scan lines 903, 905, multiple data lines 912-914, multiple first row pixel units 920 and A plurality of pixel units 930 in the second row are all disposed on the first substrate 110 as shown in FIG. 1 .

Structurally, the first scan lines 902 , 904 and the second scan lines 903 , 905 are alternately arranged on the first substrate 110 in parallel. The data lines 912 - 914 are disposed on the first substrate 110 and intersect with the scan lines 902 - 905 . The first row of pixel units 920 and the second row of pixel units 930 are arranged in parallel on the first substrate 110 , and the second row of pixel units 930 and the first row of pixel units 920 are alternately arranged.

Each first row of pixel units 920 has a plurality of first pixel structures 922, arranged along a row, electrically connected to the corresponding second scanning lines 903, 905 and data lines 912, and each first pixel structure 922 has a first Storage capacitor 1012, the first storage capacitor 1012 has a first storage capacitance value; each second row of pixel units 930 has a plurality of second pixel structures 932, arranged along the row direction, electrically connected to the corresponding first scan line 902 respectively , 904 and the data line 912, each second pixel structure 932 has a second storage capacitor 1022, and the second storage capacitor 1022 has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value.

Moreover, each first pixel structure 922 includes a first thin film transistor 1014, and the first thin film transistor 1014 is connected to the first scan line 902, the data line 912 and the first storage capacitor 1012; and each second pixel structure 932 includes a second The thin film transistor 1024 , the second thin film transistor 1024 is connected to the second scan line 903 , the data line 912 and the second storage capacitor 1022 .

In addition, each first pixel structure 922 includes a first liquid crystal capacitor 1016 connected to the first thin film transistor 1014; and each second pixel structure 932 includes a second liquid crystal capacitor 1026 connected to the second liquid crystal capacitor 1026 Two thin film transistors 1024 .

In the (2H+1)2H conversion method, for example, the data driving circuit can provide the pixel data signal 1100 to the data line 912 , and the pixel data signal can represent red, green, and blue gray scales. During the period when the pixel data signal 1100 is at a high potential 1102 , the scan driving circuit can first provide a scan signal 1112 to the scan line 912 to turn on the corresponding second thin film transistor 1024 to charge the second storage capacitor 1022 . Next, when the pixel data signal 1100 is at a low potential 1103 , the scan driving circuit can first provide a scan signal 1114 to the scan line 903 to turn on the corresponding first thin film transistor 1014 to charge the second storage capacitor 1012 . Then, the scan driving circuit can provide a scan signal 1116 to the scan line 904 to turn on the corresponding second thin film transistor 1024 to charge the second storage capacitor 1022 . During the period when the pixel data signal 1100 is at a high potential 1104, the scan driving circuit can provide a scan signal 1118 to the scan line 905 to turn on the corresponding first thin film transistor 1014, so that the first storage capacitor 1012 can be charged, and the remaining similar pixel structures and so on for scans. In this way, when driving in the (2H+1) conversion mode, the display effect of dot inversion as shown in Figure 13 is achieved, and the part surrounded by the thick black frame corresponds to the pixel array in Figure 12 .

Regardless of whether it is driven in a 2H or (2H+1) conversion mode, as long as the second storage capacitance value of the second storage capacitor 1022 is smaller than the first storage capacitance value of the first storage capacitor 1012, it can be maintained after charging through the feed-through voltage drop. The voltages are very close, or even the same, which improves display grid issues. Generally, the second storage capacitor value is 30%-99.9% of the first storage capacitor value, and the user is not easy to perceive the grid; preferably, the second storage capacitor value is 50%-95% of the first storage capacitor value It is difficult for the user to see the grid when looking closely; and more preferably, the value of the second storage capacitor is 70%-90% of the value of the first storage capacitor, which can more effectively eliminate the display grid.

In summary, the substrate 110 combined with the pixel array 200 as shown in FIG. 10 or FIG. 12 can be used as a liquid crystal display array substrate. The liquid crystal display array substrate includes a substrate 110, a plurality of first scanning lines 902-903, a plurality of second scanning lines 904-905, a plurality of data lines 912-914, a plurality of first column pixel units 920 and a plurality of second A column of pixel units 920 . The first scan lines 902 - 903 and the second scan lines 904 - 905 are parallel and alternately arranged on the substrate 110 . The data lines 912 - 914 are disposed on the substrate 110 and intersect with the scan lines 902 - 905 . A plurality of pixel units 920 in the first row are arranged in parallel on the substrate 110, and each pixel unit 920 in the first row has a plurality of first pixel structures 922, arranged along a row direction, and electrically connected to corresponding first scanning lines 902, 904 ( 2H) and data lines 912-914 or second scanning lines 903, 905 (2H+1) and data lines 912-914, each first pixel structure 922 has a first storage capacitor 1012, and the first storage capacitor 1012 has a first storage capacitor 1012 A storage capacitance value; a plurality of pixel units 930 in the second row are arranged in parallel on the substrate 110 and arranged alternately with the pixel units 920 in the first row, each pixel unit 930 in the second row has a plurality of second pixel structures 932 along the Arranged in the row direction, respectively electrically connecting the corresponding second scanning lines 903, 905 (2H) and data lines 912-914 or the first scanning lines 902, 904 (2H+1) and data lines 912-914, each The two-pixel structure 932 has a second storage capacitor 1022, and the second storage capacitor 1022 has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value.

The present invention provides that the second storage capacitance value of the second storage capacitor is smaller than the first storage capacitance value of the first storage capacitor, that is, the holding voltage after charging through the feed-through voltage drop is very close to or even the same, thereby improving the display grid or It's a matter of bright and dark lines.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (32)

1. A liquid crystal display panel, characterized in that, comprising: a first substrate; a plurality of scanning lines arranged on the first substrate; A plurality of data lines are arranged on the first substrate and intersect with the scanning lines; A plurality of pixel units in the first column are arranged in parallel on the first substrate, each of the pixel units in the first column has a plurality of first pixel structures, arranged along a column direction, and electrically connected to the corresponding scanning line and the data line respectively , each first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; A plurality of pixel units in the second row are arranged in parallel on the first substrate and arranged alternately with the pixel units in the first row, each pixel unit in the second row has a plurality of second pixel structures arranged along the direction of the row, respectively electrically connecting the corresponding scanning line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value a storage capacitor value; a second substrate disposed opposite to the first substrate; and A liquid crystal layer is arranged between the first substrate and the second substrate. 2. The liquid crystal display panel according to claim 1, wherein each of the first pixel structures comprises a first thin film transistor connected to the scan line, the data line and the first storage capacitor, and each of the first pixel structures The two-pixel structure includes a second thin film transistor connected to the scan line, the data line and the second storage capacitor. 3. The liquid crystal display panel according to claim 1, wherein the second storage capacitance is 30%-99.9% of the first storage capacitance. 4. The liquid crystal display panel according to claim 1, wherein the second storage capacitance is 50%-95% of the first storage capacitance. 5. The liquid crystal display panel according to claim 1, wherein the second storage capacitance is 70%-90% of the first storage capacitance. 6. The liquid crystal display panel according to claim 1, wherein an area of the second storage capacitor is smaller than an area of the first storage capacitor. 7. The liquid crystal display panel according to claim 1, wherein the thickness of the second storage capacitor is larger than the thickness of the first storage capacitor. 8. The liquid crystal display panel according to claim 1, wherein a dielectric constant of the second storage capacitor is smaller than a dielectric constant of the first storage capacitor. 9. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is driven in a 2H switching mode. 10. The liquid crystal display panel according to claim 1, further comprising a plurality of pixel units in the third column arranged in parallel on the first substrate, and each pixel unit in the third column is arranged in adjacent Between the second column of pixel units and the first column of pixel units, each of the third column of pixel units has a plurality of third pixel structures, arranged along the column direction, respectively electrically connected to the corresponding scanning line and the data Each third pixel structure has a third storage capacitor, and the third storage capacitor has a third storage capacitor value, wherein the third storage capacitor value is equal to the second storage capacitor value. 11. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is driven in a 3H switching mode. 12. A liquid crystal display array substrate, characterized in that it comprises: a substrate; A plurality of scanning lines are arranged on the substrate; A plurality of data lines are arranged on the substrate and intersect with these scanning lines; A plurality of pixel units in the first column are arranged in parallel on the substrate, each of the pixel units in the first column has a plurality of first pixel structures, arranged along a column direction, electrically connected to the corresponding scanning line and the data line, each a first pixel structure has a first storage capacitor with a first storage capacitor value; and A plurality of pixel units in the second column are arranged in parallel on the substrate and arranged alternately with the pixel units in the first column. Each pixel unit in the second column has a plurality of second pixel structures arranged along the direction of the column. Sexually connect the corresponding scanning line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value capacitance value. 13. A liquid crystal display panel, characterized in that it comprises: a first substrate; A plurality of first scanning lines and a plurality of second scanning lines are alternately arranged on the first substrate in parallel; A plurality of data lines are arranged on the first substrate and intersect with the scanning lines; A plurality of pixel units in the first row are arranged in parallel on the first substrate, and each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, and respectively electrically connected to the corresponding first scanning line and the For data lines, each first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; A plurality of pixel units in the second row are arranged in parallel on the first substrate and arranged alternately with the pixel units in the first row, each pixel unit in the second row has a plurality of second pixel structures arranged along the row direction, respectively electrically connecting the corresponding second scanning line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is less than the first storage capacitance value; a second substrate disposed opposite to the first substrate; and A liquid crystal layer is arranged between the first substrate and the second substrate. 14. The liquid crystal display panel according to claim 13, wherein each of the first pixel structures comprises a first thin film transistor connected to the first scanning line, the data line and the first storage capacitor, and each The second pixel structure includes a second thin film transistor connected to the second scan line, the data line and the second storage capacitor. 15. The liquid crystal display panel according to claim 13, wherein the second storage capacitance is 30%-99.9% of the first storage capacitance. 16. The liquid crystal display panel according to claim 13, wherein the second storage capacitance is 50%-95% of the first storage capacitance. 17. The liquid crystal display panel according to claim 13, wherein the second storage capacitance is 70%-90% of the first storage capacitance. 18. The liquid crystal display panel according to claim 13, wherein an area of the second storage capacitor is smaller than an area of the first storage capacitor. 19. The liquid crystal display panel according to claim 13, wherein the thickness of the second storage capacitor is larger than the thickness of the first storage capacitor. 20. The liquid crystal display panel according to claim 13, wherein a dielectric constant of the second storage capacitor is smaller than a dielectric constant of the first storage capacitor. 21. The liquid crystal display panel according to claim 13, characterized in that the liquid crystal display panel is driven in a 2H conversion mode to achieve a display effect of 2V conversion. 22. A liquid crystal display array substrate, characterized in that it comprises: a substrate; A plurality of first scanning lines and a plurality of second scanning lines are alternately arranged on the substrate in parallel; A plurality of data lines are arranged on the substrate and intersect with these scanning lines; A plurality of pixel units in the first row are arranged in parallel on the first substrate, and each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, and respectively electrically connected to the corresponding first scanning line and the For data lines, each first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; and A plurality of pixel units in the second row are arranged in parallel on the substrate and arranged alternately with the pixel units in the first row. Each pixel unit in the second row has a plurality of second pixel structures arranged along the direction of the row. Sexually connect the corresponding second scanning line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value A storage capacitor value. 23. A liquid crystal display panel, characterized in that it comprises: a first substrate; A plurality of first scanning lines and a plurality of second scanning lines are alternately arranged on the first substrate in parallel; A plurality of data lines are arranged on the first substrate and intersect with the scanning lines; A plurality of pixel units in the first row are arranged in parallel on the first substrate, and each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, and respectively electrically connected to the corresponding second scanning line and the For data lines, each first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; A plurality of pixel units in the second row are arranged in parallel on the first substrate and arranged alternately with the pixel units in the first row, each pixel unit in the second row has a plurality of second pixel structures arranged along the row direction, respectively electrically connecting the corresponding first scan line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is less than the first storage capacitance value; a second substrate disposed opposite to the first substrate; and A liquid crystal layer is arranged between the first substrate and the second substrate. 24. The liquid crystal display panel according to claim 23, wherein each of the first pixel structures comprises a first thin film transistor connected to the first scanning line, the data line and the first storage capacitor, and each The second pixel structure includes a second thin film transistor connected to the second scan line, the data line and the second storage capacitor. 25. The liquid crystal display panel according to claim 23, wherein the second storage capacitance is 30%-99.9% of the first storage capacitance. 26. The liquid crystal display panel according to claim 23, wherein the second storage capacitance is 50%-95% of the first storage capacitance. 27. The liquid crystal display panel according to claim 23, wherein the second storage capacitance is 70%-90% of the first storage capacitance. 28. The liquid crystal display panel according to claim 23, wherein an area of the second storage capacitor is smaller than an area of the first storage capacitor. 29. The liquid crystal display panel as claimed in claim 23, wherein the thickness of the second storage capacitor is larger than that of the first storage capacitor. 30. The liquid crystal display panel according to claim 23, wherein a dielectric constant of the second storage capacitor is smaller than a dielectric constant of the first storage capacitor. 31. The liquid crystal display panel according to claim 23, characterized in that the liquid crystal display panel is driven in a (2H+1) conversion mode to achieve a display effect of dot conversion. 32. A liquid crystal display array substrate, characterized in that it comprises: a substrate; A plurality of first scanning lines and a plurality of second scanning lines are alternately arranged on the substrate in parallel; A plurality of data lines are arranged on the substrate and intersect with these scanning lines; A plurality of pixel units in the first row are arranged in parallel on the substrate, each pixel unit in the first row has a plurality of first pixel structures, arranged along a row direction, electrically connected to the corresponding second scanning line and the data line respectively , each first pixel structure has a first storage capacitor, and the first storage capacitor has a first storage capacitor value; and A plurality of pixel units in the second row are arranged in parallel on the substrate and arranged alternately with the pixel units in the first row. Each pixel unit in the second row has a plurality of second pixel structures arranged along the direction of the row. Sexually connect the corresponding first scanning line and the data line, each second pixel structure has a second storage capacitor, and the second storage capacitor has a second storage capacitance value, wherein the second storage capacitance value is smaller than the first storage capacitance value A storage capacitor value.

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