CN102163054A - PROFIBUS-DP main station communication equipment and microprocessor thereof and data sharing method of ASIC chip - Google Patents
PROFIBUS-DP main station communication equipment and microprocessor thereof and data sharing method of ASIC chip Download PDFInfo
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Abstract
The invention relates to the field of automatic control and discloses PROFIBUS-DP 1 type main station communication equipment and a microprocessor thereof and a data sharing method of ASIC chips. The main station communication equipment comprises an embedded microprocessor, a peripheral circuit comprising a nonvolatile memory, an ASIC chip ASPC2, a double port RAM (random access memory) and a static memory, wherein the ASIC chip ASPC2 is connected with a PROFIBUS-DP bus through an RS485 interface circuit; and a complex programmable logic device (CPLD) is connected with the microprocessor, the ASIC chip and the static memory for enabling the microprocessor and the ASIC chip to share the data of the static memory. The ASIC chip is used to guarantee the communication rate; the CPLD is used to enable the microprocessor and the ASIC chip to share the data; the development cost is saved; the performance is high; the cost is low; and the work is stable and reliable.
Description
Technical field
The invention belongs to the automatic control technology field, be specifically related to a kind of PROFIBUS-DP master communication equipment based on embedded microprocessor and asic chip.
Background technology
PROFIBUS is a kind of internationalization, open, the standard for Fieldbus that do not rely on the device fabrication merchant, be widely used in fields such as automated manufacturing, process industry robotization and building, traffic, electric power, wherein PROFIBUS-DP is the low-cost communication standard of a kind of high speed, is used for the communication of device level control system distributing I/O more.
The applicating and exploitation of PROFIBUS-DP bussing technique is relatively more extensive at home at present, though the PROFIBUS agreement is open, and the technology sealing, core technology is controlled by offshore companies of several family such as Siemenss.Therefore cause domestic smart machine development based on the DP bus slower, and exist the slave station product many, the main website product is few; Secondary development is many, grasps problems such as core technology is few.Owing to must have a main website to communicate control in the PROFIBUS-DP network, the DP smart machine of domestic manufacturer's development and Design generally is to be articulated in the operation of can working under the DP main website of foreign vendor such as Siemens.
At present, exploitation PROFIBUS-DP main website equipment mainly contains following several feasible scheme:
(1) software PROFIBUS-DP main website.This scheme realizes institute's protocols having more than the PROFIBUS-DP Physical layer by software, the complete protocol stack of operation in microprocessor.Because present most of CPU have the UART mouth, only need add the Physical layer that a RS485 transceiver can be realized the DP agreement, realize the data link layer, user interface layer of DP agreement etc. on this basis.Though this scheme hardware is simple, with low cost, but the task of software design is very complicated, reliability is difficult to guarantee, and do not reach higher traffic rate, the theoretical limit speed of UART adds the function of data link layer and user interface layer on the general processor piece about 1.5Mbps, actual hump speed estimates only to reach hundreds of Kbps, differ greatly with the 12Mbps speed of DP agreement support, reduced the performance of communication, the application scenario of having limited equipment.Company of Hollysys has realized the PROFIBUS-DP main website based on this scheme, but is subjected to the restriction of traffic rate, uses to be difficult to promote always.
(2) based on embedded master station module secondary development.It is maximum a kind of that this scheme is that exploitation PROFIBUS-DP main website adopts.Integrated asic chip in embedded master station module inside and program curing.The developer buys flush bonding module and does secondary development on its basis.This solution development difficulty and development risk all significantly reduce, the construction cycle reduction, but existing in the market embedded master station module is monopolized by offshore companies such as Siemenss basically, adopt this scheme need buy their flush bonding module, cost of development is big and under one's control technically, the inreal core technology of grasping the PROFIBUS-DP main website.The DP main website product of domestic most of manufacturers all is based on this scheme, and cost of products is high.
(3) asic chip adds the expansion firmware program.This scheme is by the medium access control function of asic chip realization PROFIBUS-DP protocol data link layer, and other functions of data link layer and the function of user interface layer are moved its expansion firmware program by microprocessor and realized.The hardware plan of this scheme is than first kind of scheme complexity, because the use of asic chip, this scheme can reach higher traffic rate (the highest 12Mbps), can give full play to the speed advantage of PROFIBUS-DP bus, stable and reliable for performance, and rejected the extra cost of using foreign technology, cost of products is cheap relatively.At present, external chip supplier has limited the opening of the supporting firmware program of chip, do not sell firmware, therefore adopt this scheme to design hardware interface circuit voluntarily and to write firmware program and upper layer software (applications) by the developer, need the developer all very familiar to chip and DP agreement, development difficulty is very big.Still there be not the main website product stable and reliable for performance of domestic manufacturers in the market based on this solution development success.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of PROFIBUS-DP master communication equipment that can realize 1 class master function in the PROFIBUS-DP protocol stack.
For achieving the above object, the technical solution used in the present invention is: a kind of PROFIBUS-DP master communication equipment, comprise embedded microprocessor and comprise peripheral circuit, asic chip, the dual port RAM static memory of nonvolatile memory, asic chip connects the PROFIBUS-DP bus by the RS485 interface circuit, it is characterized in that: described embedded microprocessor and peripheral circuit thereof, dual port RAM are connected the 3.3V bus, dual port RAM one end interface is connected with microprocessor and peripheral circuit thereof, and other end interface uses for the user; Asic chip and static memory are connected the 5V bus; 3.3V CPLD realization level conversion and microprocessor, the shared static memory data of asic chip are set between bus and the 5V bus.
Be provided with the light-coupled isolation chip between described asic chip and the RS485 interface circuit.
Described embedded microprocessor peripheral circuit also comprises the universal asynchronous serial interface switching RS232 serial ports by microprocessor.
Described embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects LED.
Described embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects watchdog chip.
The above embedded microprocessor is the embedded-type ARM microprocessor.
The above asic chip is the ASPC2 chip.
Above-mentioned PROFIBUS-DP master communication equipment, the method that its microprocessor and asic chip are shared the static memory data may further comprise the steps:
(1) register in the microprocesser initialization asic chip;
(2) microprocesser initialization static memory;
(3) microprocessor starts asic chip;
(4) the microprocessor bus data that will send writes static memory by form;
(5) asic chip is learnt after the data that will send and to be made the HOLD signal effective to the microprocessor requests external bus;
(6) microprocessor enters high-priority interrupt, makes the HOLDA signal effective, and abdicates external bus;
(7) asic chip takes out the data in the static memory and sends bus data;
(8) asic chip is abdicated bus after finishing transmission, makes the HOLD invalidating signal;
(9) microprocessor withdraws from interruption, makes the HOLDA invalidating signal;
(10) after asic chip receives data,, make the HOLD signal effective to the microprocessor requests external bus;
(11) microprocessor enters high-priority interrupt, makes the HOLDA signal effective, and abdicates external bus;
(12) after asic chip is finished reception, the bus data that receives is write static memory;
(13) asic chip is abdicated bus after finishing reception, makes the HOLD invalidating signal;
(14) microprocessor withdraws from interruption, makes HOLDA invalid;
(15) asic chip receives data with interrupt mode notice microprocessor;
(16) judge whether to carry out message circulation next time, if then repeating step (4)～(15), then end if not.
The present invention uses asic chip to connect the PROFIBUS-DP bus can realize PROFIBUS-DP main website two-forty and unfailing performance, use embedded microprocessor can realize the data link layer functions of PROFIBUS-DP main website simultaneously, and realize complete DP main website protocol stack on this basis.Wherein user interface layer and DDLM layer are described exploitation according to the state machine that the PROFIBUS-DP standard provides, the ASPC2 chip driver program is developed in conjunction with the PROFIBUS-DP standard according to the ASPC2 chip handbook that Siemens provides, and can realize the function of ASPC2 first wife fixing plate program.
The invention has the advantages that: adopt asic chip to guarantee the traffic rate of PROFIBUS-DP bus, working stability is reliable; Adopt 32-bit microprocessor, compare external like product and adopt 16 single-chip microcomputer travelling speed high more than 30%; And utilize complicated programmable logic device to make shared data between microprocessor and the asic chip, and reduced cost of development, solved dependence to foreign vendor, possess high-performance, low cost, stable and reliable operation characteristics.
Description of drawings
Fig. 1 is a hardware design block diagram of the present invention;
Fig. 2 is ASPC2 and arm processor interface circuit design figure;
Fig. 3 is the workflow block diagram that microprocessor and asic chip are shared the static memory data.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments.
The hardware chip model that present embodiment adopts is as follows:
Embedded microprocessor: the ARM7 flush bonding processor AT91R40008 (CPU) of Atmel company;
Asic chip: the protocol chip ASPC2 of PROFIBUS main website of Siemens Company;
Dual port RAM: the IDT70V05 of IDT company (8K * 8bit);
Nonvolatile memory (Nor Flash): the SST39VF1601 of SST company (1M * 16bit);
CPLD (CPLD): the XC95144XL of Xilinx company;
Static memory (SRAM): the CY7C1041R of Cypress company (256K * 16bit);
Light-coupled isolation chip: HCPL7721 and HCPL0601;
RS485 interface chip: SN75176BD;
RS232 interface chip: MAX3232;
Watchdog chip: X25043.
Fig. 1 is a hardware design block diagram of the present invention.As shown in Figure 1, a kind of PROFIBUS-DP master communication equipment, comprise embedded microprocessor and comprise peripheral circuit, asic chip, dual port RAM and the static memory of nonvolatile memory, asic chip connects the PROFIBUS-DP bus by the RS485 interface circuit, it is characterized in that: described embedded microprocessor and peripheral circuit thereof, dual port RAM are connected the 3.3V bus, dual port RAM one end interface is connected with microprocessor and peripheral circuit thereof, and other end interface uses for the user; Asic chip, static memory are connected the 5V bus; 3.3V CPLD realization level conversion and microprocessor, the shared static memory data of asic chip are set between bus and the 5V bus.
Disturb each other for fear of digital circuits such as DP mouth communicating circuit and ASPC2, be provided with the light-coupled isolation chip between asic chip and the RS485 interface circuit.
The embedded microprocessor peripheral circuit also comprises the UART switching RS232 serial ports by microprocessor.
The embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects LED.
The embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects watchdog chip.
The AT91R40008ARM processor is as the core CPU in the hardware design, writes and moves corresponding firmware program control ASPC2 thereon and realize FDL layer function in the PROFIBUS-DP main website protocol stack.The serial line interface of the last CMOS level of ASPC2 is converted to the RS485 level that meets PROFIBUS-DP agreement physical layer specification by level transferring chip SN75176BD.Universal asynchronous serial interface on the arm processor sheet (UART) is converted to the RS232 level by chip MAX3232, can communicate with the serial ports on the ordinary PC, is used to carry out configuration and downloads.In addition, articulate a slice IDT07V05 dual port RAM on the 3.3V bus,, be mainly used in secondary development as user interface.4 LED lamps directly link to each other with the I/0 mouth of ARM, are respectively applied for duty, the configuration state of indication DP master communication equipment, four kinds of information such as network state and token status.Nonvolatile memory in the hardware plan (Nor F1ash) is used to realize functions such as program Solidification and configuration file storage.
Adopt a slice static memory (SRAM) to realize the data interaction of arm processor and ASPC2, arm processor and ASPC2 realize that by CPLD the bus arbitration timesharing takies SRAM data, address bus, realizes the share and access to the SRAM data.By the SRAM swap data, be connected between this three on the system bus between ASPC2 and the AT91R40008 processor.AT91R40008 can visit SRAM and ASPC2 internal register, and ASPC2 also can visit SRAM.
This part circuit design is mainly considered two parts: a part is the level conversion between AT91R40008 and ASPC2 and the storer, and another part is AT91R40008, the connected mode between ASPC2 and the SRAM three.
AT91R40008 is the 3.3V power supply, and ASPC2 and SRAM are the 5V power supplies, need between the two to transfer by level shifting circuit.
Connect by the shared storage mode between ASPC2 and the AT91R40008.AT91R40008 is responsible for bus arbitration under this mode.ASPC2 has one group of bus request signal HOLD and HOLDA.Because the expansion bus interface of AT91R40008 does not have bus arbitration mechanism, uses this connected mode to realize bus arbitration by auxiliary circuit.
Fig. 2 is ASPC2 and arm processor interface circuit design figure.As shown in Figure 2, above-mentioned level conversion and bus arbitration function can be realized by a slice CPLD (CPLD).
AT91R40008 is connected with the shared storage connected mode with ASPC2 with SRAM by the CPLD circuit.The HOLD signal of ASPC2 interrupts input signal as the IRQ of AT91R40008.ASPC2 activates the HOLD signal when needs visit SRAM, AT91R40008 enters interrupt service subroutine immediately, closes the output of CPLD bus and provides the HOLDA signal.The AT91R40008 external bus is in high-impedance state, and this is equivalent to AT91R40008 and has discharged system bus.ASPC2 finishes the activation of removing the HOLD signal after the visit of SRAM, and AT91R40008 withdraws from interrupt service subroutine, opens the output of all CPLD and stops to provide the HOLDA signal.This is equivalent to the control that AT91R40008 has obtained system bus again.The workflow of the shared SRAM data of AT91R40008 and ASPC2 as shown in Figure 3.
Based on the described hardware design of Fig. 2 and in conjunction with the described software flow of Fig. 3, can design the ASPC2 driver, can realize the major function of ASPC2 first wife fixing plate program.
The present invention realizes 1 class master function in the PROFIBUS-DP protocol stack.Physical layer is realized by the RS485 hardware interface circuit.Data link layer is divided into the FDL service, FMA1/2 service and medium access are controlled three parts, medium access control section function is realized by ASPC2, be that ASPC2 is a media access controller, the ASPC2 driver is responsible for realizing management and the control to ASPC2, FDL service in the data link layer, the FMA1/2 service then realizes based on the ASPC2 driver.Client layer is divided into the user, three parts of user interface (User Interface) and DDLM (Direct Data Linker Map), and DDLM and user interface layer are realized by the software that runs on the arm processor.
All softwares of PROFIBUS-DP master communication equipment all run on the arm processor.Comprise user interface layer, the DDLM layer, the FDL layer, FMA1/2 layer and ASPC2 Drive Layer, wherein the User Part of client layer is finished by the user of main website.User interface layer, the DDLM layer is described exploitation according to the state machine that the PROFIBUS-DP standard provides, the FDL layer, the service describing exploitation that the FMA1/2 layer provides according to the PROFIBUS-DP standard, the ASPC2 drive software is developed in conjunction with the PROFIBUS-DP standard according to the ASPC2 chip handbook that Siemens provides, the method that its related gordian technique method is shared the static memory data for the microprocessor narrated among the present invention and asic chip can realize the function of ASPC2 first wife fixing plate program.
Claims (8)
1. PROFIBUS-DP master communication equipment, comprise embedded microprocessor and comprise peripheral circuit, asic chip, dual port RAM and the static memory of nonvolatile memory, asic chip connects the PROFIBUS-DP bus by the RS485 interface circuit, it is characterized in that: described embedded microprocessor and peripheral circuit thereof, dual port RAM are connected the 3.3V bus, dual port RAM one end interface is connected with microprocessor and peripheral circuit thereof, and other end interface uses for the user; Asic chip and static memory are connected the 5V bus; 3.3V CPLD realization level conversion and microprocessor, the shared static memory data of asic chip are set between bus and the 5V bus.
2. PROFIBUS-DP master communication equipment according to claim 1 is characterized in that: be provided with the light-coupled isolation chip between described asic chip and the RS485 interface circuit.
3. PROFIBUS-DP master communication equipment according to claim 1 is characterized in that: described embedded microprocessor peripheral circuit also comprises the universal asynchronous serial interface switching RS232 serial ports by microprocessor.
4. PROFIBUS DP master communication equipment according to claim 1 is characterized in that: described embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects LED.
5. PROFIBUS-DP fieldbus master communication equipment according to claim 1 is characterized in that: described embedded microprocessor peripheral circuit comprises that also the I/O by microprocessor connects watchdog chip.
6. PROFIBUS-DP master communication equipment according to claim 1 is characterized in that: described embedded microprocessor is the embedded-type ARM microprocessor.
7. PROFIBUS-DP master communication equipment according to claim 1 is characterized in that: described asic chip is the ASPC2 chip.
8. PROFIBUS-DP master communication equipment according to claim 1, the method that its microprocessor and asic chip are shared the static memory data may further comprise the steps:
(1) register in the microprocesser initialization asic chip;
(2) microprocesser initialization static memory;
(3) microprocessor starts asic chip;
(4) the microprocessor bus data that will send writes static memory by form;
(5) asic chip is learnt after the data that will send and to be made the HOLD signal effective to the microprocessor requests external bus;
(6) microprocessor enters high-priority interrupt, makes the HOLDA signal effective, and abdicates external bus;
(7) asic chip takes out the data in the static memory and sends bus data;
(8) asic chip is abdicated bus after finishing transmission, makes the HOLD invalidating signal;
(9) microprocessor withdraws from interruption, makes the HOLDA invalidating signal;
(10) after asic chip receives data,, make the HOLD signal effective to the microprocessor requests external bus;
(11) microprocessor enters high-priority interrupt, makes the HOLDA signal effective, and abdicates external bus;
(12) after asic chip is finished reception, the bus data that receives is write static memory;
(13) asic chip is abdicated bus after finishing reception, makes the HOLD invalidating signal;
(14) microprocessor withdraws from interruption, makes HOLDA invalid;
(15) asic chip receives data with interrupt mode notice microprocessor;
(16) judge whether to carry out message circulation next time, if then repeating step (4)～(15), then end if not.
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Cited By (2)
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| CN103186117A (en) * | 2011-12-28 | 2013-07-03 | 深圳市汇川控制技术有限公司 | PROFIBUS-DP master realization system and method based on CPLD |
| CN104238517A (en) * | 2014-09-16 | 2014-12-24 | 西安西热控制技术有限公司 | PROFIBUS-DPV1 main communication station and method |
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