CN102169134A - A hardware-based transient voltage recording method - Google Patents

Abstract

The invention relates to a hardware-based transient voltage recording method. The method is characterized in that real-time compression, peak value calculation, trigger judgment and low rate collection of data can be completed simultaneously in one sampling clock period; the real-time compression, the peak value calculation, the trigger judgment and the low rate collection of data are realized in an FPGA (Field Programmable Gata Array); and the FPGA is connected to an external A/D (Analog-Digital converter). In the scheme provided in the method, the FPGA, which is a programmable device, is employed for real-time compression and storage of wave form. Therefore, the working efficiency of a CPU is improved, the high sampling rate is guaranteed, the storage space is remarkably saved, and the recording demands of transient processes with various high-speed or low-speed changes are satisfied.

Description

A Hardware-Based Transient Voltage Recording Method

technical field

The invention relates to a transient voltage recording method in the field of power systems, in particular to a hardware-based transient voltage recording method.

Background technique

Various faults may occur during the operation of the power grid, some of which will cause power interruption and equipment damage. The process of power grid fault is often accompanied by the disturbance of system voltage. Lightning strikes, operating overvoltage, power frequency overvoltage, pollution flashover, equipment failure, etc., can cause grid voltage disturbances and even grid accidents. Recording the disturbance of the grid voltage before the grid accident is of great value for accident inversion and analysis. In order to completely record grid voltage disturbances, a high sampling rate is required to meet the needs of recording lightning waveforms, etc.; a long memory time is required to meet the needs of recording accidents with a long duration. When a higher sampling rate is used, in order to save storage space, some compression algorithms are usually used. In the past transient voltage recording, DSP is usually used to directly read high-speed A/D data and perform real-time compression, storage, and trigger judgment. The CPU is in the process of continuous data fetching, compression, and processing, which takes up a lot of CPU time. As a result, the CPU has no time to do other work, so the sampling rate has to be reduced. With the rapid development of Field Programmable Gate Array FPGA, using FPGA to realize data compression and processing has become a new method. Because there are a certain number of flip-flops, comparators, and large-capacity memories inside the FPGA, it is possible to realize data acquisition, compression, and judgment. In power system transient voltage recording, it is usually required to have voltage mutation trigger, upper limit trigger, lower limit trigger and other trigger methods, in addition to the requirement of harmonic measurement.

Contents of the invention

The purpose of the present invention is to provide a transient voltage recording method with high sampling rate and fast acquisition of voltage waveform.

For realizing the purpose of the present invention, the present invention adopts following scheme to realize:

A hardware-based transient voltage recording method, which is improved in that: the method simultaneously completes real-time compression, peak calculation, trigger judgment and low-rate acquisition of data within one sampling clock cycle; the real-time compression of data, Peak calculation, trigger judgment and low-rate acquisition are realized in FPGA; the real-time compression is to compare the collected waveform data A with the base value B in D flip-flop 1 in comparator 1 in real time, and the compressed data is stored in Enter the FIFO of the first-in-first-out memory; the peak calculation is to compare the waveform data A with the collected maximum value Max and the minimum value Min; the upper and lower limit trigger judgments are to compare the waveform data A with a given trigger The upper limit value and the lower limit value are compared in comparator 5 and comparator 6 respectively, and when greater than the upper limit value or less than the lower limit value, an effective trigger signal is output; the low-rate acquisition is to collect the waveform data A performs snapshot compression and stores it into the first-in-first-out memory FIFO2; the FPGA is externally connected with an analog-to-digital converter A/D.

A kind of preferred technical scheme that the present invention provides is: the real-time compression of described data is carried out in the real-time compression module in FPGA; Described real-time compression module comprises D flip-flop 1, counter 1, comparator 1, timing control circuit and First-in-first-out memory FIFO; Described real-time compression comprises the following situation when comparing in comparator 1 in real-time to the waveform data A collected and the base value B in D flip-flop 1:

A. When the waveform data A is smaller than the compression ratio delta compared with the base value B, the D flip-flop 1 is turned off, the waveform data A is discarded, the counter 1 is incremented by 1, and the writing of the FIFO enables The enable signal is invalid, and no data is written into the FIFO;

B. When the waveform data A is greater than the compression ratio delta compared with the base value B, the write enable signal of the FIFO is valid, and the base value B and the count value in the counter are saved to the FIFO, so The counter 1 is cleared, the D flip-flop 1 is turned on, and the waveform data A replaces the base value B.

The second preferred technical solution provided by the present invention is: the peak value calculation of the data is carried out in the peak value calculation module in the FPGA; the peak value calculation module includes D flip-flop 2, D flip-flop 3, comparator 2, comparison Comparator 3, comparator 4 and counter 2; Described peak calculation includes the following situations when comparing the waveform data A with the collected maximum value Max and minimum value Min:

a. When A>Max, the output of the comparator 2 is high level, the D flip-flop 2 is turned on, and the waveform data A replaces the maximum value Max;

b. When A<Min, the output of the comparator 3 is high level, the D flip-flop 3 is turned on, and the waveform data A replaces the minimum value Min;

c. Every time a comparison is performed, the counter 2 adds 1, and when the value D of the counter 2 is accumulated to a given cycle count value D0, that is, when D>=D0, the output of the comparator 4 is a high level .

The third preferred technical solution provided by the present invention is: the trigger judgment of the data is carried out in the upper limit and lower limit trigger judgment modules; the upper limit and lower limit trigger judgment modules include a comparator 5 and a comparator 6; the upper limit , The lower limit trigger judgment includes the following situations:

(1) Comparing the waveform data A with a given trigger upper limit value up_limit in the comparator 5, when A>up_limit meets the upper limit trigger condition, then up_valid effectively outputs a low level;

(2) The waveform data A is compared with a given trigger lower limit value down_limit in the comparator 5 , and when A<down_limit satisfies the lower limit trigger condition, then down_valid effectively outputs a low level.

The fourth preferred technical solution provided by the present invention is: the low-rate acquisition of the data is carried out in the low-rate acquisition module in the FPGA; the low-rate acquisition module includes a first-in-first-out memory FIFO2, a counter 3 and a comparator 7 ; The low-rate acquisition includes the following situations when performing snapshot compression on the acquired waveform data A:

① comparing the value C of the counter 3 with the frequency division number F in the comparator 7, when C<F, the output of the comparator 7 is low level, and the write enable signal of FIFO2 is invalid, No data is written into FIFO2;

2. compare the value C of the counter 3 with the frequency division number F in the comparator 7, when C>F, the output of the comparator 7 is a high level, and the write enable signal of the FIFO2 is invalid, Write the waveform data A into FIFO2.

The fifth preferred technical solution provided by the present invention is: the analog-to-digital converter A/D performs analog-to-digital conversion on the rising edge of the clock signal; falling edge simultaneously.

Compared with prior art, the beneficial effect that the present invention reaches is:

The present invention provides a hardware-based transient voltage recording method, which uses a programmable gate array FPGA to compress and store waveforms in real time, improves CPU work efficiency, ensures high sampling rates, greatly saves storage space, and meets the requirements for For the recording requirements of various fast and slow changing transient processes, a parallel computing method is adopted in FPGA programming, which shows the superiority of FPGA data processing and computing in the process of massive data computing, within one sampling clock cycle It can complete data collection, compression, storage, peak calculation and trigger judgment.

Description of drawings

Figure 1 is a structural diagram of a transient voltage recording system based on FPGA;

Fig. 2 is the FPGA realization schematic diagram of real-time compression module;

Fig. 3 is the FPGA realization schematic diagram of peak calculation module;

Fig. 4 is the FPGA realization schematic diagram of upper limit, lower limit trigger judgment module;

Figure 5 is a schematic diagram of the FPGA implementation of the low-rate acquisition module.

Detailed ways

The specific embodiment of the present invention will be further described in detail below in conjunction with the accompanying drawings.

Figure 1 is a structural diagram of the FPGA-based transient voltage recording system. Using the parallel processing capability of the FPGA, real-time compression and trigger judgment are all implemented in the FPGA. The FPGA contains the following modules:

(1) real-time compression module;

(2) Peak calculation module;

(3) Upper limit and lower limit trigger judgment module;

(4) Low-rate acquisition module.

Fig. 2 is the FPGA realization synoptic diagram of real-time compression module, and real-time compression module comprises D flip-flop 1, counter 1, comparator 1, sequential control logic device and first-in-first-out memory FIFO; Adopt analog-to-digital converter A/D in the present invention For analog-to-digital conversion, the sampling rate of the analog-to-digital converter A/D is high, the amount of collected data is large, and the storage space is saved. The real-time compression method is used to compress and store the data.

The high-speed analog-to-digital converter A/D performs analog-to-digital conversion on the rising edge of the clock. On the falling edge of the clock, the collected waveform data A is compared with the base value B in real time. When the waveform data A and the base value B are less than the given When the compression ratio delta is fixed, the control variable agb=0, then the compression command compress=0, the D flip-flop 1 is closed, the waveform data A is discarded, the counter 1 is incremented by 1, and the write enable signal write_enable of the FIFO is invalid, and no data is written into the FIFO; when the waveform data A is greater than delta compared with the base value B, the control variable agb=1, and the write enable signal write_enable of the FIFO is valid, at the rising edge of the next clock signal, the base value B and counter 1 The count value is saved to the FIFO, and at the same time compress=1, the counter 1 is cleared, the D flip-flop 1 is turned on, and the base value B is replaced with the waveform data A. The data stored in the FIFO after real-time compression is only the compressed part of the sampling value and the number of compression points. Clr in counter 1 represents a clear flag, and Enable in D flip-flop 1 represents an enable signal.

The program written in comparator 1 is:

If(|A-B|＞delta)

agb=1;

Else

agb=0;

If you do not use FPGA, directly connect the analog-to-digital converter A/D to the CPU, so that when the system is working, the A/D will continuously sample at high speed, and the CPU will be in the state of continuously fetching data at intervals, which will take up a lot of CPU time. Part of the time, the CPU cannot do other work, and it may also happen that the CPU has not finished processing the last data, but also needs to process the next batch of data. This contradiction will be particularly prominent in the case of high-speed sampling. FPGA is used to compress and cache data, which greatly improves the working efficiency of CPU; and both ends of FIFO can also be connected to asynchronous clocks, so as to solve the data transmission across clock domains well.

When triggering with a sudden change in voltage, it is necessary to calculate the positive and negative peak values of the voltage. Figure 3 is a schematic diagram of the FPGA implementation of the peak calculation module. The peak calculation module includes D flip-flop 2, comparator 2, D flip-flop 3, comparator 3 and a counter 2 and comparator 4; the input of the peak calculation module has the waveform data A sampled by the analog-to-digital converter A/D and the cycle count value D0. Period count value D0 = sampling rate * 20/1000, that is, the number of sampling clocks in one power frequency period. On the falling edge of the clock signal, the FPGA compares the sampled waveform data value A with the maximum value Max and minimum value Min already collected in the power frequency cycle in the peak value calculation module: if A>Max, the value of comparator 2 The output Ea is high level, and D flip-flop 2 is turned on at the rising edge of the next clock, and the maximum value Max is replaced by waveform data A; if A<Min, the output Eb of comparator 3 is high level, and at the rising edge of the next clock Turn on the flip-flop 3 along D, replace the minimum value Min with the waveform data A, and add 1 to the counter 2 every time a comparison is made, when the value D in the counter 2 is accumulated to the given cycle count value D0, that is, D>=D0, in During a power frequency cycle, the output Ec of the comparator 4 is high level, so that the counter 2 is cleared, then the FPGA output Valid is valid, and the CPU can read the positive and negative peak values at this time. On the falling edge of the next clock signal, the peak calculation for the next cycle starts. Clr in counter 2 represents the clear flag, and Enable in D flip-flop 2 and D flip-flop 3 represents the enable signal.

The program written in comparator 2 is:

If(A>=Max)

Ea=1;

Else

Ea=0;

The program written in comparator 3 is:

If(A<=Min)

Eb=1;

Else

Eb=0;

The program written in comparator 4 is:

If(D>=D0)

Ec=1;

Else

Ec=0;

Fig. 4 is the FPGA realization sketch map of upper limit, lower limit trigger judgment module, upper limit, lower limit trigger judgment module comprise comparator 5 and comparator 6; Data A is compared with the given trigger upper limit value up_limit. When A>up_limit, the upper limit trigger condition is satisfied, then up_valid effectively outputs a low level; the sampled waveform data A is compared with the given trigger lower limit value down_limit by comparator 6 For comparison, when A<down_limit, the lower limit trigger condition is met, then down_valid outputs a low level effectively. The comparison process is automatically completed by the upper limit and lower limit trigger judgment modules of the FPGA, and the CPU only needs to store the data when receiving valid trigger signals up_limit and down_limit, which improves work efficiency.

The program written in Comparator 5 is:

If(A>up_limit)

Up_valid = 0;

Else

Up_valid = 1;

The program written in Comparator 6 is:

If(A<down_limit)

Down_valid = 0;

Else

Down_valid = 1;

Fig. 5 is the FPGA realization schematic diagram of low-rate acquisition module, and low-rate acquisition module comprises first-in-first-out memory FIFO2, counter 3 and comparator 7; In the waveform data A, one data is extracted for every F data, and there is no need to add an additional analog-to-digital converter A/D. The specific working process is: on the falling edge of the clock signal, the comparator 7 compares the value C of the counter 3 with the frequency division number F, if C<F, the output Ec of the comparator 7 is low level, and the writing of FIFO2 enables The enable signal Write_enable is invalid, and no data is written into FIFO2; when C>=F, the output Ec of the comparator 7 is high level, the write enable signal Write_enable of FIFO2 is valid, and the waveform data A is written on the rising edge of the next clock signal into FIFO2. What is stored in FIFO2 is the low-rate sampling value extracted from the data collected at high sampling rate, which can also be called snapshot compression.

The program written in Comparator 7 is:

If(C<F)

Ec=0;

Else

Ec=1;

Example 1

A hardware-based transient voltage recording method provided by the present invention is applied to a VER200 transient voltage recorder. VER200 adopts the structure of A/D+FPGA+DSP. Real-time compression and trigger judgment are all completed in FPGA. DSP only needs to read the compressed data and store the data after reading the effective trigger signal. Multi-channel synchronization The sampling rate reaches 20Msps, the data compression rate reaches more than 99%, and the power frequency voltage waveform can be recorded for up to 300 seconds, which meets the recording requirements for various fast and slow changing transient processes.

Finally, it should be noted that: the combination of the above embodiments only illustrates the technical solution of the present invention rather than limiting it. Those of ordinary skill in the art should understand that: those skilled in the art can make modifications or equivalent replacements to the specific embodiments of the present invention, but these modifications or changes are all within the protection scope of the pending claims.

Claims (6)

1. a hardware based transient voltage recording method is characterized in that, described method is finished data simultaneously at a sampling clock in the cycle Real Time Compression, peak value calculates, triggers and judge and the low rate collection; The Real Time Compression of described data, peak value calculating, triggering judgement and low rate are captured among the FPGA and realize; Described Real Time Compression is that Wave data A that collects and the base value B in the d type flip flop 1 are compared in comparer 1 in real time, and the data after the compression deposit push-up storage FIFO in; Described peak meter compares described Wave data A and the maximal value Max, the minimum M in that collect at last; The described upper limit, lower limit trigger judges it is that described Wave data A is compared respectively with given triggering higher limit and lower limit in comparer 5 and comparer 6, export effective trigger signals during greater than higher limit or less than lower limit; Described low rate collection is to deposit push-up storage FIFO2 in after the described Wave data A that collects is taken out a compression; The external modulus converter A/D of described FPGA.

2. a kind of hardware based transient voltage recording method as claimed in claim 1 is characterized in that, carries out in the Real Time Compression module of the Real Time Compression of described data in FPGA; Described Real Time Compression module comprises d type flip flop 1, counter 1, comparer 1, sequential control circuit and push-up storage FIFO; Described Real Time Compression carries out comprising when comparing in real time following situation to Wave data A and the base value B in the d type flip flop 1 that collects in comparer 1:

When A, described Wave data A compared less than ratio of compression delta with described base value B, described d type flip flop 1 was closed, and described Wave data A is dropped, and described counter 1 adds 1, described FIFO to write enable signal invalid, do not have data to write described FIFO;

When B, described Wave data A compare greater than ratio of compression delta with described base value B, described FIFO to write enable signal effective, the count value in the described base value B sum counter is saved to described FIFO, described counter 1 zero clearing, described d type flip flop 1 is opened, and described Wave data A replaces base value B.

3. a kind of hardware based transient voltage recording method as claimed in claim 1 is characterized in that, carries out in the peak value computing module of peak value calculating in FPGA of described data; Described peak value computing module comprises d type flip flop 2, d type flip flop 3, comparer 2, comparer 3, comparer 4 sum counters 2; Described peak value calculates described Wave data A and the maximal value Max that collects, comprises following situation when minimum M in compares:

A, when A＞Max, described comparer 2 is output as high level, described d type flip flop 2 is opened, described Wave data A replaces maximal value Max;

B, when A＜Min, described comparer 3 is output as high level, described d type flip flop 3 is opened, described Wave data A replaces minimum M in;

C, whenever once compare, described counter 2 adds 1, and when the value D of described counter 2 is added to given cycle count value D0, promptly during D＞=D0, described comparer 4 is output as high level.

4. a kind of hardware based transient voltage recording method as claimed in claim 1 is characterized in that, the triggering of described data judges it is to trigger in the judge module at the upper limit, lower limit to carry out; The described upper limit, lower limit trigger judge module and comprise comparer 5 and comparer 6; The described upper limit, lower limit trigger judges the following situation that comprises:

(1) described Wave data A and given triggering higher limit up_limit are compared in described comparer 5, when A＞up_limit, satisfy upper limit trigger condition, the then effective output low level of up_valid;

(2) described Wave data A and given triggering lower limit down_limit are compared in described comparer 5, when A＜down_limit, satisfy lower limit trigger condition, the then effective output low level of down_valid.

5. a kind of hardware based transient voltage recording method as claimed in claim 1 is characterized in that, the low rate of described data is captured in the low rate acquisition module among the FPGA carries out; Described low rate acquisition module comprises push-up storage FIFO2, counter 3 and comparer 7; Described low rate collection comprises following situation when the described Wave data A that collects is taken out some compression:

1. value C and the divider ratio F with described counter 3 compares in described comparer 7, and when C＜F, described comparer 7 is output as low level, FIFO2 to write enable signal invalid, do not have data to write FIFO2;

2. value C and the divider ratio F with described counter 3 compares in described comparer 7, and when C＞F, described comparer 7 is output as high level, FIFO2 to write enable signal invalid, described Wave data A is write FIFO2.

6. a kind of hardware based transient voltage recording method as claimed in claim 1 is characterized in that described modulus converter A/D carries out analog to digital conversion in rising edge of clock signal; The negative edge that described Real Time Compression, peak value calculating, triggering judgement and low rate are captured in clock signal carries out simultaneously.

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