CN102157560A - High-voltage LDMOS (landscape diffusion metal oxide semiconductor) device - Google Patents

Abstract

The invention relates to a high-voltage LDMOS device, which includes a substrate, an epitaxial layer located on the substrate, a drift region located on the side of the drain region above the epitaxial layer and whose lower surface coincides with the lower surface of the epitaxial layer, and located on both sides of the LDMOS device. At least one pair of n-type semiconductor regions and p-type semiconductor regions arranged alternately across the lower surface of the epitaxial layer on the interface between the substrate and the epitaxial layer, the n-type semiconductor region and the p-type semiconductor region The junction surface of the power device is parallel to the surface voltage drop direction when the power device is in operation, and the n-type semiconductor region and the p-type semiconductor region are closely arranged to form a PN junction. The beneficial effects of the present invention are: the n-type semiconductor region and the p-type semiconductor region in the present invention are also collectively referred to as the reduced surface electric field layer in the body, and this LDMOS device with the reduced surface electric field layer in the body effectively solves the problem of the existing LDMOS The device improves the reverse withstand voltage and reduces the contradiction of the forward conduction resistance.

Description

A high voltage LDMOS device

technical field

The invention relates to semiconductor high-voltage and low-resistance devices in the field of electronic technology, in particular to high-voltage power devices manufactured on bulk silicon.

Background technique

With the rapid development of the semiconductor industry, PIC (Power Integrated Circuit, power integrated circuit) is continuously used in many fields, such as motor control, flat panel display drive control, computer peripheral drive control, etc., the PIC circuit used Among power devices, LDMOS (Lateral Double Diffused MOSFET, lateral double diffused metal oxide semiconductor field effect transistor) high-voltage devices have high operating voltage, simple process, and are easy to be compared with low-voltage CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) circuits. Compatibility in technology and other characteristics have attracted widespread attention. However, for semiconductor high-voltage power devices made of Si (silicon) materials, the forward conduction resistance of LDMOS devices is larger than that of VDMOS (Vertical Double Diffused MOSFET, vertical double-diffused metal-oxide-semiconductor field-effect transistors). A higher forward on-resistance leads to an increase in device size, thereby increasing manufacturing costs. Figure 1 is a schematic diagram of the structure of a conventional LDMOS device with N epitaxy. In the figure, the LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a well region 5, a source region 6, a drain electrode 7, a source electrode 8, The gate 9, the substrate 1 is p-type, and the epitaxial layer 2 is n-type. When the LDMOS device is n-type, the well region 5 is p-type, the drift region 3 is n ^- type, the drain region 4 and the source region 6 are n ⁺ type, and vice versa; when the LDMOS device is p-type, the well region 5 is n-type type, the drift region 3 is p ^- type, and the drain region 4 and source region 6 are p ⁺ type. Figure 2 is a schematic diagram of the structure of a conventional N-channel LDMOS device with P epitaxy. In the figure, the LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a source region 6, a drain 7, a source 8, a gate Pole 9, substrate 1 and epitaxial layer 2 are p-type, drift region 3 is n ^- type, drain region 4 and source region 6 are n ⁺ type, drain 7, source 8 and gate 9 are metal electrodes. Figure 3 is a schematic diagram of the structure of a conventional P-channel LDMOS device with P epitaxy. In the figure, the LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a well region 5, a source region 6, a drain 7, a source Pole 8, gate 9, substrate 1 and epitaxial layer 2 are p-type, well region 5 is n-type, drift region 3 is p ^- type, drain region 4 and source region 6 are p ⁺ type. In the LDMOS device, the drift region 3 used to bear the withstand voltage needs to be doped with a low concentration, but on the other hand, in order to reduce the on-resistance of the LDMOS device during forward conduction, the drift region 3 as the current channel is required to have high doping Concentration, which forms a contradiction between the breakdown voltage BV and the on-resistance R _on . Taking common MOS (Metal-Oxide-Semiconductor, Metal-Oxide-Semiconductor) devices as an example, the specific relationship is as follows:

$R_{\mathrm{on}}=\frac{L_{\mathrm{D.}}}{{\mathrm{q\μ}}_{\mathrm{no}}{N}_{\mathrm{D.}}}=5.39\×{10}^{-9}{\left(\mathrm{BV}\right)}^{2.5}$ (for N-type MOS)

$R_{\mathrm{on}}=\frac{L_{\mathrm{D.}}}{{\mathrm{q\μ}}_p{N}_{\mathrm{D.}}}=1.63\×{10}^{-8}{\left(\mathrm{BV}\right)}^{2.5}$ (for P-type MOS)

Among them, _LD is the length of the drift region, _ND is the concentration of the drift region, μ _n and μ _p are the mobility of electrons and holes, respectively, and q is the charge of electrons. It can be seen that the on-resistance of a MOS device is proportional to the length of the drift region and inversely proportional to its concentration. The shorter the length and the higher the concentration, the smaller the on-resistance. Since the LDMOS device is one of the MOS devices, the LDMOS device has the general characteristics of the MOS device. Therefore, in order to ensure a certain withstand voltage, the length of the drift region 3 of the LDMOS device cannot be made too short; its concentration cannot be made too high, otherwise breakdown will occur near the PN junction of the well region 5 under the gate 9, causing The reverse withstand voltage of the LDMOS device is reduced.

Contents of the invention

The object of the present invention is to provide a high-voltage LDMOS device to solve the contradiction of increasing the reverse withstand voltage and reducing the forward conduction resistance of the existing LDMOS device.

In order to achieve the above object, the technical solution of the present invention is a high-voltage LDMOS device, including a substrate, an epitaxial layer located on the substrate, located on the side of the drain region above the epitaxial layer, and the lower surface coincides with the lower surface of the epitaxial layer The drift region, the drain region and the source region located at both ends of the LDMOS device, has at least one pair of n-type semiconductor regions and p-type semiconductor regions arranged alternately across the lower surface of the epitaxial layer on the interface between the substrate and the epitaxial layer, n The interface between the p-type semiconductor region and the p-type semiconductor region is parallel to the surface voltage drop direction when the power device is in operation, and the n-type semiconductor region and the p-type semiconductor region are closely arranged to form a PN junction.

The beneficial effects of the present invention are: the n-type semiconductor region and the p-type semiconductor region in the present invention are also collectively referred to as a reduced surface electric field (RESURF) layer in the body, and this LDMOS device with a reduced surface electric field layer in the body effectively solves the problem Some LDMOS devices have the contradiction of increasing the reverse withstand voltage and reducing the forward conduction resistance, so that the forward conduction resistance can be effectively reduced under the same reverse withstand voltage, or the reverse conduction resistance can be effectively increased under the same forward conduction resistance. To pressure.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a conventional LDMOS device with N epitaxy.

FIG. 2 is a schematic diagram of the structure of a conventional N-channel LDMOS device with P epitaxy.

FIG. 3 is a schematic diagram of the structure of a conventional P-channel LDMOS device with P-epitaxy.

FIG. 4 is a schematic structural diagram of an LDMOS device according to Embodiment 1 of the present invention.

FIG. 5 is a schematic structural diagram of an LDMOS device according to Embodiment 2 of the present invention.

FIG. 6 is a schematic structural diagram of an LDMOS device according to Embodiment 3 of the present invention.

FIG. 7 is a schematic structural diagram of an LDMOS device according to Embodiment 4 of the present invention.

FIG. 8 is a schematic structural diagram of an LDMOS device according to Embodiment 5 of the present invention.

FIG. 9 is a schematic structural diagram of an LDMOS device according to Embodiment 6 of the present invention.

FIG. 10 is a schematic diagram of the structure of an LDMOS device according to Embodiment 7 of the present invention.

FIG. 11 is a schematic structural diagram of an LDMOS device according to Embodiment 8 of the present invention.

Description of reference numerals: substrate 1, epitaxial layer 2, drift region 3, drain region 4, well region 5, source region 6, drain 7, source 8, gate 9, n-type semiconductor region 10, p-type semiconductor Region 11, top buried layer 12.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Embodiment 1: As shown in FIG. 4, an LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a source region 6, a drain 7, a source 8, and a gate 9. In this embodiment, the LDMOS The device is a P epitaxial N-channel LDMOS device, so the substrate 1 and the epitaxial layer 2 are p-type, the drift region 3 is n ^- type, the drain region 4 and the source region 6 are n ⁺ type, and the epitaxial layer 2 is located on the substrate 1 Above, the drift region 3 is located on the side of the epitaxial layer 2 close to the drain region 4 and the lower surface spans the lower surface of the epitaxial layer 2, the drain region 4 and the source region 6 are located at both ends of the LDMOS device, between the substrate 1 and the epitaxial layer 2 There are two pairs of n-type semiconductor regions 10 and p-type semiconductor regions 11 arranged alternately across the lower surface of the epitaxial layer 2 on the interface, and when the interface between the n-type semiconductor regions 10 and the p-type semiconductor regions 11 is in operation with the power device The direction of the surface voltage drop is parallel, the length is consistent with the length of the drift region 3, and the n-type semiconductor region 10 and the p-type semiconductor region 11 are closely arranged to form a PN junction.

In this embodiment, the logarithm, shape, width, length and doping concentration of the n-type semiconductor region 11 and the p-type semiconductor region 12 can be set arbitrarily as required, and the logarithm, shape, width and length in the embodiment cannot be understood as Limitations on the Invention.

Take this embodiment as an example to illustrate the working principle of the present invention:

First of all, the n-type semiconductor region 10 and the p-type semiconductor region 11 in this embodiment are collectively referred to as a body reduced surface field (RESURF) layer. When the LDMOS device is forward-conducting, the semiconductor region of the reduced surface electric field layer with the same doping characteristics as the drift region 3 forms an equivalent resistance in parallel with the drift region 3, so the overall on-resistance of the LDMOS device can be effectively reduced, thereby reducing conduction loss purposes. As shown in the formula: R _on ＝R _contact +R _source +R _channel +R _drain +R _drift R _resurf /(R _drift +R _resurf ), where R _on is the on-resistance, R _contact is the contact resistance, and R _source is the source resistance, R _channel is the channel resistance, R _drift = ρ _d L _drift is the resistance of the drift region, R _drain is the resistance of the drain region, R _resurf is the resistance of the layer that reduces the surface electric field, ρ _d is the resistivity of the epitaxial layer, L _drift is the length of the drift region.

When the LDMOS device reverse withstand voltage, the lateral PN junction formed by the n-type semiconductor region 10 and the p-type semiconductor region 11 with opposite doping characteristics in the lower surface electric field layer depletes each other in the lateral direction, and the doping characteristics of the drift region 3 are opposite. The vertical PN junction formed by the semiconductor region and the drift region 3 is mutually depleted with the drift region 3 in the vertical direction. In the lateral direction, the flat electric field of the surface electric field reducing layer in the body will affect the surface electric field to make it relatively flat, which improves the surface withstand voltage of the LDMOS device. At the same time, in the vertical direction, the semiconductor region with the opposite doping characteristics to the drift region 3 forms a PN junction with the drift region 3, which also affects the vertical electric field in the body to make it flat, thereby increasing the vertical breakdown voltage. In a conventional LDMOS device, the in-body longitudinal breakdown voltage BV=E _C *t _epi , and the in-body longitudinal breakdown voltage BV is determined by the longitudinal critical electric field E _C (located between the epitaxial layer 2 and the substrate 1 ) and the thickness of the epitaxial layer 2 t _epi Decide. After adding the surface electric field reduction layer, if the same vertical breakdown voltage is to be maintained, the thickness t _epi of the epitaxial layer can be greatly reduced. When the surface electric field reduction layer is realized, the doping concentration N _epi and thickness t _epi of the epitaxial layer 2 satisfy the formula N _epi *t _epi =ε*E _c /q*sqrt(N _sub /(N _epi +N _sub )), In the formula, ε is the dielectric constant, q is the electron charge, and N _sub is the doping concentration of the substrate 1 . When the longitudinal critical electric field E _C is determined, _Nepi *t _epi can be regarded as a constant, so when the thickness tepi of the epitaxial layer 2 decreases, the doping concentration _{Nepi of} the epitaxial layer 2 _will increase. It can be seen that the structure provided by this embodiment can greatly reduce the forward conduction resistance after introducing the surface electric field reducing layer, so that the conduction loss of the device can be reduced, and the withstand voltage effect of the LDMOS device can be improved under the same forward conduction resistance. ; and while ensuring the withstand voltage, the thickness of the epitaxial layer 2 can be reduced, the concentration of the drift region can be increased, and the forward conduction resistance of the drift region can be reduced.

Embodiment two: as shown in Figure 5, on the basis of embodiment one, in order to prevent the PN junction formed by the n-type semiconductor region 10 and the p-type semiconductor region 11 from affecting the electric field of the drain region 4, the n-type semiconductor region 10 and the p-type semiconductor region The length of the semiconductor region 11 can be shortened to the interface between the drain region 4 toward the center and the drift region 3 .

Embodiment 3: As shown in FIG. 6 , on the basis of Embodiment 1 or Embodiment 2, in order to prevent the n-type semiconductor region 10 and the p-type semiconductor region 11 from affecting the source region 6, the n-type semiconductor region 10 and the p-type semiconductor region 11 can be combined The length of the p-type semiconductor region 11 is shortened so that it is not connected to the interface between the drift region 3 facing the source region 6 and the epitaxial layer 2 .

Embodiment 4: As shown in FIG. 7, on the basis of Embodiment 1 or Embodiment 2 or Embodiment 3, in order to adjust the reverse withstand voltage of the LDMOS device, the n-type semiconductor region 10, the p-type semiconductor region 11 and the drift region 3 The charge balance of the top surface of the drift region 3 is added to the upper surface of the drift region 3 , and the doping characteristics of the top buried layer 12 are opposite to those of the drift region 3 .

Embodiment 5: As shown in FIG. 8, the LDMOS device includes a substrate 1, an epitaxial layer 2, a drift region 3, a drain region 4, a well region 5, a source region 6, a drain electrode 7, a source electrode 8, and a gate electrode 9. In the embodiment, the LDMOS device is an N-epitaxial N-channel LDMOS device. The substrate 1 and the well region 5 are p-type, the epitaxial layer 2 is n-type, the drift region 3 is n ^- type, the drain region 4 and the source region 6 are n ⁺ type, the epitaxial layer 2 is located on the substrate 1, and the drift region 3 is located on the side of the epitaxial layer close to the drain region 4 and the lower surface of the drift region 3 coincides with the interface between the substrate 1 and the epitaxial layer 2, the drain region 4 and the source region 6 are located at both ends of the LDMOS device, and between the substrate 1 and the epitaxial layer There are two pairs of n-type semiconductor regions 10 and p-type semiconductor regions 11 arranged alternately across the lower surface of the epitaxial layer 2 on the interface of the epitaxial layer 2, and the interface between the n-type semiconductor regions 10 and the p-type semiconductor regions 11 and the power device The surface voltage drop directions during operation are parallel, and the length extends from below the source terminal to below the drain terminal. The n-type semiconductor region 10 and the p-type semiconductor region 11 are closely arranged to form a PN junction. The working principle of this embodiment is the same as that of Embodiment 1.

In this embodiment, the n-type semiconductor region 11 and the p-type semiconductor region 12 can also set the logarithm, shape, width, length and doping concentration arbitrarily according to needs, and the logarithm, shape, width and length in the embodiment cannot be understood To limit the present invention.

Embodiment 6: As shown in FIG. 9, on the basis of Embodiment 5, in order to prevent the PN junction formed by the n-type semiconductor region 10 and the p-type semiconductor region 11 from affecting the electric field of the drain region 4, the n-type semiconductor region 10 and the p-type semiconductor region The length of the semiconductor region 11 can be shortened to the interface between the drain region 4 toward the center and the drift region 3 .

Embodiment 7: As shown in FIG. 10, in order to prevent the n-type semiconductor region 10 and the p-type semiconductor region 11 from affecting the source region 6, the lengths of the n-type semiconductor region 10 and the p-type semiconductor region 11 can be shortened to the source region 6 The interface between the central side and the well region 5 .

Embodiment 8: As shown in FIG. 11 , on the basis of Embodiment 5 or Embodiment 6 or Embodiment 7, in order to adjust the reverse withstand voltage of the LDMOS device, the n-type semiconductor region 10, the p-type semiconductor region 11 and the drift region 3 The charge balance of the top surface of the drift region 3 is added to the upper surface of the drift region 3 , and the doping characteristics of the top buried layer 12 are opposite to those of the drift region 3 .

Those skilled in the art will appreciate that the embodiments described here are to help readers understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (9)

1. A high-voltage LDMOS device, comprising a substrate (1), an epitaxial layer (2) located on the substrate (1), located on the side of the epitaxial layer (2) near the drain region (4) and the lower surface and The drift region (3) where the lower surface of the epitaxial layer (2) overlaps, the drain region (4) and the source region (6) located at both ends of the LDMOS device, is characterized in that, between the substrate (1) and the epitaxial layer (2) There are at least one pair of n-type semiconductor regions (10) and p-type semiconductor regions (11) arranged alternately across the lower surface of the epitaxial layer (2) on the interface, and the n-type semiconductor regions (10) and p-type semiconductor regions (11) ) is parallel to the surface voltage drop direction when the power device is in operation, and the n-type semiconductor region (10) and the p-type semiconductor region (11) are closely arranged to form a PN junction. 2 . The high-voltage LDMOS device according to claim 1 , wherein the high-voltage LDMOS device is a P-epitaxy N-channel LDMOS device. 3. A high-voltage LDMOS device according to claim 2, characterized in that the lengths of the n-type semiconductor region (10) and the p-type semiconductor region (11) can be shortened to the side of the drain region (4) toward the center At the interface with the drift region (3). 4. A kind of high-voltage LDMOS device according to claim 2, is characterized in that, the length of described n-type semiconductor region (10) and p-type semiconductor region (11) is shortened to be not with drift region (3) to source region (6) One side is connected to the interface of the epitaxial layer (2). 5. A kind of high voltage LDMOS device according to claim 2, it is characterized in that, add top buried layer (12) on the upper surface of drift region (3), the doping characteristic of described top buried layer (12) and drift Area (3) is the opposite. 6 . The high-voltage LDMOS device according to claim 1 , wherein the high-voltage LDMOS device is an N-epitaxial N-channel LDMOS device. 7. A high-voltage LDMOS device according to claim 6, characterized in that the lengths of the n-type semiconductor region (10) and the p-type semiconductor region (11) can be shortened to the side of the drain region (4) towards the center At the interface with the drift region (3). 8. A kind of high-voltage LDMOS device according to claim 6, is characterized in that, the length of described n-type semiconductor region (10) and p-type semiconductor region (11) is shortened to source region (6) towards the central side and At the interface of the well region (5). 9. A kind of high-voltage LDMOS device according to claim 6, it is characterized in that, add top buried layer (12) on the upper surface of drift region (3), the doping characteristic of described top buried layer (12) and drift Area (3) is the opposite.

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