CN102116979A - Liquid crystal display device having a plurality of pixel electrodes - Google Patents
Liquid crystal display device having a plurality of pixel electrodes Download PDFInfo
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- CN102116979A CN102116979A CN 200910248078 CN200910248078A CN102116979A CN 102116979 A CN102116979 A CN 102116979A CN 200910248078 CN200910248078 CN 200910248078 CN 200910248078 A CN200910248078 A CN 200910248078A CN 102116979 A CN102116979 A CN 102116979A
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Abstract
The liquid crystal display device comprises a pixel array formed by a plurality of sub-pixel arrays arranged in an array mode, wherein each sub-pixel array comprises a structure of two rows and two columns of pixels formed by four pixel electrodes, four thin film transistors, a data line and four scanning lines arranged in sequence, the source electrodes of the four thin film transistors share the data line, the drain electrode of each thin film transistor is connected with one pixel electrode, the grid electrodes of two thin film transistors in one column are respectively connected with the two scanning lines in the middle, the grid electrodes of two thin film transistors in the other column are connected with the other two scanning lines, and when the liquid crystal display device is driven, the four scanning lines are scanned in sequence. The invention avoids the vertical bar phenomenon caused by the uneven periodic gray scale because the pixel electrodes with gray scale change are arranged on different columns, and ensures the aperture opening ratio.
Description
Technical field
The present invention relates to liquid crystal indicator, relate in particular to the pel array of liquid crystal indicator.
Background technology
See also Fig. 1 to shown in Figure 3, prior art provides a kind of pel array of liquid crystal indicator, this pel array comprises a plurality of array of sub-pixels 1 of arranging with array way, each array of sub-pixels 1 comprises four pixel electrode 11A, 11B, 11C and 11D, four thin film transistor (TFT) 12A, 12B, 12C and 12D,, the structure of two row, two row formed of data line S11 and four sweep trace G11 to G14 arranging in regular turn, in this structure, the drain electrode of each thin film transistor (TFT) is connected with a pixel electrode, the grid of pixel electrode of each row by thin film transistor (TFT) connects two sweep traces respectively and forms dual scanning line structure (dual gate), concrete, pixel electrode 11A and 11B are respectively by thin film transistor (TFT) 12A, 12B is connected in sweep trace G11 and G12, pixel electrode 11C and 11D are respectively by thin film transistor (TFT) 12C, 12D is connected in sweep trace G14 and G13, the shared data line of the source electrode of four thin film transistor (TFT)s, concrete, the source electrode of pixel electrode 11A and the 11D of first row by thin film transistor (TFT) 12A and 12D and data line S11 are connected and are positioned at the left side of data line S11, and secondary series pixel electrode 11B and 11C pass through thin film transistor (TFT) 12B, 12C and data line S11 are connected and are positioned at the right side of data line S11.Fig. 1 only is a synoptic diagram, has expressed the pel array of 4 row, 6 row of being made up of six array of sub-pixels 1, and in actual production technology, the pel array of liquid crystal indicator is made up of a plurality of array of sub-pixels 1.
See also Fig. 1, Fig. 2 and Fig. 3, with Vcom (public electrode) direct current, " two dot inersion " (two 1 groups, reversal of poles) situation is an example, the procedure for displaying of the pel array that above-mentioned array of sub-pixels 1 is formed is as follows: at first open sweep trace G11, sweep trace G11 opens the thin film transistor (TFT) of first row, first row, the 3rd row and the 5th row that are connected in sweep trace G11 to pixel electrode 11A charging, after charging is finished, and the data input pixel electrode 11A of data line S11, S12 and S13; Then, close sweep trace G11, sweep trace G12 open thin film transistor (TFT) and to first the row secondary series, the pixel electrode 11B charging of the 4th row and the 6th row, in process to pixel electrode 11B charging, between first row and the secondary series because data line S11 arranged, the distance of two row is done greatlyyer, the influence of stray capacitance (not shown) is less, can ignore, and between secondary series and the 3rd row because there is not a data line, in order to improve aperture opening ratio, do the distance of two row less, stray capacitance 12 influences are bigger, therefore, the first row secondary series, the voltage of the pixel electrode 11B of the 4th row can influence first row the 3rd row, voltage on the pixel electrode 11A of the 5th row makes the voltage of pixel electrode 11A change (such as reducing), thereby, first row the 3rd row, the GTG of the pixel electrode 11A of the 5th row raises, after the pixel electrode 11B charging of first row is finished, data line S 11, the data input pixel electrode 11B of S12 and S 13, close sweep trace G12 then, open sweep trace G13, sweep trace G13 is listed as second row first by thin film transistor (TFT), the pixel electrode 11D charging of the 3rd row and the 5th row, the data input pixel electrode 11D of data line S11, open the secondary series of sweep trace G14 then to second row, the pixel electrode 11C charging of the 4th row and the 6th row, same, at secondary series to second row, in the process of the pixel electrode 11C charging of the 4th row and the 6th row, secondary series, the pixel electrode 11C of the 4th row and the 6th row makes the GTG of pixel electrode 11D raise by the voltage that stray capacitance influences the pixel electrode 11D of second row the 3rd row and the 5th row.
From the above analysis, the pixel electrode that gray scale variation takes place is pixel electrode 11A and the 3rd row of second row and the pixel electrode 11D of the 5th row of first row the 3rd row and the 5th row, and gray scale variation does not take place in the secondary series of the secondary series of first row and the 4th row and second row and the 4th row, by that analogy, in entire pixel array, the change in voltage of the pixel electrode on the odd column and make GTG change always, and GTG does not change on the even column, therefore, the pixel that gray scale variation takes place concentrates on one and lists, on macroscopic view, on the display screen in liquid crystal indicator vertical bar can appear because the periodicity GTG is uneven.
In addition, produce the phenomenon of vertical bar for the influence that reduces stray capacitance, at present, can strengthen the distance between the adjacent two row pixels,, still, like this, can reduce aperture opening ratio to reduce the influence of stray capacitance.
Summary of the invention
The technical matters that the present invention solves is that the periodicity GTG inequality of liquid crystal indicator causes the vertical bar phenomenon and strengthens the distance between the two row pixels and influence the problem of aperture opening ratio.
For addressing the above problem, the invention provides a kind of liquid crystal indicator, comprise the pel array that constitutes by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels formed of data line and four sweep traces arranging in regular turn, the shared described data line of the source electrode of described four thin film transistor (TFT)s, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan described four sweep traces successively.
Alternatively, described each sub-pixel array structure is identical.
Alternatively, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the odd column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of entire pixel array.
Alternatively, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the even column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the odd column of entire pixel array.
Alternatively, in the described pel array, in adjacent four array of sub-pixels that are arranged in delegation, the structure of each array of sub-pixels is incomplete same.
Alternatively, in the described pel array, in adjacent four array of sub-pixels that are arranged in matrix pattern, the structure of each array of sub-pixels is incomplete same.
Alternatively, there are three sub-pixel array structure identical in described four array of sub-pixels.
Alternatively, there is the structure of two array of sub-pixels identical in described four array of sub-pixels.
Compared with prior art, the present invention is because in the two row thin film transistor (TFT)s that are connected with data line, wherein a row thin film transistor (TFT) is connected with two sweep traces of centre respectively, the thin film transistor (TFT) of other row is connected with the two other sweep trace, and when described liquid crystal indicator drives, scan described four sweep traces successively.Therefore, in an array of sub-pixels, the voltage of the pixel electrode of another array of sub-pixels that influence row is adjacent in two pixel electrodes of same row and gray scale variation takes place, the pixel voltage of another pixel electrode then be subjected to adjacent another array of sub-pixels of its row pixel electrode influence and gray scale variation takes place, therefore, in entire pixel array, the pixel electrode that gray scale variation takes place is dispersed to different listing, and unlike prior art, always concentrating on one lists, therefore, the vertical bar phenomenon that the present invention has avoided periodicity GTG inequality to cause by the grid and the connected mode between the sweep trace of the thin film transistor (TFT) of adjustment pixel electrode, and the distance that need not increase between the two adjacent pixels just can achieve the goal, the aperture opening ratio that has guaranteed.
Description of drawings
Fig. 1 is the structural representation of the pel array of existing liquid crystal indicator;
Fig. 2 is the synoptic diagram during the N two field picture among Fig. 1;
Fig. 3 is the synoptic diagram during the N+1 two field picture among Fig. 1;
Fig. 4 is the structural representation of pel array first embodiment of liquid crystal indicator of the present invention;
Fig. 5 is the structural representation of pel array second embodiment of liquid crystal indicator of the present invention;
Fig. 6 is the structural representation of pel array the 3rd embodiment of invention liquid crystal indicator of the present invention;
Fig. 7 is the structural representation of pel array the 4th embodiment of liquid crystal indicator of the present invention;
Fig. 8 is the structural representation of pel array the 5th embodiment of liquid crystal indicator of the present invention;
Fig. 9 is the structural representation of pel array the 6th embodiment of liquid crystal indicator of the present invention;
Figure 10 is the structural representation of pel array the 7th embodiment of liquid crystal indicator of the present invention;
Figure 11 is the structural representation of pel array the 8th embodiment of liquid crystal indicator of the present invention.
Embodiment
The present inventor finds to make the pixel electrode that gray scale variation takes place be present in same listing and cause the vertical bar phenomenon because of the influence of stray capacitance in the process of making liquid crystal indicator.
The present inventor finds through performing creative labour, the grid of adjusting the thin film transistor (TFT) of each pixel electrode is distributed in different row with the feasible pixel electrode that gray scale variation takes place of the connected mode between the sweep trace, thereby, the vertical bar phenomenon of having avoided the pixel electrode of gray scale variation to concentrate on row and having caused, and, need not increase the distance of two adjacent column pixels, guarantee aperture opening ratio.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
See also Fig. 4, Fig. 4 represents first embodiment of this invention, and in this embodiment, the pel array of liquid crystal indicator comprises a plurality of first array of sub-pixels 2 of arranging with array way, and the structure of each first array of sub-pixels 2 is identical.With one of them first array of sub-pixels 2 is example, this first array of sub-pixels 2 comprises four pixel electrode 21A, 21B, 21C and 21D, four thin film transistor (TFT) 22A, 22B, 22C and 22D,, a data line S21 and four sweep trace G21 of arrangement in regular turn, G22, the structure of two row, two row that G23 and G24 form, in this structure, the pixel electrode of each row forms dual scanning line structure (dual gate) by two sweep traces of grid connection of thin film transistor (TFT) respectively, concrete, the pixel electrode 21A of first row and 21B are respectively by thin film transistor (TFT) 22A, 22B is connected in sweep trace G21 and G22, and the pixel electrode 21C of second row and 21D are respectively by thin film transistor (TFT) 22C, 22D is connected in sweep trace G23 and G24; The shared data line of the source electrode of two row thin film transistor (TFT)s, concrete, the thin film transistor (TFT) 22A of first row and the source electrode of 22D and data line S21 are connected and are positioned at the left side of data line S21, and the source electrode of secondary series thin film transistor (TFT) 22B and 22C and data line S21 are connected and are positioned at the right side of data line S21.In the two row thin film transistor (TFT)s that are connected with data line S21, wherein a row thin film transistor (TFT) 22B is connected with G23 with two sweep trace G22 of centre respectively with 22C, the thin film transistor (TFT) 22A of other row, 22D is connected with G24 with two other sweep trace G21, by that analogy to entire pixel array, be connected with four sweep traces that are arranged in order respectively at four thin film transistor (TFT)s of any adjacent two row that are connected with data line, wherein the grid of a row thin film transistor (TFT) is connected with two sweep traces in the middle of being positioned in these four sweep traces respectively, and the grid of the thin film transistor (TFT) of other row is connected with the two other sweep trace.Fig. 4 has shown 4 row, the 6 row picture element array structures of being made up of 6 first array of sub-pixels 2, in this structure, have three data line S21, S22 and S23, eight sweep trace G21, G22, G23, G24, G25, G26, G27 and G28 and some pixel electrode and thin film transistor (TFT)s that is positioned at sweep trace and data line intersection.Shown in 4 row, 6 row picture element array structures in, what the thin film transistor (TFT) that is connected with two sweep traces of centre was positioned at this structure is secondary series, the 4th row and the 6th row, the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at first row, the 3rd row and the 5th row of this structure, by that analogy to entire pixel array, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the even column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is in the odd column of entire pixel array.
Please continue to consult Fig. 4, the procedure for displaying of this embodiment is as follows, at first, makes sweep trace G21 open to sweep trace G21 input scan signal.After sweep trace G21 opened, the pixel electrode 21A of first row of first row, the 3rd row and the 5th row was recharged; Then, close sweep trace G21, the thin film transistor (TFT) 22A that is connected with pixel electrode 21A turn-offs, pixel electrode 21A enters the voltage hold mode, open sweep trace G22, the secondary series of first row, the pixel electrode 21B of the 4th row and the 6th row is recharged, because the pixel electrode 21A of adjacent two row, exist between the 21B stray capacitance (such as, there is stray capacitance between the pixel electrode 21B of secondary series and the tertial pixel electrode 21A), below be that example illustrates present embodiment just with first row secondary series and the tertial pixel electrode 21B and 21A and the second row secondary series and tertial pixel electrode 21C and 21D, in the process that the pixel electrode 21B of the first row secondary series is recharged, voltage on the pixel electrode 21B of the first row secondary series changes the voltage of the tertial pixel electrode 21A of row that wins by stray capacitance, such as, voltage decreases on the tertial pixel electrode 21A of first row, for the normal mutually white mode of twisted-nematic, the GTG of the tertial pixel electrode 21A of this first row raises; Follow again, close sweep trace G22, open sweep trace G23, the pixel electrode 21C of the second row secondary series that is connected with sweep trace G23 is recharged (certainly, at this moment, the 4th row of second row and the pixel electrode 21C of the 6th row also can be recharged), after turn-offing sweep trace G23, the pixel electrode 21C of the second row secondary series enters the voltage hold mode, then, open sweep trace G24, the pixel electrode 21D that is connected with sweep trace G24 is recharged (certainly, at this moment, the pixel electrode 21D of second row the 3rd row and the 5th row also can be recharged), the tertial pixel electrode 21D of second row is in the process of charging, equally, owing to have stray capacitance, the voltage on the pixel electrode 21C of the voltage influence second row secondary series of the tertial pixel electrode 21D of second row, thereby the GTG of pixel electrode 21C uprises.
To sum up, the tertial pixel electrode of first row that gray scale variation takes place for the first time is 21A, the pixel electrode that the second row secondary series of gray scale variation takes place for the second time is 21C, pixel electrode 21A and pixel electrode 21C do not list same, by that analogy to entire pixel array, the pixel electrode that gray scale variation takes place is not just at same row, compare in the situation of same row with the pixel electrode that gray scale variation takes place in the prior art, this implementation column has avoided periodicity GTG inequality to cause the situation of vertical bar, but also need not increase distance (secondary series and the 3rd row between) between adjacent two row, guaranteed aperture opening ratio.
See also Fig. 5, Fig. 5 is the second embodiment of the present invention, and among this embodiment, the pel array of described liquid crystal indicator also comprises a plurality of second array of sub-pixels 3 of arranging with array way, and the structure of each second array of sub-pixels 3 is identical.With one of them second array of sub-pixels 3 is example, second array of sub-pixels 3 comprises four pixel electrode 31A, 31B, 31C and 31D, four thin film transistor (TFT) 32A, 32B, 32C and 32D,, a data line S31 and four sweep trace G31 of arrangement in regular turn, G32, the structure of two row, two row that G33 and G34 form, in this structure, the pixel electrode of each row forms dual scanning line structure (dual gate) by two sweep traces of grid connection of thin film transistor (TFT) respectively, concrete, the pixel electrode 31A of first row and 31B are respectively by thin film transistor (TFT) 32A, 32B is connected in sweep trace G32 and G31, and the pixel electrode 31C of second row and 31D are respectively by thin film transistor (TFT) 32C, 32D is connected in sweep trace G34 and G33; The shared data line of the source electrode of two row thin film transistor (TFT)s, concrete, the thin film transistor (TFT) 32A of first row and the source electrode of 32D and data line S31 are connected and are positioned at the left side of data line S31, and the source electrode of secondary series thin film transistor (TFT) 32B and 32C and data line S31 are connected and are positioned at the right side of data line S31.In the two row thin film transistor (TFT)s that are connected with data line S31, wherein the grid of a row thin film transistor (TFT) 32A, 32D is connected with G33 with sweep trace G32, and the grid of an other row thin film transistor (TFT) 32B, 32C is connected with G34 with two other sweep trace G31.By that analogy to whole pixel permutation, by that analogy to entire pixel array, be connected with four sweep traces that are arranged in order respectively at four thin film transistor (TFT)s of any adjacent two row that are connected with data line, wherein the grid of a row thin film transistor (TFT) is connected with two sweep traces in the middle of being positioned in these four sweep traces respectively, and the grid of the thin film transistor (TFT) of other row is connected with the two other sweep trace.Fig. 5 has shown the structure of 4 row, 6 row of being made up of 6 second array of sub-pixels 3, in this structure, have three data line S31, S32 and S33, eight sweep trace G31, G32, G33, G34, G35, G36, G37 and G38 and some pixel electrode and thin film transistor (TFT)s that is positioned at sweep trace and data line intersection.Shown in the pel array of 4 row 6 row in, what the thin film transistor (TFT) that is connected with two sweep traces of centre was positioned at this structure is first row, the 3rd row and the 5th row, the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at secondary series, the 4th row and the 6th row of this structure, by that analogy to entire pixel array, the thin film transistor (TFT) that two middle sweep traces connect is positioned at the odd column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of entire pixel array.
Please continue to consult Fig. 5, because among this embodiment, the course of work of sweep trace and data line is identical, therefore, does not repeat them here.Be that example is described only below to affected pixel electrode, in this embodiment, the tertial pixel electrode 31A of first row influences the pixel electrode 31B of the first row secondary series and makes the GTG of pixel electrode 31B change, the pixel electrode 31C of the second row secondary series influences the second tertial pixel electrode 31D of row and makes the GTG of pixel electrode 31D change, in this embodiment, pixel 31B that GTG changes and 32D do not list same, by that analogy to the pel array of entire liquid crystal display device, the pixel electrode that gray scale variation takes place is not just at same row, thereby, the vertical bar phenomenon of having avoided the pixel electrode of grey scale transformation to concentrate on row and having caused, and, need not increase the distance between the two adjacent column pixels, guarantee aperture opening ratio.
In Fig. 4 and the pel array shown in Figure 5, the structure of each array of sub-pixels is identical, and certainly, the structure of each array of sub-pixels in the pel array also can be inequality, be example with Fig. 6 to Figure 10 below, the structure of the different pel array of sub-pixel array structure be described as follows:
See also Fig. 6, Fig. 6 is the third embodiment of the present invention, in this embodiment, line up matrix pattern in adjacent four array of sub-pixels, in these four pel arrays, there is the structure of three array of sub-pixels identical, concrete, comprise three second array of sub-pixels 3 and one first array of sub-pixels 2, described first array of sub-pixels 2 is positioned at the lower right corner of matrix pattern, in this embodiment, all is at sweep trace G41, G42, G43, G44, G45, G46, G47 with open after G48 obtains corresponding sweep signal successively be connected with pixel electrode thin film transistor (TFT), corresponding then data-signal does not repeat them here the input of signal by data line S41 and S42 input.In Fig. 6, the thin film transistor (TFT) of the first row secondary series and tertial pixel electrode is scanned line G41 and opens simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned line G44 simultaneously and opens, therefore, stray capacitance can not influence the GTG of pixel electrode, the sweep signal of obtaining G45 when the thin film transistor (TFT) of the pixel electrode 41B of the third line secondary series is opened and when entering the voltage hold mode, when sweep trace G46 charges to the tertial pixel electrode 41A of the third line, the pixel electrode 41B that this pixel electrode 41A can influence the third line secondary series makes the GTG of pixel electrode 41B change, same reason, obtain the signal of sweep trace G47 and when entering the voltage hold mode at the thin film transistor (TFT) of the tertial pixel electrode 41D of fourth line, the pixel electrode 41C of fourth line secondary series can influence the voltage of the tertial pixel electrode 41D of fourth line and make the GTG of pixel electrode 41D change, in this embodiment, the pixel electrode 41B of generation gray scale variation and 41D be not at same row, be pushed into entire pixel array with this reason class, the pixel electrode that gray scale variation takes place does not list same, therefore, the pixel electrode array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 7, Fig. 7 is the fourth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are arranged in matrix pattern, in these four array of sub-pixels, there is the structure of two array of sub-pixels identical, concrete, comprise two second array of sub-pixels 3 and two first array of sub-pixels 2, two second array of sub-pixels 3 form a line, two first array of sub-pixels 2 form a line, in this embodiment, when sweep trace was scanned line by line, the first row secondary series and the 3rd row were scanned line G51 simultaneously and open, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned line G54 simultaneously and opens, the thin film transistor (TFT) of the third line secondary series and tertial pixel electrode is scanned line G55 simultaneously and opens, the thin film transistor (TFT) of fourth line secondary series and tertial pixel electrode is scanned line G58 simultaneously and opens, and therefore, stray capacitance can not influence the GTG of pixel electrode, therefore, the pixel electrode array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 8, Fig. 8 is the fifth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are lined up in the matrix pattern, in these four array of sub-pixels, the structure of two array of sub-pixels that are in the crossed position is identical, concrete, comprise two second array of sub-pixels 3 and two first array of sub-pixels 2, two array of sub-pixels 2 are positioned on the diagonal line, two array of sub-pixels 3 are positioned on the diagonal line, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned line G62 simultaneously and open, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned line G63 simultaneously and opens, the thin film transistor (TFT) of the third line secondary series and tertial pixel electrode is scanned line G65 simultaneously and opens, the thin film transistor (TFT) of fourth line secondary series and tertial pixel electrode is scanned line G68 simultaneously and opens, therefore, stray capacitance can not influence the GTG of pixel electrode, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Fig. 9, Fig. 9 is the sixth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are lined up matrix pattern, in these four array of sub-pixels, there is the structure of three array of sub-pixels identical, concrete, comprise three first array of sub-pixels 2 and one second array of sub-pixels 3, second array of sub-pixels 3 is positioned at the lower left corner of matrix pattern, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned line G71 and open simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned line G74 simultaneously and opens, therefore, stray capacitance can not influence the GTG of pixel electrode, the sweep signal of obtaining G76 when the thin film transistor (TFT) of the pixel electrode 71B of the third line secondary series is opened and when entering the voltage hold mode, sweep trace G76 is in the time of the pixel electrode 71B of the third line secondary series charging, this pixel electrode 71B can influence the tertial pixel electrode 71A of the third line makes the GTG of pixel electrode 71A change, same reason, obtain the signal of sweep trace G77 and when entering the voltage hold mode at the thin film transistor (TFT) of the pixel electrode 71C of fourth line secondary series, the tertial pixel electrode 71D of fourth line can influence the fourth line secondary series pixel electrode 71C voltage and make the GTG of pixel electrode 71C change, in this embodiment, the pixel electrode 71A of generation gray scale variation and 71C be not at same row, be pushed into entire pixel array with this reason class, the pixel electrode that gray scale variation takes place does not list same, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
See also Figure 10, Figure 10 is the seventh embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are arranged in matrix pattern, in these four array of sub-pixels, there is the structure of three array of sub-pixels identical, concrete, comprise three first array of sub-pixels 2 and one second array of sub-pixels 3, described second array of sub-pixels 3 is positioned at the lower right corner of matrix pattern, in this embodiment, when sweep trace is scanned line by line, the first row secondary series and the 3rd row are scanned line G82 and open simultaneously, the thin film transistor (TFT) of the second row secondary series and tertial pixel electrode is scanned line G83 simultaneously and opens, therefore, stray capacitance can not influence the GTG of pixel electrode, when sweep signal that the thin film transistor (TFT) of the tertial pixel electrode 81A of the third line is obtaining sweep trace G85 be opened make that pixel electrode 81A enters the voltage hold mode in, sweep trace G86 is in the time of the pixel electrode 81B of the third line secondary series charging, this pixel electrode 81B can influence the tertial pixel electrode 81A of the third line makes the GTG of pixel electrode 81A change, same reason, obtain the signal of sweep trace G87 and when entering the voltage hold mode at the thin film transistor (TFT) of the pixel electrode 81C of fourth line secondary series, the tertial pixel electrode 81D of fourth line can influence the fourth line secondary series pixel electrode 81C voltage and make the GTG of pixel electrode 81C change, in this embodiment, the pixel electrode 81A of generation gray scale variation and 81C be not at same row, be pushed into entire pixel array with this reason class, the pixel electrode that gray scale variation takes place does not list same, therefore, the pel array of this embodiment the phenomenon that the GTG inequality causes vertical bar can not occur equally.
Above-mentioned the 3rd embodiment to the seven embodiment are all in adjacent four array of sub-pixels that are arranged in matrix pattern, the situation that the structure of each array of sub-pixels is incomplete same, but, predictably, when four array of sub-pixels are arranged in delegation or row, described liquid crystal indicator the phenomenon that the GTG inequality causes vertical bar can not occur equally
See also Figure 11, Figure 11 is the eighth embodiment of the present invention, in this embodiment, adjacent four array of sub-pixels are in line, in this embodiment, comprise three second array of sub-pixels 3 and one first array of sub-pixels 2, described three second array of sub-pixels 3 are adjacent, in this embodiment, described four pel arrays are lined up the structure of two row, eight row, in this structure, the pixel electrode 91B1 of the first row secondary series and tertial pixel electrode 91A are scanned line G92 and charge simultaneously, therefore, the phenomenon that the GTG inequality can not occur, equally, the pixel electrode 91C1 of the second row secondary series and tertial pixel electrode 91D are scanned line G93 and charge simultaneously, the phenomenon of GTG inequality also can not occur; The pixel electrode 91B of first row the 4th row is by the pixel electrode 91A influence of first row the 5th row and GTG changes, the pixel electrode 91D of second row the 5th row is by the pixel electrode 91C influence of second row the 4th row and GTG changes, thereby, pixel electrode 91D and 91B that gray scale variation takes place do not list same, thereby, can avoid the phenomenon of GTG inequality, same reason, the 91B of first row the 6th row of generation gray scale variation and the 91D of second row the 7th row be not at same row, therefore, in the situation that adjacent four array of sub-pixels are in line, the vertical bar phenomenon can not appear yet.By that analogy, described three second array of sub-pixels 3 and first array of sub-pixels 2 are arranged in a row according to other modes, also can avoid occurring the phenomenon of vertical bar.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (8)
1. liquid crystal indicator, comprise the pel array that constitutes by a plurality of array of sub-pixels of arranging with array way, each array of sub-pixels comprises four pixel electrodes, four thin film transistor (TFT)s,, the structure of two row, the two row pixels formed of data line and four sweep traces arranging in regular turn, the shared described data line of the source electrode of described four thin film transistor (TFT)s, the drain electrode of each thin film transistor (TFT) connects a pixel electrode, it is characterized in that, wherein the grid of two thin film transistor (TFT)s of row is connected with two sweep traces of centre respectively, the grid of two thin film transistor (TFT)s of other row is connected with the two other sweep trace, when described liquid crystal indicator drives, scan described four sweep traces successively.
2. liquid crystal indicator as claimed in claim 1 is characterized in that, described each sub-pixel array structure is identical.
3. liquid crystal indicator as claimed in claim 2, it is characterized in that, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the odd column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the even column of entire pixel array.
4. liquid crystal indicator as claimed in claim 2, it is characterized in that, the thin film transistor (TFT) that is connected with two sweep traces of centre is positioned at the even column of entire pixel array, and the thin film transistor (TFT) that is connected with the two other sweep trace is positioned at the odd column of entire pixel array.
5. liquid crystal indicator as claimed in claim 1 is characterized in that, in the described pel array, in adjacent four array of sub-pixels that are arranged in delegation, the structure of each array of sub-pixels is incomplete same.
6. liquid crystal indicator as claimed in claim 1 is characterized in that, in the described pel array, in adjacent four array of sub-pixels that are arranged in matrix pattern, the structure of each array of sub-pixels is incomplete same.
7. liquid crystal indicator as claimed in claim 6 is characterized in that, has three sub-pixel array structure identical in described four array of sub-pixels.
8. liquid crystal indicator as claimed in claim 6 is characterized in that, has the structure of two array of sub-pixels identical in described four array of sub-pixels.
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| CN 200910248078 CN102116979B (en) | 2009-12-31 | 2009-12-31 | Liquid crystal display device having a plurality of pixel electrodes |
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| CN 200910248078 CN102116979B (en) | 2009-12-31 | 2009-12-31 | Liquid crystal display device having a plurality of pixel electrodes |
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| CN102116979B CN102116979B (en) | 2013-05-01 |
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| CN102269903A (en) * | 2011-07-19 | 2011-12-07 | 南京中电熊猫液晶显示科技有限公司 | Pixel driving framework |
| WO2014153837A1 (en) * | 2013-03-27 | 2014-10-02 | 京东方科技集团股份有限公司 | Pixel structure and drive method thereof, display panel, and display device |
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