CN102073008A

CN102073008A - On-chip clock uncertainty measurement circuit device and system

Info

Publication number: CN102073008A
Application number: CN2010105347829A
Authority: CN
Inventors: 于航; 杨旭
Original assignee: BEIJING LOONGSON ZHONGKE TECHNOLOGY SERVICE CENTER Co Ltd
Current assignee: Loongson Technology Corp Ltd
Priority date: 2010-11-08
Filing date: 2010-11-08
Publication date: 2011-05-25
Anticipated expiration: 2030-11-08
Also published as: CN102073008B

Abstract

The invention provides an on-chip clock uncertainty measurement circuit device. The device comprises a delay circuit and a detection unit, wherein the delay circuit comprises a rough adjustment circuit and a fine adjustment circuit; two paths of clock signals A and B to be measured from two different measurement points of the same time source on a chip are roughly adjusted and delayed by the rough adjustment circuit; the roughly adjusted clock signals A and B are finely adjusted and delayed by the fine adjustment circuit; the phases of the finely adjusted clock signals A and B are detected by the detection unit; and the clock skew of the clock signals A and B is calculated when the phases of the finely adjusted clock signals A and B are the same. The invention also provides a measurement system which comprises the measurement circuit device and a ruler circuit. In the invention, on-chip measurement is performed on the clock skew and even clock jitter by using a composite non-linear delay line, so the measurement accuracy is high and the required data quantity is small.

Description

On-chip clock uncertainty measuring circuit device and system

Technical Field

The invention relates to the technical field of measurement of chip clock uncertainty, in particular to an on-chip measurement circuit device and system capable of measuring clock deviation and even clock jitter of a microprocessor.

Background

Computers now often need to use a clock, for example, to ensure that many operations occur in the correct order or synchronously. It is therefore important that the clocks themselves operate close to synchronization. Typically, the two clocks are not always perfectly synchronized and there is a timing difference between the clocks. In addition, the timing difference between the two clocks varies with time. This variation in clock timing difference is referred to as clock skew or clock skew. Many computer timing protocols require information such as the time offset between two clocks.

An On-Chip Clock Uncertainty Measurement (On-Chip Clock Uncertainty Measurement) system is suitable for processing a large amount of data, and meanwhile, the testability design is more suitable for testability chips and mass production.

As shown in fig. 1, the conventional uncertainty system of the on-chip measurement clock includes a skip circuit designed by International Business Machines Corporation (IBM Corporation) based on a Time-to-Digital converter (TDC) principle, which is a widely used uncertainty system of the on-chip measurement clock at present.

The SKITTER circuit comprises two Delay Lines (DL) which are composed of Inverters (INV) with the same low fan-out load, and the delay lines are long enough to ensure that at least one period of clock delay can still be accommodated when the working frequency is lowest; the delay line is then sampled by a D-type flip-flop (DFF) using a relative clock, and the sampled result is fed into a Scan Chain (Scan Chain) to obtain a Scan result as shown in fig. 2 for subsequent data analysis and operation.

The SKITTER circuit analyzes a single group of clock data, accumulates data in a plurality of periods, if the length of the clock period changes, the clock jitter (jitter) in the circuit is detected, and the size of the clock jitter (jitter) can be calculated through the delay and jitter stages of an Inverter (INV). For the simultaneous analysis of the two groups of clock data, if the same period edges of the two clocks have phase difference, the clock skew (skew) exists between the two clocks, and the magnitude of the clock skew can also be calculated through the delay of an Inverter (INV) and the series of the phase difference.

In IBM's design, the SKITTER circuit has 128 stages of Inverters (INV), each stage having a delay of 5-8 Picoseconds (PS), which is also the measurement accuracy of the circuit. Therefore, the measurement accuracy of the circuit is limited by the process.

In order to improve the measurement accuracy, a new circuit structure is proposed: vernier Delay Line (VDL), as shown in fig. 3, the Inverters (INV) forming two Delay lines have different delays, and the difference is τ, so that one clock signal samples another clock signal through one Delay Line, and each sampling has an accumulation of a small Delay difference equal to τ, similar to the principle of Vernier caliper. If the clock skew (skew) between the two clock signals is Tskew, the length of the delay line should be at least Tskew/τ, thus showing that the circuit scale is too large. In addition, due to the influence of factors such as Process, Voltage and Temperature Variation (PVT), and the like, a certain performance deviation exists between the discrete Inverters (INV), so that the measurement accuracy has an error of PS magnitude, and therefore, the circuit hardly has an ideal effect in practical application.

A Sub-Sampling method has also been proposed, in which a clock signal to be measured is sampled by a low-frequency Sampling signal, and a clock skew (skew) is calculated according to a statistical principle. However, this method requires the storage and calculation of a large amount of data, and also requires the introduction of a clock of another frequency, which is difficult in practice, so that no large-scale industrial application is available at present.

Through analysis, the prior arts mainly adopt a single linear delay mode to adjust the clock, and the main problems that the measurement range and the measurement precision are small, and the data amount required to be processed and the required circuit scale are large are faced. But longer delay lines also introduce greater noise. Moreover, for circuits such as the SKITTER, the measurement precision can be realized only by adopting a specific process due to excessive dependence on the process, and the universality is not realized.

Disclosure of Invention

The invention aims to provide a circuit device and a system for measuring on-chip clock uncertainty, which adopt a composite nonlinear delay line to carry out on-chip measurement on clock deviation and even clock jitter, and have high measurement precision and small required data volume.

To achieve the object of the present invention, there is provided a circuit device for measuring on-chip clock uncertainty, comprising: comprises a delay circuit and a detection unit; the delay circuit comprises a coarse tuning circuit and a fine tuning circuit; two paths of clock signals A and B to be measured from two different measuring points of the same time source on the chip; the delay circuit delays a clock signal a and a clock signal B:

after the coarse adjustment circuit performs coarse adjustment delay on the clock signal A and the clock signal B, the fine adjustment circuit performs fine adjustment delay on the clock signal A and the clock signal B after the coarse adjustment; the detection unit detects the phases of the clock signal A and the clock signal B after fine adjustment;

and when the phases of the clock signal A and the clock signal B after fine adjustment are the same, calculating to obtain the clock deviation of the clock signal A and the clock signal B according to the coarse adjustment delay and the fine adjustment delay of the clock signal A and the clock signal B after fine adjustment.

The above technical solution can be further improved in the following manner.

The coarse tuning circuit is a coarse tuning unit, and the fine tuning circuit is 2n +1 differential delay units connected in parallel, wherein n is a natural number; after the coarse tuning unit coarsely tunes and delays the clock signal A and the clock signal B, respectively dividing the coarsely tuned clock signal A and the coarsely tuned clock signal B into 2n +1 paths of parallel signals; then, inputting the 2n +1 paths of parallel signals into 2n +1 parallel differential delay units in pairs for fine adjustment; the delay difference formed by the 2n +1 parallel differential delay units to the two paths of clock signals passing through has the ratio of n: n-1: 0: - (n-1) to-n.

The difference delay unit comprises a first fine tuning unit and a second fine tuning unit; the clock signal A and the clock signal B after the coarse adjustment are respectively finely adjusted by a first fine adjustment unit and a second fine adjustment unit; the delay ratios of the first fine tuning unit and the second fine tuning unit in the 2n +1 difference delay units to the two paths of signals are n: 0 respectively; (n-1) to 0; ...; 0: 0; .., 0: n-1; 0: n.

The invention provides a system for measuring the uncertainty of an on-chip clock, which is characterized in that: the device comprises a measuring circuit device of on-chip clock uncertainty and a scale circuit; the on-chip clock uncertainty measuring circuit device comprises a delay circuit and a detection unit; the delay circuit comprises a coarse tuning circuit and a fine tuning circuit; two paths of clock signals A and B to be measured from two different measuring points of the same time source on the chip; the delay circuit delays a clock signal a and a clock signal B:

after the coarse tuning unit coarsely tunes and delays the clock signal A and the clock signal B, respectively dividing the coarsely tuned clock signal A and the coarsely tuned clock signal B into 2n +1 paths of parallel signals; then, inputting the 2n +1 paths of parallel signals into 2n +1 parallel differential delay units in pairs for fine adjustment; the delay difference formed by the 2n +1 parallel difference delay units to the two paths of clock signals is in a ratio of n to n-1: ...: 0.: - (n-1): n; the detection unit detects the phases of the clock signal A and the clock signal B after fine adjustment;

when the phases of the clock signal A and the clock signal B after fine adjustment are the same, calculating the clock deviation of the clock signal A and the clock signal B according to the coarse adjustment delay and the fine adjustment delay of the clock signal A and the clock signal B after fine adjustment;

the scale circuit comprises a delay cell ring oscillator and a difference delay cell ring oscillator; the delay unit ring oscillator is used for measuring the real size of the coarse adjustment precision of the measurement circuit device of the on-chip clock uncertainty, and the difference delay unit ring oscillator is used for measuring the real size of the fine adjustment precision of the measurement circuit device of the on-chip clock uncertainty.

The invention has the beneficial effects that: the on-chip clock uncertainty measuring circuit device and the on-chip clock uncertainty measuring system have the characteristics of less control data, large measuring range, high measuring precision and the like, and can reduce the area of an actual circuit to a certain extent.

Drawings

FIG. 1 is a schematic diagram of a prior art SKITTER circuit based on the time-to-digital converter principle;

FIG. 2 is a sample schematic of the circuit of FIG. 1;

FIG. 3 is a schematic diagram of a prior art vernier delay line circuit;

FIG. 4 is a circuit schematic of the on-chip clock uncertainty measurement circuit arrangement of the present invention;

wherein,

1 measurement circuit of clock skew and clock jitter:

111 a first multiplexer, 112 a second multiplexer;

121 a first coarse tuning unit input buffer, 122 a second coarse tuning unit input buffer;

131 a first coarse tuning unit, 132 a second coarse tuning unit;

141 a first fine input buffer, 142 a second fine input buffer;

15 difference delay unit;

FIG. 5 is a circuit schematic of the first coarse tuning unit shown in FIG. 4;

FIG. 6 is a circuit diagram of the differential delay unit of FIG. 4 implemented by adding load capacitors to form a plurality of parallel differential delay units;

FIG. 7 is a circuit schematic of the scale circuit of the present invention;

FIG. 8 is a circuit schematic of an alternative controller for a NAND gate (NAND) of the present invention;

FIG. 9 is a schematic diagram of a complementary symmetric structure of a NAND gate (NAND) of the present invention;

FIG. 10 is a schematic diagram of an inverter architecture employing a metal-oxide-semiconductor field effect transistor (MOS) load in accordance with the present invention;

fig. 11 is a circuit schematic of the phase detector of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the on-chip clock uncertainty measuring circuit apparatus and system of the present invention are further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The circuit device and the system for measuring the on-chip clock uncertainty utilize the principle of a Delay-Locked Loop (Delay-Locked Loop). The system for measuring the on-chip clock uncertainty comprises two parts: a Measurement circuit device 1 (SJM) for on-chip clock uncertainty; and a scale circuit (Ring).

The device comprises a measurement circuit device of on-chip clock uncertainty, a clock jitter measurement circuit device and a clock skew measurement circuit device, wherein the measurement circuit device of the on-chip clock uncertainty is used for measuring clock skew (skew) and clock jitter (jitter) of an on-chip clock; the circuit comprises a delay circuit (comprising a coarse adjusting circuit and a fine adjusting circuit), a detection unit and a sampling unit. The delay of the coarse tuning circuit to the clock signal is even times of the delay D of the basic delay unit (DC) (i.e. the accuracy of the coarse tuning circuit is the delay D of the basic delay unit (DC)), and the delay of the fine tuning circuit to the clock signal is less than the delay D of the basic delay unit (DC) (i.e. the accuracy of the fine tuning circuit is less than the delay D of the basic delay unit (DC)).

A circuit arrangement for measuring on-chip clock uncertainty, characterized by:

comprises a delay circuit and a detection unit; the delay circuit comprises a coarse tuning circuit and a fine tuning circuit; two paths of clock signals A and B to be measured from two different measuring points of the same time source on the chip; the delay circuit delays a clock signal a and a clock signal B:

and when the phases of the clock signal A and the clock signal B after fine adjustment are the same, calculating the clock deviation of the clock signal A and the clock signal B according to the coarse adjustment delay and the fine adjustment delay of the clock signal A and the clock signal B after fine adjustment.

Each difference delay unit comprises a first fine tuning unit and a second fine tuning unit; the clock signal A and the clock signal B after the coarse adjustment are respectively finely adjusted by a first fine adjustment unit and a second fine adjustment unit; the delay ratios of the first fine tuning unit and the second fine tuning unit in the 2n +1 difference delay units to the two paths of signals are n: 0 respectively; (n-1) to 0; ...; 0: 0; .., 0: n-1; 0: n.

The detection unit is 2n +1 phase detectors, and the 2n +1 phase detectors are respectively connected with the 2n +1 difference delay units; the phase discriminator compares the phases of the clock signal A and the clock signal B after fine adjustment, and

outputs

0 or 1.

When the output of the phase discriminator appears at the boundary between 0 and 1 (only the clock signal A and the clock signal B after fine adjustment can be judged to have the same phase and appear at the boundary between 0 and 1), the clock deviation (only approximate) of the clock signal A and the clock signal B is the average value of the difference of the delay of the coarse adjustment unit to the two paths of clock signals and the difference of the delay of the two difference delay units outputting the boundary between 0 and 1 to the two paths of clock signals.

The scale circuit includes two Ring oscillators (Ring oscillators): a delay cell Ring oscillator (Ring _ DC) and a delta delay cell Ring oscillator (Ring _ SDC). A delay cell Ring oscillator (Ring _ DC) for measuring the actual delay Dreal of the basic Delay Cell (DC), i.e. the true magnitude of the coarse tuning accuracy of the measuring circuit arrangement of the on-chip clock uncertainty; a difference delay unit Ring oscillator (Ring _ SDC) for measuring the actual unit delay difference dach of the difference delay unit (SDC), i.e. the true magnitude of the fine tuning accuracy of the measurement circuitry of the on-chip clock uncertainty.

Preferably, the circuit device 1(Skew and Jitter Measurement, SJM) for measuring the on-chip clock uncertainty includes, as shown in fig. 4, a coarse tuning unit 13 (i.e., a coarse tuning circuit), 9 groups of differential delay units 15 (i.e., fine tuning circuits) connected in parallel, 9 Phase Detectors (PDs) (i.e., detection units), and 9D-type flip-flops (DFFs) (i.e., sampling units) connected to the phase detectors;

two paths of clock signals (a clock signal A and a clock signal B) from two different measurement points of the same time source on a chip input a coarse-tuned clock signal into a Phase Detector (PD) and a D-type trigger (the coarse-tuned clock signal is used for controlling the phase detection process of the phase detector and the sampling of the trigger, belongs to the prior art, and is not described in detail herein); inputting the finely adjusted clock signal into a Phase Discriminator (PD) for phase discrimination, and sampling a phase discrimination result by a D-type trigger (DFF); when the output of the D type flip-flop (DFF) shows that the delayed clock signal A and the delayed clock signal B are in phase synchronization (namely, the output of the D type flip-flop is in a 0-1 boundary), the time deviation of the two clock signals (the clock signal A and the clock signal B) of the same time source is calculated according to the output of the D type flip-flop (DFF).

As shown in fig. 4, the coarse tuning unit 13 includes a first coarse tuning unit 131 and a second coarse tuning unit 132, and the clock signal a and the clock signal B are coarsely tuned by the first coarse tuning unit 131 and the second coarse tuning unit 132, respectively. The first coarse tuning unit 131 and the second coarse tuning unit 132 both use a 4-bit digital controlled delay line (DCDL-4), and the 4-bit digital controlled delay line uses a binary control structure, which has the advantage that it can control a delay with a smaller step size but a larger range with fewer control signals.

As shown in fig. 5, the 4-bit digital controlled delay line of the first coarse tuning unit 131 is composed of 4 groups of delay units connected in series in a binary manner.

The 4 groups of delay units are respectively a 16-stage delay unit (DC × 16), an 8-stage delay unit (DC × 8), a 4-stage delay unit (DC × 4) and a 2-stage delay unit (DC × 2); the 16-stage delay unit (DC × 16) comprises 16 basic delay units connected in series, and the other stages of delay units are similar in structure. Each group of delay units is connected with the transmission line in parallel and then is connected with an alternative controller (MUX2), digital control signals (CA16, CA8, CA4 and CA2) of 4 groups of delay units are respectively input into the corresponding alternative controller (MUX2), and the delay units of the corresponding group are controlled through the digital control signals. The digital control signal is provided by a scan chain. The use of scan chains to control digitally controlled delays is prior art and is not the focus of the present invention and is used here only as a tool and is not described in detail here.

During control: CA16 ═ 1, representing the delay accounted for in DCDL _4 by the delays generated by the 16 stage delay units; CA16 is 0, indicating that the delay generated by the 16-stage delay unit does not account for the delay of DCDL _ 4. Similarly, CA8 controls an 8-stage delay unit; CA4 controls a 4-stage delay unit; CA2 controls a stage 2 delay unit. Let the delay of the 1-stage elementary delay unit (DC) be D (in this embodiment, the unit of the delay of the 1-stage elementary delay unit is picosecond, where 1,000,000,000 picosecond is 1 second), the combination of these 4 groups of delay units can make DCDL _4 form any integer multiple delay between 0-15 of 2D.

As shown in fig. 4, the differential Delay unit (SDC) 15 is implemented by a parallel form. On one hand, the parallel structure is adopted, the differential delay unit is not required to be controlled, and the control position, the control difficulty and the measurement time are reduced; on the other hand, smaller delay can be realized, and the measurement accuracy is increased.

Preferably, the coarsely adjusted clock signal a is divided into an odd number path S ═ 2n +1 (a 1, a2, A3, and.. 9.; n ═ 1, 2, 3, and.. 1.), and the coarsely adjusted clock signal B is divided into an odd number path S ═ 2n +1 (B1, B2, B3, and.. 9.; n; 1, 2, 3). Then, the signals are input into an odd group (S2 n +1,

n

1, 2, 3.) in pairs (a 1 and B1, a2 and B2, A3 and B3) and fine-adjusted by the differential delay units connected in parallel; after the delay is finely adjusted by odd groups of (S-2 n +1, n-1, 2, 3.) parallel differential delay units, the delay difference formed by the 2n +1 parallel differential delay units to the two passing clock signals has the proportion of n: n-1: 0: n- (n-1): n. In the present embodiment, S is 2n +1 is 9, i.e., n is 4. Preferably, in order to realize the delay D (i.e., the delay of one gate) with the accuracy smaller than that of the 1-stage basic delay unit (DC), the present invention realizes the differential delay unit by increasing the load capacitance.

Preferably, as shown in fig. 4, S is 2n +1 9, i.e., n is 4. After the delay is finely adjusted by 9 groups of differential delay units which are connected in parallel, the ratio of delay difference formed by the 9 groups of differential delay units which are connected in parallel to two paths of clock signals is 4: 3: 2: 1: 0: 1: 2: 3: 4.

The delay ratios of the first fine tuning unit and the second fine tuning unit in the 2n +1 difference delay units to the two paths of signals are respectively 4: 0; 3: 0; 2: 0; 1: 0; 0: 0; 0: 1; 0: 2; 0: 3; 0: 4.

As shown in fig. 6, SDC _4, SDC _3, SDC _2, SDC _1, and SDC _ R are respectively added with 4, 3, 2, 1, and 0 stages of metal-oxide-semiconductor field effect transistor (MOS transistor) loads at the DC output terminals of the first two stages, since the shunt capacitance is linearly increasing, 9 combinations (SDC _4, SDC _ R), (SDC _3, SDC _ R), (SDC _2, SDC _ R), (SDC _1, SDC _ R), (SDC _ R, SDC _1), (SDC _ R, SDC _2), (SDC _ R, SDC _3) and (SDC _ R, SDC _4) in fig. 4, the finely adjusted 9 groups of differential delay units of clock signal a and clock signal B form delay differences of 4: 3: 2: 1: 0: 1: 2: 3: 4 for the two clock signals passing through. The unit delay difference d of the differential delay unit is determined by the size of the load capacitor, and a precise group of small delay units can be realized. That is, the delay differences formed by the two clock signals passing through the 9 groups of difference delay units shown in fig. 4 are respectively 4d, 3d, 2d, 1d, 0, -1d, -2d, -3d, -4d, and after the delay is finely adjusted by the 9 groups of difference delay units connected in parallel, the ratio of the delay differences formed by the 9 groups of difference delay units connected in parallel to the two clock signals passing through is 4: 3: 2: 1: 0: 1: 2: 3: 4.

More preferably, the present inventionThe size of the metal-oxide-semiconductor field effect transistor (MOS transistor) in the DC is the same as that of the metal-oxide-semiconductor field effect transistor (MOS transistor) in the DC, so that overlarge deviation caused by the process can be avoided. The determination of the number of parallel differential delay units can be determined by the simulated delay D of the basic delay unit (DC)_{Simulation (Emulation)}D of simulated unit delay difference of difference delay units connected in parallel_{Simulation (Emulation)}If the number of groups S (i.e., 2n +1) of the parallel differential delay units is obtained, the requirement of equation (1) needs to be satisfied:

this ensures that the circuit has no dead angle for measurement, and if this condition is not met, the boundary between 0 and 1 shown in table 1 (the algorithm comparison table for the output of the measurement circuit SJM) may not be observed, and the specific measurement value may not be read. However, S is not too large, otherwise resources are wasted, and in the embodiment of the present invention, the final number S of groups of the differential delay units connected in parallel is calculated and determined by using the following formula:

wherein,is rounded up meaning.

When calculating the number of groups, D is calculated according to parameters provided by the process_{Simulation (Emulation)}And d_{Simulation (Emulation)}The design method is obtained through simulation, is not an actual numerical value, and needs to increase certain design redundancy during actual design.

Because of increasing the capacitive load, the turnover time (transition) of the clock is inevitably changed, in order to reduce the influence, preferably, the invention adopts NP complementary load capacitance, wherein NP stands for N-type MOS tube and P-type MOS tube, N, P stands for the characteristic structure of MOS tube; therefore, the rising edge and falling edge transition time (transition) of the clock signal passing through can be ensured to be changed the same, and the final output clock signal transition time (transition) is basically the same as the input clock signal through the shaping of the following two stages of DC (the rising time or the falling time of the two clocks is basically the same, so that higher measurement precision can be ensured).

Inputting a coarse-tuned clock signal to a Phase Detector (PD) and a D-type flip-flop (the coarse-tuned clock signal is used to control the phase detection process of the PD and the sampling of the flip-flop, which belongs to the prior art and is not described in detail herein); inputting the finely adjusted clock signal into a Phase Discriminator (PD) for phase discrimination, and outputting a phase discrimination result to be 0 or 1 (the output of the phase discriminator can only be 0 or 1 is the prior art and is not the key point of the invention, the phase discriminator is only used as a tool and is not described in detail here) after the phase discrimination, and a D-type trigger (DFF) samples the phase discrimination result; when the output of the D type flip-flop (DFF) shows that the delayed clock signal A and the delayed clock signal B are in phase synchronization (namely, the output of the D type flip-flop is in a 0-1 boundary), the time deviation of the two clock signals (the clock signal A and the clock signal B) of the same time source is calculated according to the output of the D type flip-flop (DFF).

The mode of operation of the on-chip clock uncertainty measurement circuit arrangement is controlled by a mode of operation control signal (denoted OC in fig. 4). When OC is 1, the device is in a sampling and measuring working mode, and data continuously jumps and cannot be read;

when OC is 0, the output operation mode is in, and data can be read.

The basic procedure for the use of the on-chip clock uncertainty measuring circuit arrangement 1 is substantially as follows: two clock signals to be measured are selected by utilizing switches of two clock signal control circuits, then digital control signals of a coarse tuning unit are set by adjusting a scan chain, and then measurement results (output of 9D-type triggers) are observed:

the outputs of the 9D type flip-flops have 0 and 1 boundaries, and the time deviation of two clock signals (clock signal A and clock signal B) of the same time source is calculated according to the outputs of the D type flip-flops (DFF).

The outputs of the 9D type flip-flops do not have 0 and 1 junctions, and the digital control signals of the coarse tuning unit are required to be set by adjusting the scan chain so as to realize re-measurement. And repeatedly adjusting the digital control signals of the coarse tuning unit set by the scan chain according to the output of the observed 9D type flip-flops, and finally obtaining the output of the 9D type flip-flops comprising the junction of 0 and 1.

In this embodiment, the method of calculating the time offset between two clock signals of the same time source from the output of the D-type flip-flop (DFF) is as follows: after sampling, the corresponding D-type flip-flop (DFF) has 3 groups of 27 output signals (3 groups represent continuous 3 cycles), which respectively represent the measurement of three continuous cycles of the clock signal to be measured.

The three sets of signals are relatively independent, and the possible occurrence of each set of output signals and their measurements are shown in the following table.

Output result algorithm comparison table of measuring circuit SJM (Table 1)

Q4VX～Q4NVX	Skaw (CKA-CKB) (X is 1, 2 or 3, error is 0.5d)
		000000000	After delay, CKB is prior to CKA, skew is too large to read, and retesting is required
000000001	(NA-NB)×D-3.5×d
		000000011	(NA-NB)×D-2.5×d
000000111	(NA-NB)×D-1.5×d
		000001111	(NA-NB)×D-0.5×d

000011111	(NA-NB)×D+0.5×d
		000111111	(NA-NB)×D+1.5×d
001111111	(NA-NB)×D+2.5×d
		011111111	(NA-NB)×D+3.5×d
111111111	After delay, CKA precedes CKB, skew is too large to read, and retesting is required

If the phase discrimination result of the phase discriminator is 0 when the clock signal A is prior to the clock signal B after the delay, the output of the D-type flip-flop (DFF) is 0; then when the clock signal B precedes the clock signal a and the phase detection result of the phase detector is 1, the output of the type D flip-flop (DFF) is 1. At the 0 and 1 interface (i.e., the time between transitions between 0 and 1) of the output of the D-type flip-flop (DFF), the two clock signals are phase synchronized. Therefore, the temperature of the molten metal is controlled,

when the output (the output is the phase discrimination result of the phase discriminator) of the D-type flip-flop (DFF) has a 0-1 boundary, the clock deviation of the clock signal A and the clock signal B is the average value of the delay difference of the coarse tuning unit to the two paths of clock signals plus the delay difference of the two difference delay units outputting the 0-1 boundary to the two paths of clock signals.

As shown in the above table, the above,

when the output of Q4VX-Q4NVX is 000000001, i.e.

The output of Q4VX is 0, the output of Q3VX is 0, the output of Q2VX is 0, the output of Q1VX is 0,

the output of Q0VX is 0,

the output of Q1NVX is 0, the output of Q2NVX is 0, the output of Q3NVX is 0, and the output of Q4NVX is 1.

When the output of Q3NVX is 0, the difference between the delays of clock signal a and clock signal B on this path is: (NA-NB). times.D-3. times.d;

when the output of Q4NVX is 1, the difference between the delays of clock signal a and clock signal B on this path is: (NA-NB). times.D-4. times.d;

the time offset between the actual clock signal a and the clock signal B is:

(NA-NB)×D+(-3×d-4×d)/2＝(NA-NB)×D-3.5×d

that is, when the output of Q4VX-Q4NVX is 000000001, the time offset (NA-NB). times.D-3.5. times.d between clock signal A and clock signal B.

When the 0 and 1 boundaries do not occur in the outputs of Q4VX-Q4NVX, i.e., after a delay, clock signal A and clock signal B do not appear to be in phase. When the output of Q4VX-Q4NVX does not have a boundary between 0 and 1, the digital control signal of the coarse tuning unit needs to be set by adjusting the scan chain to realize the re-measurement. And repeatedly adjusting the digital control signals of the scanning chain setting coarse tuning unit according to the output of the observed 9D type flip-flops, and finally obtaining the output of the 9D type flip-flops comprising the interfaces of 0 and 1. The use of scan chains to control digitally controlled delay lines is prior art and is not the focus of the present invention and is used here only as a tool and is not described in detail here.

When the outputs of Q4VX-Q4NVX are otherwise, the time offset between clock signal A and clock signal B can be calculated, as well.

The reverse is true.

Wherein NA and NB are the number of DCs in A, B two DCDL _4, respectively, and are expressed as:

N_A＝CA16×16+CA8×8+CA4×4+CA2×2

N_B＝CB16×16+CB8×8+CB4×4+CB2×2

N_Ais the number of delays of the 4-bit digitally controlled delay line of the first coarse tuning unit 131 counted in DCDL _ 4; n is a radical of_BIs the number of delays of the 4-bit digitally controlled delay line of the second coarse tuning unit 132 counted in DCDL _ 4;

the digital control signals of the 4-bit digital control delay lines of the first coarse tuning unit 131 and the second coarse tuning unit 132 are provided by a scan chain, and the values of the digital control signals (CA16, CA8, CA4, CA2 and CB16, CB8, CB4, CB2) are obtained from the scan chain, thereby calculating N_AAnd N_BThe value of (c).

D is the delay of the basic delay unit (DC), D is the unit delay difference of the difference delay unit (in this embodiment, the unit of the unit delay difference of the difference delay unit is femtosecond, where 0.001 picosecond is 1 femtosecond), which respectively represent the accuracy of the coarse adjustment and the accuracy of the fine adjustment of the SJM circuit. The time offset between clock signal a and clock signal B can be derived by substituting the actual delay dtotai of the basic Delay Cell (DC) and the actual unit delay difference dtotai of the difference delay cell (SDC), as measured by the scale circuit (the specific measurement method is described in detail below), into the above formula.

The phase discriminator respectively carries out phase comparison on three continuous periods of two paths of clock signals, three groups of output signals of 2n + 1D type trigger (DFF) outputs (the output is the phase discrimination result of the phase discriminator), the maximum jumping digit number is set as M (the maximum digit number of the change of the junction of the

output

0 and 1 of the D type trigger (DFF)) according to the digit number of the adjacent positions of 0 and 1 of the three groups of output signals, and the clock jitter t of the two clock signals to be measured is calculated_jitterComprises the following steps: t is t_jitter＝M×d，

Wherein d is a unit delay difference of the parallel differential delay units.

Wherein M is obtained by observing the output results of the D-type flip-flops with different periods. In this example, M is the number of output result jitter bits for three consecutive cycles. The time jitter (jitter) between the clock signal a and the clock signal B can be obtained by substituting the actual unit delay difference dtotai (the specific measurement method is described in detail below) of the differential delay unit (SDC) measured by the scale circuit into the above formula.

The actual delay D of the basic delay unit (DC) is realized when the circuit works under different voltage and temperature conditions_{Fruit of Chinese wolfberry}Actual unit delay difference d of sum difference delay unit (SDC)_{Fruit of Chinese wolfberry}Are different and therefore require the measurement of the actual D_{Fruit of Chinese wolfberry}And d_{Fruit of Chinese wolfberry}。

Considering that the whole period of the on-chip measurement clock may cause larger result error due to noise, the invention adopts two Ring oscillators Ring-DC and Ring-SDC to respectively measure the true size of the coarse adjustment precision and the fine adjustment precision of the measurement circuit device (SJM) of the on-chip clock uncertainty, namely the actual delay D of the basic delay unit (DC)_{Fruit of Chinese wolfberry}Actual unit delay difference d of sum difference delay unit (SDC)_{Fruit of Chinese wolfberry}. The circuit configuration of the ring oscillator is shown in fig. 7.

Here, Ring is needed to multiplex the pins of the microprocessor chip, and the oscillation waveform is output externally, and then the period is measured by using an external oscilloscope. In this form, the output signal is routed through a Printed Circuit Board (PCB), so the output signal frequency cannot be too large (accuracy within 100MHz is high), therefore Ring in the present invention adopts a 161-stage series connection form, and performs 16 frequency division on the output waveform, and finally outputs the signal.

In order to minimize device variation, basic Delay Cells (DC) and difference delay cells (SDC) are preferably modeled, and no de-noise protection is used in the two Ring oscillators Ring-DC and Ring-SDC, but rather a power-to-ground capacitor (DECAP) is added to attenuate the effects of power supply noise.

If the measured period of the Ring oscillator Ring _ DC of the delay unit is T_DCThe period of the Ring oscillator Ring _ SDC of the delta delay unit is T_SDCIf the two ring oscillators have the number of stages N and are divided by P (in the embodiment of the present invention, division by 16), the actual delay can be obtained as follows:

preferably, in the embodiment of the present invention, N is 161 and P is 16.

Preferably, the on-chip clock on-chip measurement system further includes a first multiplexer 111 and a second multiplexer 112, a first coarse tuning unit input buffer 121 and a second coarse tuning unit input buffer 122, a first fine tuning input buffer 141 and a second fine tuning input buffer 142.

After the circuit is activated, two clock signals (respectively represented by a clock signal A and a clock signal B) of the same time source are input into each group of clock signals to be measured, and three signals are respectively input by CK1A, CK2A, CK3A, CK1B, CK2B and CK 3B; then, the signals are shaped by respectively passing through a first coarse tuning unit input buffer 121 and a second coarse tuning unit input buffer 122; the shaped signals sequentially pass through a first coarse tuning unit 131 and a second coarse tuning unit 132 to perform coarse tuning on the phases of the two groups of clock signals;

the first fine input buffer 141 and the second fine input buffer 142 shape the coarsely adjusted clock signal again; the clock signal shaped again is fine-tuned by passing through a plurality of groups of differential delay units 15 connected in parallel.

Preferably, the alternative controller (MUX2) employs a NAND gate (NAND) based alternative controller (MUX2), as shown in fig. 8. The benefit of using this structure is that the transition time of the clock signal is consistent with that in DC during its internal transmission. MUX2 is critical in DCDL because all DCs are consistent and if the structure of MUX2 is not appropriate, it is likely that the consistency of the clock's flip time (transition) on propagation will be violated.

Preferably, the NAND gates (NAND) are of complementary symmetric structure, as shown in fig. 9. The physical properties of the two input ports in this structure are strictly symmetrical, which ensures that the transition time of the clock signal is not changed due to the sequence of the clock ports. NAND gates (NAND) do not use the commonly used CMOS architecture, considering that both input ports of NAND gates are likely to be clock paths.

Selection of elementary Delay Cells (DC):

since the binary adjustment mode is adopted for DCDL _4 and DCDL _3, and the number of control signals is small, in the embodiment of the present invention, it is preferable to use an Inverter (INV) as the basic delay unit.

As another alternative, preferably, when there are more control signals, a NAND gate (NAND) can be used as the basic delay unit, but more metal-oxide-semiconductor field effect transistors (MOS) are used in the NAND gate (NAND), which introduces more noise.

Preferably, the basic Delay Cell (DC) employs an Inverter (INV) structure with a metal-Oxide-Semiconductor (N-mos) fet load, as shown in fig. 10. Namely, adding an NMOS which is turned on with the same size under the NMOS of the Inverter (INV). This structure has two advantages: firstly, the transmission characteristic of a NAND gate (NAND) is simulated, and the consistency of the whole DCDL is ensured; the second is that the structure is substantially symmetrical with respect to the transfer characteristics of the rising and falling edges of the clock signal. The load capacitance in fig. 10 acts two: firstly, the capacitive load of the whole DCDL is balanced; the second is to increase the delay of the single DC appropriately to reduce the length of the DCDL. Particularly, in the present invention, the DCDL adopts a binary adjustment mode, and each length increase is doubled.

DC is also a key for determining the DCDL length as a basic constituent unit of DCDL. In determining the DCDL length, the delay produced by the circuit under extremely Fast conditions (Fast mode (Fast Corner)1.2V-40 c for the present embodiment) needs to be taken into account to ensure that the resulting DCDL length is sufficient to cover the predetermined measurement range under all conditions.

Selection of Phase Detector (PD):

the invention adopts the phase discriminator to judge whether the delayed clock signals are synchronous or not, so the accuracy of the phase discriminator can seriously influence the measurement result, and the invention is also a most complex module.

Preferably, the phase detector of the present invention uses a master-slave flip-flop with a four-stage SR Latch (SR _ Latch) connected in series as the phase detector, and as shown in fig. 11, both the phase detector and the flip-flop need to be controlled by a clock. Four clock signals are generated by using the coarsely adjusted clock signals, namely C1, C2, C3 and C4, wherein C1, C2 and C3 are used for the phase detector, and C4 is used for the flip-flop, and the clock C4 is homologous with the previous clock signals C1, C2 and C3 mainly because sampling of the flip-flop and the previous phase detector guarantee a certain time relationship to ensure that the output is correct. .

The structure that level four SR Latch is established ties prolongs SR Latch in space in order to exchange phase discrimination time, avoids the metastable state that probably appears (single SR _ Latch structure, when two input signal along too close the time, SR Latch probably gets into the metastable state), guarantees the exactness of phase discrimination. This also requires that the gate-level devices on the critical path have balanced transmission characteristics for the rising and falling edges of the clock signal, so that all NAND gates (NAND) in the circuit also adopt the complementary symmetrical structure in MUX2, and the Inverter (INV) of the balanced logic adopts the previous NMOS-loaded Inverter (INV) structure.

The sampling signal of the phase detector is a high-level effective signal, so the positions of the rising edge and the falling edge of the signal become more important. In order to ensure the phase detection time of three half cycles, the high levels of the sampling signals C1, C2 and C3 are required to be contained in the high level of the clock input signal, and keep a certain distance without overlapping, so that the clock signal to be detected can be prevented from directly passing through the SR Latch, and logic errors are avoided. However, since the signal can only be delayed and cannot be advanced, the fastest falling edge of the sampling signal C1 has to pass through a stage of NAND gate (NAND) and a stage of NOR, and the delay of the stage of SR Latch is smaller than that of the stage of NAND gate (NAND), which requires the falling edge of the sampled signal to come later, and there are two general solutions: one is to add a buffer before the first stage SR Latch, and the other is to add a buffer after the SR Latch. The invention leads the signal from the input end of SDC as the sampling signal of PD, and uses SDC as the front buffer (buffer), thus able to reduce the circuit scale.

Preferably, the load capacitor uses a MOS transistor capacitor in consideration of the problems of applicability and portability.

Preferably, the sizes of the transistors on the clock critical path are all the same, the width-to-length ratio of the transistors is moderate, the channel directions are the same, and no metal wiring is arranged above the active region;

preferably, a one-dimensional symmetrical grid is adopted in any gate circuit in the embodiment of the invention, and a virtual grid (Dummy) is added at the edge of a transistor to ensure strict symmetry;

preferably, in the MUX2 and the SR latch-based phase detector (SRPD), the metal layer where the wires are located, the length, width, direction of the metal trace, and the via hole through which the wires pass are as symmetrical and balanced as possible.

The circuit device and the system for measuring the on-chip clock uncertainty have the characteristics of less control data, large measurement range, high measurement precision and the like, and can reduce the area of an actual circuit to a certain extent.

For example, if the prior art SKITTER circuit is tested to have a measurement accuracy of 8ps per stage and 128 stages, 256 signals are finally required, and the measurement range is ± 1024 ps. By adopting the invention, if the first-stage delay of the binary control delay line is 35ps, and the total delay is 5, the measurement range is 1085 ps; the variation gradient of the following parallel differential delay line is 4ps, the measurement precision is 4ps, and the required signal quantity is

The total number of the final required signals is 21+5 × 2-31. This is evident from a comparison with the prior art:

the SKITTER uses 256 signals to realize the measuring range of 1024ps and the measuring precision of 8 ps.

The invention realizes the measurement range 1085ps and the measurement precision 4ps by using 31 signals.

The on-chip clock uncertainty measuring circuit device and the on-chip clock uncertainty measuring system have the characteristics of less control data, large measuring range, high measuring precision and the like, and can reduce the area of an actual circuit to a certain extent.

Finally, it should be noted that it is obvious that various changes and modifications can be made to the present invention by those skilled in the art without departing from the spirit and scope of the present invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A circuit arrangement for measuring on-chip clock uncertainty, characterized by:

2. The on-chip clock uncertainty measurement circuit arrangement of claim 1, wherein:

the coarse tuning circuit is a coarse tuning unit, and the fine tuning circuit is 2n +1 differential delay units connected in parallel, wherein n is a natural number;

after the coarse tuning unit coarsely tunes and delays the clock signal A and the clock signal B, respectively dividing the coarsely tuned clock signal A and the coarsely tuned clock signal B into 2n +1 paths of parallel signals; then, inputting the 2n +1 paths of parallel signals into 2n +1 parallel differential delay units in pairs for fine adjustment; the delay difference formed by the 2n +1 parallel differential delay units to the two paths of clock signals passing through has the ratio of n: n-1: 0: - (n-1) to-n.

3. The on-chip clock uncertainty measurement circuit arrangement of claim 2, wherein:

the difference delay unit comprises a first fine tuning unit and a second fine tuning unit; the clock signal A and the clock signal B after the coarse adjustment are respectively finely adjusted by a first fine adjustment unit and a second fine adjustment unit;

the delay ratios of the first fine tuning unit and the second fine tuning unit in the 2n +1 difference delay units to the two paths of signals are n: 0 respectively; (n-1) to 0; ...; 0: 0; .., 0: n-1; 0: n.

4. The on-chip clock uncertainty measurement circuit arrangement of claim 2 or 3, wherein:

the detection unit is 2n +1 phase detectors, and the 2n +1 phase detectors are respectively connected with the 2n +1 difference delay units;

the phase discriminator compares the phases of the clock signal A and the clock signal B after fine adjustment, and outputs 0 or 1.

5. The on-chip clock uncertainty measurement circuit arrangement of claim 4, wherein:

when the output of the phase discriminator has a boundary between 0 and 1, the clock deviation of the clock signal A and the clock signal B is the average value of the difference between the delay of the coarse tuning unit to the two paths of clock signals and the delay of the two difference delay units outputting the boundary between 0 and 1 to the two paths of clock signals.

6. The on-chip clock uncertainty measurement circuit arrangement of claim 2, wherein:

the coarse adjustment unit comprises a first coarse adjustment unit and a second coarse adjustment unit; the clock signal A and the clock signal B are coarsely regulated by a first coarse regulating unit and a second coarse regulating unit respectively;

the first coarse tuning unit and the second coarse tuning unit are 4-bit digital control delay lines, and the 4-bit digital control delay lines are binary control structures.

7. The on-chip clock uncertainty measurement circuit arrangement of claim 6, wherein:

the 4-bit digital control delay line comprises a basic delay unit, and the simulation delay D of the basic delay unit_{Simulation (Emulation)}；

D of simulated unit delay difference of the parallel differential delay units_{Simulation (Emulation)}The number of the groups of the differential delay units connected in parallel is 2n +1, and the requirement of the following formula is met:

8. the on-chip clock uncertainty measurement circuit arrangement of claim 6, wherein:

wherein,

is rounded up meaning.

9. The on-chip clock uncertainty measurement circuit arrangement of claim 4, wherein:

the phase detectors respectively carry out phase comparison on three continuous periods of two paths of clock signals, 2n +1 phase detectors output three groups of output signals, and the maximum bit number of adjacent position change of 0 and 1 is set as M according to the bit number of adjacent position change of 0 and 1 of the three groups of output signals; calculating to obtain the clock jitter t of two clock signals to be measured_jitterComprises the following steps: t is t_jitter＝M×d；

Wherein d is a unit delay difference of the parallel differential delay units.

10. The on-chip clock uncertainty measurement circuit arrangement of claim 7 or 8, wherein:

the elementary delay cells are inverters with mosfet loads.

11. The on-chip clock uncertainty measurement circuit arrangement of claim 2, wherein:

the parallel differential delay unit is realized by increasing load capacitance.

12. The on-chip clock uncertainty measurement circuit arrangement of claim 4, wherein:

the phase detector is a master-slave flip-flop with four stages of SR latches connected in series.

13. A system for measuring on-chip clock uncertainty, comprising:

the device comprises a measuring circuit device of on-chip clock uncertainty and a scale circuit;

the on-chip clock uncertainty measuring circuit device comprises a delay circuit and a detection unit; the delay circuit comprises a coarse tuning circuit and a fine tuning circuit; two paths of clock signals A and B to be measured from two different measuring points of the same time source on the chip; the delay circuit delays a clock signal a and a clock signal B:

after the coarse tuning unit coarsely tunes and delays the clock signal A and the clock signal B, respectively dividing the coarsely tuned clock signal A and the coarsely tuned clock signal B into 2n +1 paths of parallel signals; then, inputting the 2n +1 paths of parallel signals into 2n +1 parallel differential delay units in pairs for fine adjustment; the delay difference formed by the 2n +1 parallel differential delay units to the two paths of clock signals passing through has the ratio of n: n-1: 0: - (n-1) to-n; the detection unit detects the phases of the clock signal A and the clock signal B after fine adjustment;

14. The system for measuring on-chip clock uncertainty of claim 13, wherein:

the detection unit is 2n +1 phase detectors, and the 2n +1 phase detectors are respectively connected with the 2n +1 difference delay units; the phase discriminator compares the phases of the clock signal A and the clock signal B after fine adjustment, and outputs 0 or 1;

15. The system for measuring on-chip clock uncertainty of claim 13, wherein:

the coarse tuning unit comprises a basic delay unit, and the actual delay of the basic delay unit is D_{Fruit of Chinese wolfberry}The actual unit delay difference of the differential delay unit is d_{Fruit of Chinese wolfberry}；

N is the number of stages of the ring oscillator, T_DCPeriod of delay cell ring oscillator, T_SDCThe period of the ring oscillator of the difference delay unit is P, and the number of frequency division is P.