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CN102054533A - 隔离顺序、随机和系统数据以减少垃圾回收的针对基于页映射的非易失性半导体存储器 - Google Patents

隔离顺序、随机和系统数据以减少垃圾回收的针对基于页映射的非易失性半导体存储器 Download PDF

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CN102054533A
CN102054533A CN201010526407XA CN201010526407A CN102054533A CN 102054533 A CN102054533 A CN 102054533A CN 201010526407X A CN201010526407X A CN 201010526407XA CN 201010526407 A CN201010526407 A CN 201010526407A CN 102054533 A CN102054533 A CN 102054533A
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M-M·苏
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Abstract

一种隔离顺序、随机和系统数据以减少垃圾回收的针对基于页映射的非易失性半导体存储器。本发明公开了一种非易失性半导体存储器，其包括具有存储器阵列的存储器器件，该存储器阵列包括多个存储段。从主机接收多个顺序存取写命令和随机存取写命令，其中每个写命令标识至少一个逻辑块地址。顺序存取写命令的逻辑块地址映射到多个存储段以生成顺序映射数据，且顺序映射数据映射到多个区的第一区。随机存取写命令的逻辑块地址被映射到多个存储段以生成随机映射数据，并且随机映射数据映射到多个区的第二区。

Description

隔离顺序、随机和系统数据以减少垃圾回收的针对基于页映射的非易失性半导体存储器 
背景技术
非易失性半导体存储器可用于计算机系统(如，台式、膝上型、便携式计算机等等)或消费装置(如音乐播放器、移动电话、照相机等等)或其他合适用具的大容量存储装置。非易失性半导体存储器可包括一个或更多存储器器件(如闪存)和存取每个存储器器件的控制电路。每个存储器器件都耦接到I/O(输入/输出)总线以及大量接口控制线。当向存储器器件发出编程命令或擦除命令时，控制电路通过I/O总线传递地址和命令数据(并为编程操作传递写数据)。当发出读取命令时，控制电路通过I/O总线传递地址和命令数据然后通过I/O总线接收读取的数据。 
每个存储器器件通常包括多个块，这些块每次被存取一页。例如，单个块可包括128页，其中每页包括4k字节。由于页在尚未首次擦除的情况下通常不能被重写，因此通常选择不同块中新的一页来执行“重写”操作。为了促进重新部署数据到不同页，非易失性半导体存储器实施间接存取，其中表示数据块的逻辑块地址(LBA)映射到表示多页中一页的物理块地址(PBA)。通过这种方式，当数据块的页移动时，LBA易于再分配给新PBA。 
非易失性存储器周期性地执行垃圾回收操作，其中第一块的剩余有效页被重新部署到第二块，从而第一块可被擦除(由此在重写操作期间擦除先前重新部署的无效页)。期望最小化非易失性存储器中垃圾回收的量，以减小写放大和功率消耗，以及提高持久性和性能。 
附图说明
图1是根据本发明实施例的非易失性半导体存储器，其包括具有存储器阵列的存储器器件，该存储器阵列包括多个存储段。 
图2示出本发明的实施例，其中系统数据、随机数据和顺序数据 的映射数据存储在各映射区中。 
图3A-3D示出本发明实施例，其中基于页的映射方案用于寻址存储段(该实施例中的页)。 
图4A-4C示出本发明实施例，其中大量写命令的映射数据在被写入到非易失性存储器之间缓存在易失性存储器中。 
图5A示出根据本发明实施例在易失性存储器中存取的全局LBA/PBA映射。 
图5B示出用于存储顺序存取写命令的映射数据的顺序日志，其中顺序日志用于在电源故障时更新全局LBA/PBA映射。 
图5C示出用于存储随机/系统存取写命令的映射数据的随机/系统日志，其中随机/系统日志用于在电源故障时更新全局LBA/PBA映射。 
图6是根据本发明实施例的流程图，其中满页映射数据在被写入到非易失性存储器之前存储在每个写日志中，且全局LBA/PBA映射被周期性写入到非易失性存储器中。 
具体实施方式
图1示出非易失性半导体存储器2，其包括存储器器件4和定义多个区的控制电路8，存储器器件4具有包括多个存储段的存储器阵列6，每个区包括多个存储段。从主机10接收多个顺序存取写命令，以将顺序数据写入到存储器器件4，其中每个顺序存取写命令标识至少一个逻辑块地址(LBA)。从主机10接收多个随机存取写命令，以将随机数据写入到存储器器件4，其中每个随机存取写命令标识至少一个LBA。顺序存取写命令的LBA映射到多个存储段，以生成顺序映射数据，且顺序映射数据映射到多个区的第一区。随机存取写命令的LBA映射到多个存储段从而生成随机映射数据，且随机映射数据映射到多个区的第二区。 
非易失性半导体存储器2可包括控制电路8和存储器器件4的任何适当配置。在图1的实施例中，存储器器件4包括合适的闪存(如NAND或NOR(闪存)，且控制电路包括闪存控制器8，闪存控制器8包括执行不同算法(如LBA到PBA的映射、纠错编码(ECC)、耗损平衡，等等)的微处理器12。存储器控制器8进一步包括用于在易 失性存储器(如动态随机存储器(DRAM))中缓存写/读数据的缓存器14和用于与存储器器件4接口的合适的接口电路16。存储器器件4耦连到I/O总线18以及多个接口控制线20。当发出编程命令或擦除命令给存储器器件4时，微处理器12通过I/O总线18传递地址和命令数据(并且为编程操作传递写入数据)。当发出读取命令时，微处理器12通过I/O总线18传递地址和命令数据，然后通过I/O总线18接收读取的数据。在一个实施例中，微处理器12从存储器器件4接收状态信息22从而判断其何时完成写入/读取操作。 
图1的实施例中的存储器器件4包括用于从接口电路16接收控制信号和命令数据的控制器24。例如，命令数据可包括地址信息，用于将数据写入到存储器阵列6的特定存储段。写入数据缓存在数据寄存器26中，且当控制器24接收刷新(flush)命令时，控制器24将缓存在数据寄存器26中的数据传递到存储器阵列6的目标存储段(页)中。 
在一个实施例中，存储器控制器8通过仿真主机系统可以使用标准磁盘驱动器通信协议(如ATA协议)对其进行存取的磁盘驱动器来实现固态驱动器(SSD)。此实施例中的主机10可包括独立的微处理器(如在台式或膝上型计算机中)，该处理器通过合适的接口(如串行或并行ATA)与SSD通信。在可替换实施例中，可以在消费装置中实现(如照相机或移动电话)非易失性半导体存储器2，其中主机10可实现为由用于实现存储器控制器8的相同微处理器12执行的固件组件。 
在一个实施例中，存储器器件4中的存储器阵列6包括多个块，其中每个块包括多个页。在一个实施例中，页必须在写入之前被擦除。因此页是通过将新数据写入不同页(通常在不同块中)、将LBA重映射到新PBA以及使旧页无效的方式而被“重写”。周期性地，块的无效页在垃圾回收过程中通过将块的有效页复制到新块，且然后擦除整个块而被恢复。 
存储器控制器8通过为每个区分配多个块来定义多个区，其中每个区存储与顺序存取写命令、随机存取写命令或系统存取写命令相关联的写入数据或映射数据，如图2所示。在一个实施例中，块可以根据需要动态地分配给每个区。将写入数据和映射数据隔离到各个区内 有助于通过减少存储有效和无效页的块数来减少每个区内的垃圾回收量。也就是，如果写入数据和映射数据被隔离，则将增加区内整个块被重写的可能性，以便无需重新定位有效页即可擦除块。 
该概念可参考图3A-3D来理解，图3A-3D示出根据本发明的实施例的基于页的映射方案。使用基于页的映射，每个LBA可映射到任何块内任何页的PBA。当将具有映射到第一块的第一页的第一LBA的数据写入到第二块的第二页时，第一块的有效页没有象基于块的映射那样重新分配到第二块。这在图3A和3B中进行了图示说明，其中在写操作过程中，写入数据被写入到第二块的页面中，并且第一块中的相应页被无效。该过程在随后写操作期间针对不同页重复，如图3B和3C所示，直到第一块的所有页已经被无效，如图3D所示。然后，第一块被擦除，由此其可被重新分配，而无需重新部署任何有效页(因为没有有效页)。 
在每个写操作期间，LBA到PBA的映射被更新从而反映页的重新部署或反映新LBA的新页的分配。此外，映射数据被周期性地写入到存储器器件4中，从而在发生电源故障的情况下保存映射。在图4A-4C所示的实施例中，大量写命令的映射数据在写入存储器器件4之前高速缓存在易失性存储器中。例如，在一个实施例中，直到已经执行足够的写命令以使用映射数据填满整个页时，才将映射数据写入到存储器器件4。一旦已经高速缓存一页的映射数据，映射数据即被写入存储器阵列的一页中。与一次写入映射数据的部分页相比，这减少了对存储器阵列(以及存储器阵列的关联碎片)执行的写操作的数量。 
图5A示出本发明的实施例，其中全局LBA到PBA映射存储在存储器器件4中，并在上电时被读入存储器控制器8的易失性存储器中。当存储器控制器8执行写命令时，易失性存储器中的全局映射被更新以反映LBA到PBA映射的变化。映射数据也存储在与写操作类型(顺序、随机或系统)对应的写日志中。之后，写日志周期性地存储到存储器器件4中，从而在电源故障的情况下保存映射数据。写日志比全局映射小的多，且因此与将整个全局映射保存到存储器器件4相比，将写日志保存到存储器器件4中需要较少的时间并导致更少的写放大。如果发生电源故障，则从存储器器件4读取写日志并且写日志用于更 新全局映射。全局映射也周期性地被保存到存储器器件4中，但频率比写日志低。 
图5B示出存储与顺序存取写命令关联的映射数据的示例写日志的部分。使用顺序存储，LBA和对应的PBA是连续的，且因此只有起始LBA与连续PBA(区和区内页号)一起存储(在图5B的例子中LBA0)。在替换实施例中，起始PBA与运行长度的PBA一起存储，这要求更少的存储器空间。图5C示出存储与随机存取写命令或系统存取写命令关联的映射数据的示例写日志的部分。由于LBA到PBA的映射是随机的，因此写日志针对每个相应页存储LBA和PBA(区和区内页号)。图5B和5C还示出，在一个实施例中，每个写日志存储足够的映射数据以填充一页，其中一旦为填充写日志而执行了足够的写操作，就将写日志保存到存储器器件4。 
图6是根据本发明实施例的流程图，其中当非易失性半导体存储器上电时，全局映射从存储器器件中读取到易失性存储器中(步骤28)。映射日志从存储器器件读取并且在需要时用于更新全局映射(步骤30)。当接收到写命令时(步骤32)，根据写命令的类型将写入数据写到目标区。如果写命令是顺序存取写命令，则用户数据被写到存储器器件的顺序数据区(步骤34)，并且顺序映射数据被生成并存储在顺序写日志中(步骤36)。如果顺序写日志已满(步骤38)，则顺序写日志被写入存储器器件的顺序映射区，并且顺序写日志被清除以处理后续顺序存取写命令(步骤40)。如果写命令是随机存取写命令，则用户数据被写入存储器器件的随机数据区(步骤42)，并且随机映射数据被生成并存储在随机写日志中(步骤44)。如果随机写日志已满(步骤46)，则随机写日志被写入存储器器件的随机映射区，并且随机写日志被清除以处理后续随机存取写命令(步骤48)。如果写命令是系统存取写命令，则系统数据被写入存储器器件的系统数据区(步骤50)，并且系统映射数据被生成并存储在系统写日志(步骤52)中。如果系统写日志已满(步骤54)，则系统写日志被写入存储器器件的系统映射区，并且系统写日志被清除以处理后续系统存取写命令(步骤56)。在预定间隔后(步骤58)，全局映射被写入存储器器件(步骤60)，并且当前存储在存储器器件中的写日志被无效(步骤62)， 因为在发生电源故障的情况下，不再需要当前存储在存储器器件中的写日志更新全局映射(直到更多写命令被处理)。 
在系统存取写命令期间被写入到存储器器件的系统数据可包括任何合适的系统数据。例如，当写日志被写入存储器器件时(在图6的步骤40、48和56)，写命令是系统存取写命令。写日志被写入到系统数据区并且相应的映射数据存储在系统写日志中。可能在正常操作过程中生成其他合适的系统数据，如与垃圾回收或耗损平衡算法关联的系统数据。 
存储器控制器8可以任何合适方式将写命令标识为顺序的或随机的。在一个实施例中，从主机接收的写命令可包括指定写命令类型的标识符。在另一个实施例中，新的写命令最初作为随机存取写命令处理，直到顺序写命令的连续数目超过预定阈值。之后，后续写命令作为顺序存取写命令处理，直到连续序列中有中断。 

Claims (18)

1.一种非易失性半导体存储器，其包括：
包括存储器阵列的存储器器件，该存储器阵列包括多个存储段；以及
控制电路，其可操作用于：
定义多个区，每个区包括多个所述存储段；
从主机接收多个顺序存取写命令以将顺序数据写入到所述存储器器件，其中每个顺序存取写命令标识至少一个逻辑块地址即LBA；
从所述主机接收多个随机存取写命令以将随机数据写入到所述存储器器件中，其中每个随机存取写命令标识至少一个LBA；
映射所述顺序存取写命令的LBA到多个所述存储段以生成顺序映射数据；
映射所述顺序映射数据到所述区的第一区；
映射所述随机存取写命令的LBA到多个所述存储段以生成随机映射数据；以及
映射所述随机映射数据到所述区的第二区。
2.根据权利要求1所述的非易失性半导体存储器，其中所述控制电路进一步可操作用于：
生成多个系统存取写命令以将系统数据写入存储器器件，其中每个系统存取写命令标识至少一个LBA；
映射所述系统存取写命令的LBA到多个所述存储段以生成系统映射数据；以及
映射所述系统映射数据到所述区的第三区。
3.根据权利要求2所述的非易失性半导体存储器，其中：
所述存储段包括多个块，每个块包括多个页；
所述控制电路进一步可操作为通过擦除整个块来擦除页；
所述第一区包括第一块；
所述第二区包括第二块；并且
所述第三区包括第三块。
4.根据权利要求3所述的非易失性半导体存储器，其中所述控制电路进一步可操作用于：
在执行多个所述顺序存取写命令后，写入所述顺序映射数据到所述第一区；
在执行多个所述随机存取写命令后，写入所述随机映射数据到所述第二区；
在执行多个所述系统存取写命令后，写入所述系统映射数据到所述第三区。
5.根据权利要求4所述的非易失性半导体存储器，其中所述控制电路进一步可操作为擦除所述第一、第二和第三区之一中的第一块，而不将所述第一块的有效页重新部署到第二块。
6.一种非易失性半导体存储器，其包括：
包括存储器阵列的存储器器件，所述存储器阵列包括多个块，每个块包括多个页；以及
控制电路，其可操作用于：
定义多个区，每个区包括多个所述存储段；
从主机接收多个顺序存取写命令以将顺序数据写到所述存储器
器件，其中每个顺序存取写命令标识至少一个逻辑块地址即LBA；
从所述主机接收多个随机存取写命令以将随机数据写到所述存
储器器件，其中每个随机存取写命令标识至少一个LBA；
映射所述顺序存取写命令的LBA到所述区的第一区；
映射所述随机存取写命令的LBA到所述区的第二区；以及
通过如下操作执行写命令：
写入具有映射到第一块的第一页的第一LBA的数据到第二块的第二页，而不将所述第一块的有效页重新部署到所述第二块；以及
映射所述第一LBA到所述第二块的所述第二页。
7.根据权利要求6所述的非易失性半导体存储器，其中所述控制电路进一步可操作用于：
生成多个系统存取写命令以将系统数据写入所述存储器器件，其中每个系统存取写命令标识至少一个LBA；以及
映射所述系统存取写命令的LBA到所述区的第三区。
8.根据权利要求7所述的非易失性半导体存储器，其中：
所述控制电路进一步可操作为通过擦除整个块来擦除一页；
所述第一区包括第一块；
所述第二区包括第二块；并且
所述第三区包括第三块。
9.根据权利要求8所述的非易失性半导体存储器，其中所述控制电路进一步可操作为擦除所述第一、第二和第三区之一中的第一块，而不将所述第一块的有效页重新部署到第二块。
10.一种操作包括存储器器件的非易失性半导体存储器的方法，所述存储器器件包括存储器阵列，所述存储器阵列包括多个存储段，所述方法包括：
定义多个区，每个区包括多个所述存储段；
从主机接收多个顺序存取写命令以将顺序数据写入所述存储器器件，其中每个顺序存取写命令标识至少一个逻辑块地址即LBA；
从所述主机接收多个随机存取写命令以将随机数据写入所述存储器器件，其中每个随机存取写命令标识至少一个LBA；
映射所述顺序存取写命令的LBA到多个所述存储段以生成顺序映射数据；
映射所述顺序映射数据到所述区的第一区；
映射所述随机存取写命令的LBA到多个所述存储段以生成随机映射数据；以及
映射所述随机映射数据到所述区的第二区。
11.根据权利要求10所述的方法，进一步包括：
生成多个系统存取写命令以将系统数据写入所述存储器器件，其中每个系统存取写命令标识至少一个LBA；
映射所述系统存取写命令的LBA到多个所述存储段以生成系统映射数据；以及
映射所述系统映射数据到所述区的第三区。
12.根据权利要求11所述的方法，其中：
所述存储器段包括多个块，每个块包括多个页；
页是通过擦除整个块而被擦除的；
所述第一区包括第一块；
所述第二区包括第二块；并且
所述第三区包括第三块。
13.根据权利要求12所述的方法，进一步包括：
在执行多个所述顺序存取写命令后，写入所述顺序映射数据到所述第一区；
在执行多个所述随机存取写命令后，写入所述随机映射数据到所述第二区；以及
在执行多个所述系统存取写命令后，写入所述系统映射数据到所述第三区。
14.根据权利要求13所述的方法，进一步包括擦除所述第一、第二和第三区之一的第一块，而不将所述第一块的有效页重新部署到第二块。
15.一种操作包括存储器器件的非易失性半导体存储器的方法，所述存储器器件包括存储器阵列，所述存储器阵列包括多个块，每个块包括多个页，所述方法包括：
定义多个区，每个区包括多个存储段；
从主机接收多个顺序存取写命令以将顺序数据写入所述存储器器件，其中每个顺序存取写命令标识至少一个逻辑块地址即LBA；
从所述主机接收多个随机存取写命令以将随机数据写入所述存储器器件，其中每个随机存取写命令标识至少一个LBA；
映射所述顺序存取写命令的LBA到所述区的第一区；
映射所述随机存取写命令的LBA到所述区的第二区；以及
通过如下操作执行写命令：
写入具有被映射到第一块的第一页的第一LBA的数据到第二块的第二页，而不将所述第一块的有效页重新部署到所述第二块；以及
映射所述第一LBA到所述第二块的所述第二页。
16.根据权利要求15所述的方法，进一步包括：
生成多个系统存取写命令以将系统数据写入所述存储器器件，其中每个系统存取写命令标识至少一个LBA；以及
映射所述系统存取写命令的LBA到所述区的第三区。
17.根据权利要求16所述的方法，其中：
通过擦除整个块而擦除页：
所述第一区包括第一块；
所述第二区包括第二块；以及
所述第三区包括第三块。
18.根据权利要求17所述的方法，进一步包括擦除所述第一、第二和第三区之一的第一块，而不将所述第一块的有效页重新部署到第二块。
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CN110262981B (zh) * 2018-03-12 2023-08-11 爱思开海力士有限公司 控制器及该控制器的操作方法
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CN112433956A (zh) * 2019-08-26 2021-03-02 美光科技公司 逻辑到物理表高速缓存中基于顺序写入的分区

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