CN102034804A - Multilayer stacked storage and manufacture method thereof - Google Patents

Abstract

The invention discloses a multilayer stacked storage and a manufacture method thereof. A storage chip comprises a gating unit, a peripheral circuit and at least two storage unit layers, and the storage chip comprises at least two kinds of storage units. During the data storage, the data type requiring processing is judged through the peripheral circuit, and then a command is sent to select the special type of storage to make the best of various storage units and realize the optimization of the storage in various properties. During the actual application, one storage chip can replace a plurality of storage chips so as to achieve the purposes of lowering the cost and improving the property.

Description

Multilayer stacked memory and its manufacturing method

technical field

The invention belongs to the technical field of semiconductors, and relates to a memory, in particular to a multi-layer stacked memory; meanwhile, the invention also relates to a method for manufacturing the above-mentioned multi-layer stacked memory.

Background technique

Information technology is the pillar industry of today's national economy, semiconductor technology is the cornerstone of information technology, and semiconductor memory is the core component of the semiconductor system. For nearly half a century, the development of semiconductor memory has been changing rapidly, and various types of memory devices have emerged successively. At present, the most widely used storage devices are as follows: dynamic memory (DRAM), static memory (SRAM), magnetic disk, flash memory (FLASH) and so on. These memories have their own characteristics and advantages, and play an irreplaceable role in various fields. In addition, emerging storage technologies are still emerging, and resistance-switching memories such as phase-change memory (PCRAM), resistive memory (RRAM) and magnetoresistive memory (MRAM) are now hot examples.

Although with the development of semiconductor technology, memory technology has also been greatly improved, and the performance in terms of power consumption, density and speed is getting stronger and stronger. It has outstanding performance and can meet all storage functions. Therefore, in an electronic system, multiple memory chips are often used at the same time to obtain better overall performance. For example, in electronic products including personal computers and smart phones, DRAM+mass memory (FLASH or disk ) and other hybrid modes for data storage. The purpose of this hybrid mode is to fully integrate the non-volatility of FLASH and the high speed and unlimited erasing times of DRAM, and finally realize the optimization of electronic system performance. However, the performance of the system using multiple memory chips still cannot reach the best state, and the cost is relatively high. At present, there is no unified storage mode that can replace the above-mentioned mixed mode. If there is a high-performance unified mode, the performance of the memory will be further improved, the structure of the electronic system will be further simplified, and the cost will be further reduced.

Contents of the invention

The technical problem to be solved by the present invention is to provide a multi-layer stacked memory, which can improve the performance of the memory.

In addition, the invention also provides a method for manufacturing a multi-layer stacked memory.

In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

A multi-layer stacked memory, the memory chip includes gate units, peripheral circuits and at least two memory cell layers, and the memory chip contains at least two types of memory cells. In the process of data storage, the peripheral circuit judges the type of data to be processed, and then sends an instruction to select a specific type of memory, so that various memory units learn from each other to achieve performance optimization in all aspects of the memory. In practical applications, a block A memory chip can replace multiple memory chips to reduce costs and improve performance.

As a preferred solution of the present invention, the memory chip has multiple storage layers and gate transistors corresponding thereto.

As a preferred solution of the present invention, the memory contains at least two types of memory units.

As a preferred solution of the present invention, in the data storage process, different types of storage units are used for data storage and processing for different types of data. The judgment and processing of data types are realized by the control module contained in the peripheral circuit. The control module It can determine the type of data to be processed, and then send an instruction to select a specific memory unit for data storage. The flow of the peripheral circuit judging the type of data to be processed includes one of the following steps: judging whether data storage requires high-speed storage; if so, selecting a storage unit of high-speed storage type; type of storage unit; determine whether the data is stored for a long time, if it is a storage module with a high data retention capacity type; otherwise, select a storage module with a low data retention capacity type.

As a preferred solution of the present invention, the peripheral circuits are shared among the multi-layer memory units.

As a preferred solution of the present invention, the respective characteristics of various types of memory units are brought into play and utilized in the multi-layer stacked memory, and finally have stronger performance than a single memory chip. In practical applications, one chip can replace multiple Memory chips to realize a unified storage mode.

As a preferred solution of the present invention, the memory unit is a volatile memory or a non-volatile memory. The memory units contained in each layer are preferably phase change memory, or resistive random access memory, or magnetoresistive memory, or dynamic random access memory, or static random access memory, or flash memory, or ferroelectric memory.

A method of manufacturing a multi-layer stacked memory comprising multiple types of memory cells, characterized in comprising the steps of:

A. Manufacture the first type of memory cells on Wafer A, and make Wafer A have a flat surface. Wafer A also has peripheral circuits and gating units corresponding to memory cells, wherein the peripheral circuits include read and write. , Erase drive circuit, data judgment circuit and instruction sending circuit;

B. Manufacture the second type of memory and supporting gating units on wafer B, and planarize the surface of wafer B;

C. Using a low-temperature wafer bonding process to bond the above two discretely manufactured memory wafers together, and make each layer electrically connected;

D. Anneal at a temperature below 400 degrees, peel off the excess wafer of wafer B, the peeled wafer can be recycled and reused, and planarize the obtained multi-layer stacked wafer after peeling;

E. Repeat steps B to D to perform a multi-layer memory stacking process until a sufficient number of memory layers is obtained. After the multi-layer stacking is completed, there are peripheral circuits in a specific layer, and the memory cells between each layer can be Sharing peripheral circuits, in the repeated process, it is not necessary to use all the second type of storage cells, and can be other types of storage cells;

F. Leads and packages.

As a preferred solution of the present invention, during the use of the memory chip, the peripheral circuit first judges the type of data to be processed, and then selects a specific memory unit to perform related operations through the instructions of the peripheral circuit.

As a preferred solution of the present invention, the multi-layer stacked memory contains multi-layer structures and multiple types of memory; the method is to combine memory wafers manufactured separately through bonding.

As a preferred solution of the present invention, the highest process temperature of the low-temperature wafer bonding adopted in steps C and D) is lower than 400 degrees.

A method of manufacturing a multi-layer stacked memory comprising multiple types of memory cells, comprising the steps of:

A. First, manufacture the memory array and peripheral circuits with the highest process temperature on Wafer A;

B. Using a wafer bonding process, the semiconductor thin layer is bonded to the above-mentioned wafer A after planarization, and the semiconductor thin layer includes a doped layer that has been activated by high-temperature impurities;

C. Using a semiconductor process to manufacture a gate transistor array on the above-mentioned semiconductor thin layer, and manufacture a corresponding second layer memory array and word/bit line;

D. Fill the medium and perform a planarization process;

E. Repeat steps B-D to manufacture multi-layer stacked memory chips. In the repeating process, it is not necessary to use all the memory cells used in step C, and may be other types of memory cells;

As a preferred solution of the present invention, in the above-mentioned steps, the storage array with a higher maximum process temperature is manufactured first, and then the memory array with a lower maximum process temperature is manufactured, so that the subsequent process temperature does not affect the performance of the manufactured storage device .

As a preferred solution of the present invention, the multi-layer stacked memory includes a multi-layer structure and multiple types of memory.

The beneficial effect of the present invention is that: the multi-layer stacked memory proposed by the present invention can synthesize the advantages of various types of memory, and adopting one memory chip can achieve or exceed the effect of the mixed mode of multiple chips, thereby realizing storage in a unified mode. According to actual needs, the advantages of various types of memory are fully utilized in the application, so that the multi-layer stacked memory has superior comprehensive performance. In addition, the density of the multi-layer stacked memory will increase several times. The final memory not only greatly improves the performance, but also significantly reduces the unit density cost of the memory, reduces the types of memory used in the electronic system, and has obvious advantages in both cost and performance.

The memory chip not only contains a stacked structure of multi-layer semiconductor memory, but also contains multiple types of memory cells, that is, multiple memory chips are included in one chip, realizing a quasi-"unified" mode. In the data processing process, through the judgment of the type of data to be processed, a specific storage unit is selected for data storage, and the advantages of various memory chips inside the memory are fully utilized to achieve the greatest effect. In addition, the multi-layer stacked memory obviously has a huge advantage in density (the multi-layer structure will double the density of the device), because the ultra-long connection is eliminated, and the three-dimensional stacked memory has the advantages of speed, power consumption, etc. Performance will also be greatly improved.

The memory not only has a multi-layer structure (so it has an advantage in density), but also has multiple storage units in a single memory chip, thereby realizing a quasi-"unified" mode of storage, which can replace the existing "hybrid" mode. In practical applications, the peripheral circuit in the chip judges and selects the type of data to be processed, sends instructions, and selects the appropriate type of storage unit for data storage and processing; through the integration of multi-layer and multi-layer storage units, The various memory units contained in the multi-layer stacked memory chip learn from each other, so that the memory has powerful comprehensive performance.

For example, in an electronic system, some data needs to be read frequently, so these data need to be stored in a storage unit with fast reading speed, low power consumption and good fatigue characteristics; If it needs to be read frequently, it can be stored in a large-capacity non-volatile memory, and these memories often do not have advantages in speed and power consumption. In short, different types of data can be stored in different storage units according to the classification of data types. In the existing electronic system, the realization of the above-mentioned process is realized through the mixed mode of multiple different types of storage units, but with the present invention, one chip can realize the comprehensive function of multiple chips in the mixed mode, and greatly improve density.

Description of drawings

Figure 1A is a schematic structural diagram of a multi-layer three-dimensional stacked memory, which is illustrated by taking 1-layer MARAM, 2-layer RRAM, and 1-layer PCRAM as examples (the figure is only a partial schematic diagram, and the peripheral circuits, gates, etc. are not drawn, and are also Not drawn to scale).

FIG. 1B is a schematic diagram of units of three different memories involved in FIG. 1A .

Figures 1C-1F are process flow diagrams for fabricating the structure.

2A-C are schematic diagrams of a module having a judging function performing judgment during data processing.

Detailed ways

Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment one

The structure diagram of the resistive switching memory with a multi-layer stack structure shown in FIG. 1A is better explained by this, but it does not mean that the present invention is the structure shown in FIG. 1A. Now the number of layers of the memory can be changed, Kind, size, arrangement and structure, none of these are limiting elements of the present invention.

It can be seen from FIG. 1A that the device has a multilayer stack structure, including one MRAM layer 101 , two RRAM layers 102 and one PCRAM layer 103 . Each of the above-mentioned layers not only includes resistive memory cells, but also includes corresponding gate cells (although not shown in the figure, it does not mean that there are none). In addition, layer 101 not only includes magnetoresistive memory units and gating units, but also generally includes peripheral circuits, which are shared by all layers, and play the role of gating and operating the above four layers of memory, and also have the function of controlling data. judgment and arrangement.

FIG. 1B is a schematic diagram of the structure of three kinds of memory cells of MRAM, RRAM and PCRAM respectively.

The upper magnet electrode layer 15, the insulator layer 14 and the lower magnet electrode layer 13 of the MRAM form a simple storage unit. Generally speaking, the magnetization direction of the lower magnet electrode layer 13 is fixed, and by controlling the direction of the current flowing in the upper magnet electrode layer , change the magnetization direction of the upper magnet electrode layer, and then change the resistance of the entire device unit: that is, if the upper magnet electrode layer is in the same direction as the lower layer, the resistance of the device will decrease, which is a logic "0" state; When the lower layer is reversed, the resistance of the device will increase, which is the logic "1" state. Apparently in FIG. 1A , in layer 101, there are two MRAM cells whose state is “1”, and one cell whose state is “0” (for example). MRAM is characterized by extremely fast speed, but its disadvantages are low density and high cost, and it is suitable as a small-capacity fast memory.

The structure of RRAM is composed of upper and lower electrodes (24 and 26) and metal oxide 25. The upper and lower electrodes are generally noble metals, and data storage is performed through the resistance conversion generated by the metal oxide 25 with a strong correlation effect when an electrical signal is applied, such as high resistance Logic "1" for low resistance and logic "0" for low resistance. The structure and manufacturing process of RRAM are simple, and the cost is low, but the erasability is very poor. It is not suitable for products that are often used in frequent operations, but it is suitable for large-capacity data storage.

The structure of PCRAM is roughly similar to that of RRAM, and it is also composed of electrode pairs and memory cells. Because the power consumption of PCRAM is continuously reduced with the reduction of the size of the cells, in most cases, in addition to the upper and lower electrodes 33 and 36, there will often be There are sidewalls 34 to limit the volume of the phase change material 35, so that the contact area between the phase change material 35 and the bottom electrode 33 is greatly reduced to obtain better performance, and at the same time limit the diffusion of the phase change material during heating. The structure and manufacturing process of PCRAM are also very simple, the cost is also low, the data retention ability and fatigue characteristics are good, but the tolerance to high temperature process is low.

To sum up, the above three types of memory have their own strengths and weaknesses in various aspects and can form a good complement. If they can be integrated together, the overall performance of the memory chip will be greatly improved.

In fact, it is not limited to the above three types of memory, and it is also true for other types of memory. Here, the above three types of memory are used as examples for illustration. In practical applications, memories such as DRAM or SRAM can also be integrated with memories such as FLASH to form the above-mentioned multi-layer stack structure, which is obviously also within the protection scope of the present invention and will not be repeated here.

Please refer to FIG. 1A-FIG. 1F, the present invention discloses a method for manufacturing a multilayer stacked resistance switching memory, including the following steps:

[Step 1] Firstly, a peripheral circuit (not shown in FIG. 1C ) and an MRAM cell array are fabricated on the silicon substrate 11 . The structure of the MRAM cell 16 is shown in FIG. 1B . The peripheral circuit includes not only the read, write, and erase circuits, but also the circuit for judging and sending instructions. The MRAM array is composed of MRAM storage units and MOSFET gates, which are not shown in the figure. Planarization is achieved after fabrication, as shown in Figure 1C.

[Step 2] Form a layer of silicon layer (single crystal or polycrystalline) on the above-mentioned 101 layer by semiconductor process, as the basis for manufacturing the gate tube, and form a PN junction or Schottky potential after doping on the silicon substrate 21 Barrier (need to add a metal layer), PN junction or Schottky barrier will be used in subsequent steps to manufacture gate cells, as shown in Figure 1D.

[Step 3] Manufacture an RRAM unit above the corresponding gate unit, which has a sandwich structure. The unit structure is shown in FIG. 1B , and each unit is electrically isolated by a dielectric material 12 .

[Step 4] Repeat steps 2 and 3 to form a second RRAM layer, as shown in Figure 1E.

[Step 5] Form a PN junction or Schottky barrier after doping on the silicon substrate C, and the PN junction or Schottky barrier will be used to manufacture gate units in subsequent steps.

[Step 6] Transfer the surface silicon of the silicon substrate C with a PN junction or Schottky barrier to the above-mentioned memory array obtained in step 4 (as shown in Figure 1F) by bonding, and remove the redundant silicon substrate (The stripping or thinning method can be used.

[Step 7] Manufacture the gate unit and the corresponding phase-change memory array on the silicon substrate obtained by the above-mentioned bonding through a semiconductor process, and the phase-change memory unit has a sidewall structure.

[Step 8] Through encapsulation, a multi-layer stacked memory including one layer of MRAM, multiple layers of RRAM and one layer of phase-change memory is obtained, as shown in FIG. 1A . Obviously, the type of memory used in the above process steps and the number of stacked layers can be changed according to actual needs, and a brief example is given here.

[Step 9] In the obtained multi-layer stacked memory, MRAM has a fast speed, but low density; RRAM is characterized by a simple structure, because metal oxide is used as a storage medium material, so it has a strong tolerance to process temperature. That is, higher process temperatures can be tolerated. Relatively speaking, higher process temperature may cause damage to phase change memory, therefore, the corresponding high temperature manufacturing process is placed at the front end of the process

[Step 10] Practical application. Compared with RRAM, phase change memory has great advantages in terms of reliability and erasable times. It can largely make up for the lack of performance of high-density, low-cost RRAM devices, and at the same time make up for the density disadvantage of MRAM. In the end, more The layer-stacked memory not only has ultra-high density, but also has better overall performance and lower cost. Therefore, in the actual operation process, the peripheral circuit can judge whether a high-speed device is needed for the data, if yes, use MRRAM, if not, use RRAM device for data storage. The specific judgment process can be as follows: the peripheral circuit first judges whether data storage needs high-speed storage; if so, then selects a high-speed storage type storage unit; otherwise, judges whether data operations are frequent, and if so, selects a high-fatigue type storage unit; otherwise , to determine whether the data is stored for a long time, if it is a storage module with a high data retention capacity type; otherwise, a storage module with a low data retention capacity type is selected.

To sum up, the multi-layer stacked memory proposed by the present invention can integrate the advantages of various types of memory, and adopting one memory chip can achieve or exceed the effect of the mixed mode of multiple chips, thereby realizing storage in a unified mode. According to actual needs, the advantages of various types of memory are fully utilized in the application, so that the multi-layer stacked memory has superior comprehensive performance. In addition, the density of the multi-layer stacked memory will increase several times. The final memory not only greatly improves the performance, but also significantly reduces the unit density cost of the memory, reduces the types of memory used in the electronic system, and has obvious advantages in both cost and performance.

Embodiment two

In this embodiment, the manufacturing method of the multilayer stacked resistance switching memory of the present invention includes the following steps:

[Step 1] Manufacture peripheral circuits and two layers of DRAM storage layers on wafer A. These two layers of DRAM cells will be used as high-speed memory.

[Step 2] Manufacture polysilicon on wafer A using a low-temperature process, manufacture polysilicon diodes and corresponding phase-change memory arrays through semiconductor processes, and obtain polysilicon diode-gated phase-change memory through filling and planarization of dielectric materials layer, the polysilicon diode can be a PN diode or a Schottky diode.

[Step 3] Continue to deposit polysilicon on the multi-layer memory wafer obtained above to manufacture subsequent storage layers until the desired number of layers is reached.

【Step 4】Lead package.

[Step 5] Practical application. Compared with phase change memory, the advantage of DRAM is its speed and almost unlimited erasable times, while the advantage of phase change memory is its high density and non-volatility. DRAM and phase change memory are integrated on the same wafer, It will not only have DRAM high speed and almost unlimited erasable times in the same memory chip, but also have the characteristics of high density and non-volatility, and will have important application value in consumer electronics. At the same time, the superposition of DRAM and phase change memory will achieve greater density on the same chip area. In practical applications, it is first possible to judge through the peripheral circuit whether the data to be processed requires frequent operations. If so, select the DRAM part for storage, and if not, select the phase change memory.

Embodiment Three

The invention discloses a method for manufacturing a multi-layer stacked resistance switching memory, comprising the following steps:

[Step 1] Firstly, the peripheral circuit and the RRAM array are manufactured on the silicon base A, wherein the peripheral circuit not only includes the read, write, and erase circuits, but also includes the judgment and sending instruction circuit parts, and the RRAM array is composed of RRAM memory cells and gate transistors. Planarization is achieved after fabrication.

[Step 2] After doping on the silicon substrate B, a PN junction or Schottky barrier is formed, and the PN junction or Schottky barrier will be used to manufacture gate units in subsequent steps.

[Step 3] Transfer the surface layer silicon with a PN junction or Schottky barrier on the surface of the silicon substrate B to the above-mentioned array obtained on the silicon substrate A by bonding, and remove the redundant silicon substrate (can be stripped or thinned Law.

[Step 4] After planarization, gate cells and corresponding RRAM arrays are fabricated on the silicon substrate obtained by bonding above through a semiconductor process.

[Step 5] Repeat steps 2 to 4 until enough RRAM storage layers are obtained.

[Step 6] Form a PN junction or Schottky barrier after doping on the silicon substrate C, and the PN junction or Schottky barrier will be used to manufacture gate units in subsequent steps.

[Step 7] Transfer the surface layer silicon with PN junction or Schottky barrier on the surface layer of the silicon substrate C to the array obtained in step 5 by bonding, and remove the redundant silicon substrate (the stripping or thinning method can be used The gate unit and the corresponding phase-change memory array are manufactured on the silicon substrate obtained by the above-mentioned bonding through a semiconductor process.

[Step 8] Repeat steps 6 to 7 until enough PCRAM storage layers are obtained.

[Step 9] A multi-layer stacked memory including multi-layer RRAM and multi-layer phase change memory is obtained through packaging. Obviously, the type of memory used in the above process steps and the number of stacked layers can be changed according to actual needs.

[Step 9] In the actual application process, the peripheral circuit can judge the data type to choose PCRAM or RRAM for data storage, and the judgment standard can be set by the user. For example, the process of the peripheral circuit judging the type of data to be processed includes one of the following steps: judging whether data storage requires high-speed storage; if so, selecting a storage unit of the high-speed storage type; A storage unit of high fatigue type; judging whether the data is stored for a long time, if it is a storage module with a high data retention capacity; otherwise, a storage module with a low data retention capacity is selected.

In application, the peripheral circuit selects a suitable type of storage unit for data storage and processing according to the data judgment process similar to that shown in Fig. 2A-C.

For example, first determine whether data storage requires high-speed storage; if so, select a high-speed storage type storage unit; otherwise, determine whether data reading is frequent, and if so, select a high-fatigue type storage unit; otherwise, select a high-data management type storage module.

Obviously, in practical applications, memory chips have different numbers and types of memory chips. In a simple electronic system, perhaps only one judgment (such as whether it is high-speed, whether it is frequent, as shown in 2B and 2C) is required to select the data type; and in a complex electronic system, there may be more than two types of memory chips, and the corresponding judgment becomes more complicated.

Although the method of centralized judgment is demonstrated here, it should be pointed out that this can be adjusted according to actual needs, and even an option can be left in the memory chip for the user to set the judgment standard by himself, which is not limiting the present invention Characteristics.

The description and application of the invention herein is illustrative and is not intended to limit the scope of the invention to the above-described embodiments. Variations and changes to the embodiments disclosed herein are possible, and substitutions and equivalents for various components of the embodiments are known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be realized in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other modifications and changes may be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims (16)

1. A multi-layer stacked memory, characterized in that: the memory chip includes peripheral circuits and at least two layers of memory cell layers and gate cells corresponding thereto, and the memory chip contains at least two types of memory cells; During the data storage process, the peripheral circuit judges the type of data to be processed, and then sends an instruction to select a specific type of memory for data storage according to the judgment result. 2. The multi-layer stacked memory according to claim 1, characterized in that: In the process of data storage, different types of storage units are used for data storage or processing for different types of data. 3. The multi-layer stacked memory according to claim 1, characterized in that: The peripheral circuit includes a control module, which can determine the type of data to be processed, and then send an instruction according to the result of the determination to select a corresponding memory unit for data storage. 4. The multi-layer stacked memory according to any one of claims 1 to 3, characterized in that: The process of determining the data type to be processed by the peripheral circuit includes one of the following steps: Determine whether data storage requires high-speed storage; if so, select a storage unit of high-speed storage type; Determine whether the data operation is frequent, and if so, select a high-fatigue storage unit; It is judged whether the data is to be stored for a long time, and if it is selected, a storage module with a high data retention capacity is selected; otherwise, a storage module with a low data retention capacity is selected. 5. The multi-layer stacked memory according to any one of claims 1 to 3, characterized in that: Peripheral circuits are shared among the multilayer memory cells. 6. The multi-layer stacked memory according to any one of claims 1 to 3, characterized in that: The memory unit is a volatile memory or a non-volatile memory. 7. The multi-layer stacked memory according to any one of claims 1 to 3, characterized in that: The type of the memory unit contained in each layer is a phase change memory, or a resistance random access memory, or a magnetoresistive memory, or a dynamic random access memory, or a static random access memory, or a flash memory, or a ferroelectric memory. 8. A method for manufacturing a multilayer stacked memory, characterized in that the method comprises the steps of: A. Manufacture the first type of memory cells on the first wafer, and make the first wafer have a flat surface. The first wafer also has peripheral circuits and gate units corresponding to the memory cells, wherein the peripheral circuits include Read, write, wipe drive circuit and data judgment circuit and instruction sending circuit; B. Manufacture a set type of memory and supporting gating units on the second wafer, and planarize the surface of the second wafer; C. Using a low-temperature wafer bonding process to bond the above two discretely manufactured memory wafers together, and make each layer electrically connected; D. Annealing at a temperature below 400 degrees, peeling off the excess part of the second wafer, and performing a planarization process on the obtained multi-layer stacked wafer after peeling; E. Repeat steps B to D to perform a multi-layer memory stacking process until a set number of memory layers is obtained. After the multi-layer stacking is completed, there are peripheral circuits in a specific layer, and the memory cells between each layer Shared peripheral circuits; the same or different types of memory in step B during the repeated process; F. Leads and packages. 9. The method for manufacturing a multi-layer stack memory according to claim 8, characterized in that: During the use of the memory chip, the peripheral circuit first judges the type of data to be processed, and then according to the judgment result, selects a specific memory unit to perform related operations through the instructions of the peripheral circuit. 10. The method for manufacturing a multi-layer stack memory according to claim 8, characterized in that: A multi-layer stacked memory contains multiple layers and multiple types of memory. 11. The method for manufacturing a multilayer stack memory according to claim 8, characterized in that: The memory wafers are manufactured separately and then bonded together to form a multilayer structure. 12. The method for manufacturing a multi-layer stack memory according to claim 8, characterized in that: The process temperature of the low-temperature wafer bonding adopted in step C and step D is lower than 400 degrees. 13. A method for manufacturing a multi-layer stacked memory, characterized in that the method comprises the steps of: S1, first fabricate a memory array and peripheral circuits with a higher maximum process temperature on the first wafer; S2. Using a wafer bonding process, bonding the thin semiconductor layer to the above-mentioned first wafer after planarization, the thin semiconductor layer includes a doped layer that has undergone high-temperature impurity activation treatment; S3. Using a semiconductor process, manufacturing a gate transistor array on the above-mentioned semiconductor thin layer, and manufacturing a corresponding second-layer memory array and word/bit line; S4, filling the medium, and performing a planarization process; S5. Steps S2-S4 are repeated to manufacture a multi-layer stacked memory chip, and the memory manufactured in the repeating process is the same or different from the memory type in step S3. 14. The method for manufacturing a multilayer stack memory according to claim 13, characterized in that: In the above steps, the memory array with a higher maximum process temperature is manufactured first, and then the memory array with a lower maximum process temperature is manufactured. 15. The method for manufacturing a multilayer stack memory according to claim 13, characterized in that: A multi-layer stacked memory contains multiple layers and multiple types of memory. 16. The method of manufacturing a multi-layer stack memory according to claim 13, characterized in that: The surface semiconductor transferred to the first wafer through the bonding method contains a doped layer, and the impurities have been activated at a high temperature.

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