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CN102023811A - Method, controller and storage system for issuing programmed instructions to flash memory - Google Patents

Method, controller and storage system for issuing programmed instructions to flash memory Download PDF

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Publication number
CN102023811A
CN102023811A CN2009101721618A CN200910172161A CN102023811A CN 102023811 A CN102023811 A CN 102023811A CN 2009101721618 A CN2009101721618 A CN 2009101721618A CN 200910172161 A CN200910172161 A CN 200910172161A CN 102023811 A CN102023811 A CN 102023811A
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China
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flash memory
host
write
buffer
data
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CN2009101721618A
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CN102023811B (en
Inventor
叶志刚
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The embodiment of the invention provides a method, a controller and a storage system for issuing a programming command to a flash memory. The method includes receiving a plurality of host write commands and write data corresponding to the host write commands from a host system using a Native Command Queuing (NCQ) protocol, and issuing a cache program Command to the flash memory chip to write the write data into the flash memory chip. Therefore, the time for executing the host write command can be effectively shortened by only using the cache program command and the native instruction sorting protocol to execute the data write.

Description

Flash memory is assigned method, controller and the stocking system of programmed instructions
Technical field
The present invention relates to a kind of flash controller and flash memory system of flash memory being assigned method and use the method for programmed instructions.
Background technology
Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., the most suitable being used on the portable electronic product.For example, solid state hard disc is exactly a kind of with the storage device of nand flash memory as Storage Media, and extensively is disposed in the mobile computer as main storage device.
Fig. 1 is the summary calcspar of the general flash memory of diagram.In general, when host computer system 110 sees through connector 122 and flash memory electric connection and desire storage data to flash memory 120, write data to the program of the flash memory module 126 of flash memory 120 and can divide into data transmission (transfer) and two parts of data programization (program).Specifically, when host computer system 110 is desired in flash memory 120 storage data, flash controller 124 can be by data input/output bus 128 with the buffer zone 132 of data transmission to the flash memory module 126, afterwards flash memory module 126 can with the data programization in the buffer zone 132 to the storer of flash memory module 126 (promptly, the storage area) 134, wherein flash memory module 126 with data programization during the storer 134, flash memory module 126 is to be in actual busy (busy) state, and can't assign any instruction or transmit any data it when flash memory module 126 is under the actual busy condition flash controller 124.That is to say that flash controller 124 must could respond the next instruction of host computer system 110 and processing host system 110 after flash memory module 126 is finished sequencing.
Specifically, when flash controller 124 receives main frame when writing instruction and needing to write data with writing data and write to flash memory module 126 from host computer system 110, flash controller 124 can be assigned programmed instructions by data input/output bus 128, and the relevant information in this programmed instructions will be temporary in the buffer zone 132.For example, this programmed instructions is made up of with character strings such as " instruction W2 " " instruction W1 ", " physical address ", " writing data ", wherein flash controller 124 is prepared the executive routine program by " instruction W1 " indication flash memory module 126, by the address that " physical address " indication flash memory module 126 is desired sequencing, desire the data of sequencing and pass through " instruction W2 " indication flash memory module 126 beginning executive routineizations by " writing data " indication flash memory module 126.Therefore, when flash memory module 126 begins that according to " instruction W2 " in the programmed instructions data in the buffer zone 132 are write to storer 134, flash controller 124 just can be replied host computer system 110 after need receiving the affirmation of finishing sequencing (acknowledgement) information that comes from flash memory module 126, in general, assign the time of instructing host computer system to receive the confirmation information when host computer system and be called the response time (response time).
Along with the development of transmission technology, make the transmission speed of connector significantly promote, for example, advanced annex (the Serial Advanced Technology Attachment of sequence, SATA) connector can reach 1,500,000,000 of per seconds (Gigabit, Gb), even per second 30Gb.Yet the speed of said procedure flash memory but under the speed of far low connector, still can't effectively improve by the whole usefulness that stores, and how to shorten therefore that to carry out the time that main frame writes instruction be the target that these those skilled in the art endeavour.
Summary of the invention
The invention provides a kind of method of assigning programmed instructions, it can shorten effectively carries out the time that main frame writes instruction.
The invention provides a kind of flash controller, it can shorten effectively carries out the time that main frame writes instruction.
The invention provides a kind of flash memory system, can shorten effectively and carry out the time that main frame writes instruction.
Exemplary embodiment of the present invention proposes a kind of method of assigning programmed instructions, and the data that are used for coming from a host computer system write to a flash chip.Originally the method for assigning programmed instructions comprises provides a flash controller, and (Native Command Queuing, NCQ) agreement receives a plurality of main frames and writes instruction from host computer system to use a primary instruction ordering by flash controller.Originally the method for assigning programmed instructions comprises that also writing instruction transmission one by flash controller according to main frame assigns instruction sequences to host computer system.Originally the method for assigning programmed instructions also comprises according to assigning instruction sequences and receives main frame in order write instruction and write a plurality of data that write of instruction with respective hosts from host computer system, and assigns a fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Exemplary embodiment of the present invention proposes a kind of flash controller, and the data that are used for coming from a host computer system write to a flash chip.This flash controller comprises a microprocessor unit, a memory buffer, a flash interface unit, a host interface unit and a memory management unit.The flash interface unit is electrically connected to microprocessor unit, and in order to connect flash chip.Memory buffer is electrically connected to microprocessor unit.Host interface unit is electrically connected to microprocessor unit, and in order to connect above-mentioned host computer system, wherein host interface unit is supported the NCQ agreement.Memory management unit is electrically connected to microprocessing unit, and writes instruction in order to use the NCQ agreement to receive a plurality of main frames from host computer system by host interface unit.In addition, memory management unit writes instruction transmission one by host interface unit according to main frame and assigns instruction sequences to host computer system.Moreover, memory management unit sees through host interface unit and receives main frame in order write instruction and write a plurality of data that write of instruction with respective hosts from host computer system according to assigning instruction sequences, and assigns fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Exemplary embodiment of the present invention proposes a kind of flash memory system, is used to store the data that come from a host computer system.This flash memory system comprises that in order to a connector that electrically connects above-mentioned host computer system, a flash chip and a flash controller wherein connector is supported the NCQ agreement.Flash controller is electrically connected to connector and flash chip, and writes instruction in order to use the NCQ agreement to receive a plurality of main frames from host computer system by connector.In addition, flash controller writes instruction transmission one according to main frame and assigns instruction sequences to host computer system.Moreover, flash controller sees through connector and receives main frame in order write instruction and write a plurality of data that write of instruction with respective hosts from host computer system according to the above-mentioned instruction sequences of assigning, and assigns a fast program fetch instruction to flash chip respectively and write in the flash chip will write data.
Based on above-mentioned, the method for assigning programmed instructions, flash controller and the flash memory system of exemplary embodiment of the present invention can shorten effectively to be carried out the time that main frame writes instruction, promotes the usefulness of data access thus.
Also in conjunction with the accompanying drawings the present invention is described in further detail below by specific embodiment.
Description of drawings
Fig. 1 is the summary calcspar of the general flash memory system of diagram;
Fig. 2 A is a host computer system of using flash memory according to embodiment of the invention diagram;
Fig. 2 B is the synoptic diagram of the illustrated computing machine of exemplary embodiment, input/output device and flash memory according to the present invention;
Fig. 2 C is the synoptic diagram of the illustrated host computer system of another exemplary embodiment and flash memory according to the present invention;
Fig. 2 D is the summary calcspar of the illustrated flash memory of exemplary embodiment according to the present invention;
Fig. 3 is the summary calcspar of the illustrated flash memory crystal grain of exemplary embodiment according to the present invention;
Fig. 4 A is that the illustrated flash controller of exemplary embodiment sees through the example schematic that the data input/output bus is assigned fast program fetch instruction according to the present invention;
Fig. 4 B is the time sequences figure according to flash chip illustrated in the instruction shown in Fig. 4 A;
Fig. 5 is the illustrated process flow diagram of assigning programmed instructions of exemplary embodiment according to the present invention.
Description of reference numerals:
110: host computer system; 120: flash memory;
122: connector; 124: flash controller;
126: flash memory module; 128: the data input/output bus;
132: buffer zone; 134: storer;
200: flash memory; 202: connector;
204: flash controller; 206: microprocessor unit;
208: memory management unit; 210: host interface unit;
212: the flash interface unit; 214: memory buffer;
220: flash chip; 290: host computer system;
295: bus; 300: the 0 flash memory modules;
302: the 0 data input/output bus; 310: the 1 flash memory modules;
312: the 1 data input/output bus; 320: the 2 flash memory modules;
322: the 2 data input/output bus; 330: the 3 flash memory modules;
332: the 3 data input/output bus; 340: the 4 flash memory modules;
342: the 4 data input/output bus; 350: the 5 flash memory modules;
352: the 5 data input/output bus; 360: the 6 flash memory modules;
362: the 6 data input/output bus; 370: the 7 flash memory modules;
372: the 7 data input/output bus; 400: the 0 flash memory crystal grain;
402: the storage area; 404: the first buffer zones;
406: the second buffer zones; 410: the 1 flash memory crystal grain;
420: the 2 flash memory crystal grain; 430: the 3 flash memory crystal grain;
440: the 4 flash memory crystal grain; 450: the 5 flash memory crystal grain;
460: the 6 flash memory crystal grain; 470: the 7 flash memory crystal grain;
480: the 8 flash memory crystal grain; 490: the 9 flash memory crystal grain;
500: the 10 flash memory crystal grain; 510: the 11 flash memory crystal grain;
520: the 12 flash memory crystal grain; 530: the 13 flash memory crystal grain;
540: the 14 flash memory crystal grain; 550: the 15 flash memory crystal grain;
1100: computing machine; 1102: microprocessor;
1104: random access memory; 1106: input/output device;
1108: system bus; 1110: data transmission interface;
1202: mouse; 1204: keyboard;
1206: display; 1208: printer;
1212: carry-on dish; 1214: memory card;
1216: solid state hard disc; 1310: digital still camera;
The 1310a:SD card; The 1310b:MMC card;
The 1310c:CF card; 1310d: memory stick;
1310e: embedded storage device; W1, W2, W3: instruction;
D1, D2, D3: data; ADD1, ADD2, ADD3: physical address;
CM1, CM2, CM3, CM4, CM5, CM6, CM7, CM8, CM9: instruction;
T1, T2, T3: data transmission; B1, B2, B3: busy time;
S501, S503, S505, S507, S509, S511, S513, S515, S517: the step of assigning programmed instructions.
Embodiment
Generally speaking flash memory comprises flash chip and controller (also claiming control circuit).Usually flash memory can use with host computer system, so that host computer system can write to data flash memory or reading of data from flash memory.In addition, flash memory also being arranged is to comprise embedded flash memory and can be executed on the host computer system with substantially as the software of this embedded flash controller.
Fig. 2 A is a host computer system of using flash memory according to embodiment of the invention diagram.
Please refer to Fig. 2 A, host computer system 290 generally comprises computing machine 1100 and I/O (input/output, I/O) device 1106.Computing machine 1100 comprise microprocessor 1102, random access memory (random access memory, RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 comprises mouse 1202, keyboard 1204, the display 1206 and printer 1208 as Fig. 2 B.It must be appreciated, the unrestricted input/output device 1106 of the device shown in Fig. 2 B, input/output device 1106 can also comprise other device.
Flash memory 200 is to electrically connect by data transmission interface 1110 other assembly with host computer system 290 in embodiments of the present invention.Data can be write to flash memory 200 or reading of data from flash memory 200 by microprocessor 1102, random access memory 1104 with the processing of input/output device 1106.For example, flash memory 200 can be carry-on dish 1212, memory card 1214 or solid state hard disc (Solid State Drive, SSD) 1216 shown in Fig. 2 B.
Generally speaking, but host computer system 290 can be any system of storage data substantially.Though in this exemplary embodiment, host computer system 290 is to explain with computer system, yet host computer system 290 can be systems such as digital camera, video camera, communicator, message player or video signal player in another exemplary embodiment of the present invention.For example, in host computer system is digital camera (video camera) 1310 o'clock, and flash memory then is its employed SD card 1310a, mmc card 1310b, CF card 1310c, memory stick (memory stick) 1310d or embedded storage device 1310e (shown in Fig. 2 C).Embedded storage device 1310e comprise the built-in multimedia card (Embedded MMC, eMMC).What deserves to be mentioned is that the built-in multimedia card is directly to be electrically connected on the substrate of host computer system.
Fig. 2 D is the detailed block diagram of flash memory 200 shown in the pictorial image 2A.
Please refer to Fig. 2 D, flash memory 200 comprises connector 202, flash controller 204 and flash chip 220.
Connector 202 is to be electrically connected to flash controller 204 and to connect host computer systems 290 in order to pass through bus 295.In this exemplary embodiment, connector 202 is advanced annex (Serial AdvancedTechnology Attachment, a SATA) connector of sequence.Particularly, the primary instruction ordering of connector 202 supports (Native Command Queuing, NCQ) agreement, and be to transmit with the NCQ agreement to write instruction between host computer system 290 and the flash controller 204.Specifically, when transmitting main frame and write instruction with the NCQ agreement between host computer system 290 and the flash controller 204, a plurality of main frames that host computer system 290 can send desire earlier write instruction and send flash controller 204 together to, and flash controller 204 is assigned instruction sequences to host computer system 290 its expections of response, particularly, host computer system 290 only transmits the instruction of desiring to assign and gives flash controller 204 in this process, and can not transmit the data of desiring to write.Afterwards, host computer system 290 transmits main frame according to the response of flash controller 204 and writes instruction and data, and flash controller 204 responds host computer system 290 again after finishing All hosts to write instruction each writes the executing state of instruction.Particularly, when sequencing mistake (program fail) took place, host computer system 290 can retransfer instruction and the data that the sequencing mistake takes place correspondence to flash controller 204 according to the reported information (that is executing state) of flash controller 204.Perhaps, in another exemplary embodiment of the present invention, when sequencing mistake (program fail) took place, host computer system 290 can retransfer all instructions to flash controller 204 with data.
In addition, it must be appreciated that in exemplary embodiment of the present invention, connector 202 so the invention is not restricted to this for supporting the SATA connector of NCQ, connector 202 also can be other connector of supporting the NCQ agreement.
Flash controller 204 can be carried out with hardware pattern or real a plurality of logic locks or the steering order of doing of firmware pattern, and carries out the runnings such as writing, read and erase of data in flash chip 220 according to the instruction of host computer system 290.Flash controller 204 comprises microprocessor unit 206, memory management unit 208, host interface unit 210, flash interface unit 212 and memory buffer 214.
Microprocessor unit 206 is the main control unit of flash controller 204, in order to cooperative cooperatings such as memory management unit 208, host interface unit 210, flash interface unit 212 and memory buffer 214 to carry out the various runnings of flash memory 200.
Memory management unit 208 is to be electrically connected to microprocessor unit 206, in order to carry out according to this exemplary embodiment assign programmed instructions and block management mechanism, the running of memory management unit 208 will elaborate in following cooperation is graphic.
In this exemplary embodiment, memory management unit 208 is to be embodied in the flash controller 204 with a firmware pattern.For example, the memory management unit 208 that will comprise a plurality of steering orders (for example is burned onto a program internal memory, ROM (read-only memory) (Read Only Memory, ROM)) be embedded in the flash controller 204 in and with this program internal memory, when flash memory 200 running, a plurality of steering orders of memory management unit 208 can be carried out to finish by microprocessor unit 206 and assign programmed instructions and block management mechanism according to the embodiment of the invention.
In another exemplary embodiment of the present invention, the steering order of memory management unit 208 also can the program code pattern be stored in the specific region (for example, being exclusively used in the system region of storage system data in the flash chip) of flash chip 220.Same, when flash memory 200 runnings, a plurality of steering orders of memory management unit 208 can be carried out by microprocessor unit 206.In addition, in another exemplary embodiment of the present invention, memory management unit 208 also can a hardware pattern be embodied in the flash controller 204.
Host interface unit 210 is instruction and the data that are electrically connected to microprocessor unit 206 and transmitted in order to reception and identification host computer system 290.That is to say that instruction that host computer system 290 is transmitted and data can be sent to microprocessor unit 206 by host interface unit 210.In this exemplary embodiment, host interface unit 210 is that corresponding connector 202 is the SATA interface.Yet, it must be appreciated to the invention is not restricted to this that host interface unit 210 also can be other data transmission interface that is fit to.
Flash interface unit 212 is to be electrically connected to microprocessor unit 206 and in order to access flash chip 220.That is to say that the data of desiring to write to flash chip 220 can be converted to 220 receptible forms of flash chip by flash interface unit 212.
Memory buffer 214 is to be electrically connected to microprocessor unit 206 and in order to the temporary data that come from the data and instruction of host computer system 290 or come from flash chip 220.
In addition, though not shown in this exemplary embodiment, flash controller 204 yet comprises general utility functions modules such as error correction unit and Power Management Unit.
Flash chip 220 is to be electrically connected to flash controller 204 and in order to storage data.Flash chip 220 comprises the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370.In this exemplary embodiment, the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 are multilayer storer (Multi LevelCell, MLC) nand flash memory module.Yet, the invention is not restricted to this, the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 be single layer of memory (Single Level Cell, SLC) nand flash memory module also.
In this exemplary embodiment, the 0th flash memory module the 300, the 1st flash memory module the 310, the 2nd flash memory module the 320, the 3rd flash memory module the 330, the 4th flash memory module the 340, the 5th flash memory module the 350, the 6th flash memory module 360 and the 7th flash memory module 370 are to be electrically connected to flash controller 204 respectively.Specifically, the flash interface unit 212 of flash controller 204 is respectively by the 0th data input/output bus (Data input/output bus) 302, the 1st data input/output bus 312, the 2nd data input/output bus 322, the 3rd data input/output bus 332, the 4th data input/output bus 342, the 5th data input/output bus 352, the 6th data input/output bus 362 and the 7th data input/output bus 372 transmit data and give the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, the 6th flash memory module 360 and the 7th flash memory module 370.
In this exemplary embodiment, the 0th flash memory module 300 comprises the 0th flash memory crystal grain (die) 400 and the 1st flash memory crystal grain 410, the 1st flash memory module 310 comprises the 2nd flash memory crystal grain 420 and the 3rd flash memory crystal grain 430, the 2nd flash memory module 320 comprises the 4th flash memory crystal grain 440 and the 5th flash memory crystal grain 450, the 3rd flash memory module 330 comprises the 6th flash memory crystal grain 460 and the 7th flash memory crystal grain 470, the 4th flash memory module 340 comprises the 8th flash memory crystal grain 480 and the 9th flash memory crystal grain 490, the 5th flash memory module 350 comprises that the 10th flash memory crystal grain 500 and the 11st flash memory crystal grain 510, the 6 flash memory modules 360 comprise that the 12nd flash memory crystal grain 520 and the 13rd flash memory crystal grain 530 and the 7th flash memory module 370 comprise the 14th flash memory crystal grain 540 and the 15th flash memory crystal grain 550.
What deserves to be mentioned is, in exemplary embodiment of the present invention, the 0th flash memory module 300, the 1st flash memory module 310, the 2nd flash memory module 320, the 3rd flash memory module 330, the 4th flash memory module 340, the 5th flash memory module 350, dispose the 0th data input/output bus 302 respectively between the 6th flash memory module 360 and the 7th flash memory module 370 and the flash controller 204, the 1st data input/output bus 312, the 2nd data input/output bus 322, the 3rd data input/output bus 332, the 4th data input/output bus 342, the 5th data input/output bus 352, the 6th data input/output bus 362 and the 7th data input/output bus 372, therefore memory management unit 208 can use parallel model (parallelmode) to transmit by many data input/output bus simultaneously and write data to corresponding flash memory module, to promote access speed.In addition, each flash memory module comprises two flash memory crystal grain, so memory management unit 208 can use interleaving modes (interleave mode) be sent to two interior flash memory crystal grain of same flash memory module with will writing data interlace, more to increase access usefulness.In more detail, as mentioned above, the process that writes data in flash memory crystal grain comprises data transmission (transfer) and two parts of data programization (program), and interleaving mode (interleave mode) is exactly in the example of two flash memory crystal grain that use same data input/output bus transmission data, utilize one of them flash memory crystal grain just carrying out the data sequencing during transmit data and give another flash memory crystal grain.
Fig. 3 is the summary calcspar of the illustrated flash memory crystal grain of exemplary embodiment according to the present invention.At this, the 0th flash memory crystal grain the 400, the 1st flash memory crystal grain the 410, the 2nd flash memory crystal grain the 420, the 3rd flash memory crystal grain the 430, the 4th flash memory crystal grain the 440, the 5th flash memory crystal grain the 450, the 6th flash memory crystal grain the 460, the 7th flash memory crystal grain the 470, the 8th flash memory crystal grain the 480, the 9th flash memory crystal grain the 490, the 10th flash memory crystal grain the 500, the 11st flash memory crystal grain the 510, the 12nd flash memory crystal grain the 520, the 13rd flash memory crystal grain the 530, the 14th flash memory crystal grain 540 is all identical with the structure and the function mode of the 15th flash memory crystal grain 550, below only describes with the 0th flash memory crystal grain 400.
Please refer to Fig. 3, the 0th flash memory crystal grain 400 comprises storage area 402, first buffer zone 404 and second buffer zone 406.
Storage area 402 comprises a plurality of physical blocks and in order to storage data.Physical blocks is the least unit of erasing.That is each physical blocks contains the storer of being erased in the lump of minimal amount.Each physical blocks has several pages (page).In this exemplary embodiment, the page is the minimum unit of sequencing.In other words, the page is the minimum unit that writes data or reading of data.Each page generally includes user data field and redundant area.The user data field is in order to storage user's data, and redundant area is in order to data (for example, the bug check and the correcting code (Error Checking and Correcting Code, ECC Code) of stocking system.
What deserves to be mentioned is the 0th flash memory crystal grain 400, the 1st flash memory crystal grain 410, the 2nd flash memory crystal grain 420, the 3rd flash memory crystal grain 430, the 4th flash memory crystal grain 440, the 5th flash memory crystal grain 450, the 6th flash memory crystal grain 460, the 7th flash memory crystal grain 470, the 8th flash memory crystal grain 480, the 9th flash memory crystal grain 490, the 10th flash memory crystal grain 500, the 11st flash memory crystal grain 510, the 12nd flash memory crystal grain 520, the 13rd flash memory crystal grain 530, physical blocks in the 14th flash memory crystal grain 540 and the 15th flash memory crystal grain 550 can be that a plurality of solid elements carry out writing of data by memory management unit 208 groups, read and erase.Particularly each solid element is made up of the physical blocks in a plurality of flash memory crystal grain, so memory management unit 208 can use above-mentioned parallel model and interleaving mode to promote the speed of access.
Moreover, because the storer of flash memory only can turn to " 0 " from " 1 " program, the data in the physical blocks of must erasing earlier in the time of therefore will upgrading the data in the physical blocks.Yet writing of flash memory is to be unit with the page, is to be unit with the physical blocks and erase, so the physical blocks in the storage area 402 can be come storage data in the mode of rotating.Specifically, memory management unit 208 can logically be grouped into the solid element of grouping system region (system area), data field (data area), spare area (spare area) and replace district (replacement area), the solid element that wherein is grouped into system region is in order to store the relevant important information of flash memory, and be grouped into the solid element that replaces the district is the solid element that has damaged in data field or the spare area in order to replace, therefore under general access status, host computer system 290 is can't access system district and the solid element that replaces in the district.Write the data that instruction writes as for storing in the solid element that is grouped into the data field by main frame, and the solid element in the spare area is in order to the solid element in the replacement data district when the execution main frame writes instruction.For example, the main frame that receives host computer system 290 when flash memory 200 writes instruction and desire when upgrading a certain page of (or writing) data a certain solid element to the data field, memory management unit 208 can extract a solid element and effective legacy data in the solid element of desiring to be updated and the new data of desiring to write are write in the solid element that extracts from the spare area from the spare area, and the solid element that will write effective legacy data and new data logically is associated as the data field, and the solid element of desiring in the data field to be updated erased and logically is associated as the spare area.In order to allow host computer system 290 access successfully with the solid element of the mode storage data of rotating, flash memory 200 can provide logical address to host computer system 290.That is to say, flash memory 200 can by in logical address-physical address mapping table (logical address-physicaladdress mapping table), write down and more the enantiomorphic relationship between the solid element of new logical addresses and data field reflect rotating of solid element, so host computer system 290 only need write and flash memory 200 is understood and be read or write data according to logical address-physical address mapping table to the physical address of the solid element of institute's mapping at providing logical address.
First buffer zone 404 and second buffer zone 406 are the data that transmitted in order to temporary flash controller 204.As mentioned above, the process that writes data in the 0th flash memory crystal grain 400 comprises data transmission and two parts of data programization.In the part of data transmission, flash controller 204 meetings are with data transmission to the first buffer zone of desiring to write 404, and afterwards, the data of desiring to write can be moved to second buffer zone 406.And in the part of data programization, the data of desiring to write can write to storage area 402 from second buffer zone 406.At this, first buffer zone 404 is also referred to as data and gets (data cache) district soon, and second buffer zone 406 is also referred to as and gets buffering (cache buffer) district soon, what wherein first buffer zone 404 and second buffer zone 406 can be kept in a page respectively writes data with corresponding sequencing unit (that is the page).
Specifically, when memory management unit 208 receives main frame when writing instruction and needing to write data with writing data and write to the 0th flash memory crystal grain 400 from host computer system 290, memory management unit 208 can be assigned programmed instructions by flash interface unit 212 and data input/output bus 302, and the data of desiring to write in this programmed instructions are transferred to first buffer zone 404 from buffering storer 214, the data of desiring afterwards to write can be moved to second buffer zone 406 from first buffer zone 404, at last, data can be programmed into storage area 402 from second buffer zone 406.Particularly, in this exemplary embodiment, it is by " instruction W1 " that memory management unit 208 only can use, " physical address ", " write data " and programmed instructions that character string is formed such as " instructions W3 " is come the sequencing data, wherein memory management unit 208 is prepared the executive routine program by " instruction W1 " indication the 0th flash memory crystal grain 400, by the physical address of " physical address " indication the 0th flash memory crystal grain 400 desire sequencing, desire the data of sequencing and begin to carry out fast program fetchization (cache program) by " instruction W3 " indication the 0th flash memory crystal grain 400 by " writing data " indication the 0th flash memory crystal grain 400.At this, when " instruction W3 " in the service routine instruction, flash controller 204 can just receive the affirmation information of the 0th flash memory crystal grain 400 when data have been moved second buffer zone 406 from first buffer zone 404, and can handle next instruction.
For example, using the NCQ agreements to receive two continuous main frames from host computer system 290 at flash controller 204 writes instruction and needs in the example of two page executive routineizations of the 0th flash memory crystal grain 400, because the 0th flash memory crystal grain 400 has two buffer zones (promptly, first buffer zone 404 and second buffer zone 406), therefore the data that first main frame write instruction when the 0th flash memory crystal grain 400 are moved to second buffer zone 406 from first buffer zone 404, and first buffer zone 404 just can be eliminated and receive the data that second main frame writes instruction.Particularly, the 0th flash memory crystal grain 400 just first main frame is being write instruction write data from second buffer zone 406 sequencing during the storage area 402, what first buffer zone 404 can be responsible for receiving next programmed instructions writes data (that is, second main frame writes the data of instruction).That is to say, by using " instruction W3 " can make memory management unit 208 need not to wait for that the 0th flash memory crystal grain 400 finishes under the situation of sequencing that first main frame writes instruction, just can continue to handle second main frame and write instruction, and second main frame write writing in data transmission to the first buffer zone 404 of instruction.Therefore, the 0th flash memory crystal grain 400 can side by side be carried out first main frame and write the data programization that writes data of instruction and the data transmission that writes data of second host command, carries out the time that main frame writes instruction and shorten.
Fig. 4 A is that the illustrated flash controller of exemplary embodiment sees through the example schematic that the data input/output bus is assigned fast program fetch instruction according to the present invention, and Fig. 4 B is the time sequences figure according to flash chip illustrated in the instruction shown in Fig. 4 A.In the example of Fig. 4 A and Fig. 4 B, memory management unit 208 is to use the NCQ agreement to receive 3 main frames from host computer system 290 and writes instruction.At this, it is 3 continuous logical addresses that these 3 main frames write the instruction logical address desiring to write, and memory management unit 208 can produce according to the order of these a little logical addresses and assign instruction sequences, so that host computer system 290 is assigned these 3 main frames and is write instruction according to the instruction sequences of assigning that memory management unit 208 is produced, wherein the 1st main frame writes to instruct and comprises logical address of desiring to write and the data D1 that desires to write, the 2nd main frame writes instruction and comprises logical address of desiring to write and the data D2 that desires to write, the 3rd main frame writes instruction and comprises logical address of desiring to write and the data D3 that desires to write, and these 3 main frames to write that instruction desires in the logical address that writes be the physical blocks of mapping to the 0 flash memory crystal grain 400.
Please refer to Fig. 4 A and Fig. 4 B, assigning instruction sequences according to this when the memory management unit 208 of flash controller 204 receives after the 1st main frame that comes from host computer system 290 write instruction and the data desiring to write, memory management unit 208 can write among the data D1 that the logical address in the instruction desires with it to write to flash chip 220 according to the 1st main frame and assign by " instruct W1 ", " ADD1 ", fast program fetch instruction (the instruction CM1 shown in Fig. 4 A that character string such as " data D1 " and " instruction W3 " is formed, instruction CM2, transmission T1 and instruction CM3), the physical address of " ADD1 " representation program data wherein.Also be just to say, memory management unit 208 can send the physical address that main frame writes the logical address institute mapping in the instruction to the 0th flash memory crystal grain 400 (promptly according to logical address-physical address mapping table, instruction CM2), and with data D1 transfer to first buffer zone 404 (that is transmission T1).Afterwards, the 0th flash memory crystal grain 400 can be according to fast program fetch instruction (promptly, instruction CM3) data D1 is moved to second buffer zone 406 from first buffer zone 404, and data D1 is moved to second buffer zone 406 from first buffer zone 404 finishing, with data D1 from second buffer zone 406 sequencing to the storage area 402.Particularly, when the 0th flash memory crystal grain 400 begins to execute instruction CM3, the 0th flash memory crystal grain 400 can be in a busy condition, and data D1 is moved to second buffer zone 406 from first buffer zone 404 promptly to reply be (ready) state of awaiting orders (that is busy time B1) finishing.When the 0th flash memory crystal grain 400 is replied to armed state, memory management unit 208 can respond host computer system 290, from host computer system 290, receive the 2nd main frame and write instruction and data D2, and the 0th flash memory crystal grain 400 is assigned the fast program fetch instruction of being made up of " instruction W1 ", " ADD2 ", " data D2 " and character strings such as " instruction W3 " (the instruction CM4 shown in Fig. 4 A, instruction CM5, transmission T2 and instruction CM6) transfer to first buffer zone 404 (that is transmission T2) with the data D2 that the 2nd main frame write instruction.At this moment, the data programization of data D1 is side by side to carry out with the data transmission of data D2.That is to say, owing to have 2 buffer zones (promptly in the 0th flash memory crystal grain 400, first buffer zone 404 and second buffer zone 406), therefore see through to get soon to write to instruct the data of desiring to write are moved to second buffer zone 406 from first buffer zone 404, second buffer zone 406 is used for data programization to the storage area 402, and first buffer zone 406 just can continue to receive data from buffering storer 214.
Then, after transmission data D2, after the 0th flash memory crystal grain 400 is finished the data programization of data D1, the 0th flash memory crystal grain 400 can be moved data D2 to second buffer zone 406 from first buffer zone 404 according to instruction CM6, and data D2 is moved to second buffer zone 406 from first buffer zone 404 finishing, with data D2 from second buffer zone 406 sequencing to the storage area 402.When the 0th flash memory crystal grain 400 began to execute instruction CM6, the 0th flash memory crystal grain 400 can be in busy condition, and was armed state (that is busy time B2) finishing data D2 moved to second buffer zone 406 promptly to reply from first buffer zone 404.Similarly, when the 0th flash memory crystal grain 400 is replied to armed state, memory management unit 208 can respond host computer system 290, from host computer system 290, receive the 3rd main frame and write instruction and data D3, and the 0th flash memory crystal grain 400 is assigned the fast program fetch instruction of being made up of " instruction W1 ", " ADD3 ", " data D3 " and character strings such as " instruction W3 " (the instruction CM7 shown in Fig. 4 A, instruction CM8, transmission T3 and instruction CM9) transfer to first buffer zone 404 (that is transmission T3) with the data D3 that the 3rd main frame write instruction.
Then, after transmission data D3, after the 0th flash memory crystal grain 400 is finished the data programization of data D2, the 0th flash memory crystal grain 400 can be moved data D3 to second buffer zone 406 from first buffer zone 404 according to instruction CM9, and data D3 is moved to second buffer zone 406 from first buffer zone 404 finishing, with data D3 from second buffer zone 406 sequencing to the storage area 402.Similarly, when the 0th flash memory crystal grain 400 begins to execute instruction CM9, the 0th flash memory crystal grain 400 can be in busy condition, and is armed state (that is busy time B3) finishing data D3 moved to second buffer zone 406 promptly to reply from first buffer zone 404.
What deserves to be mentioned is, in memory management unit 208 receives to reply to the affirmation information of armed state from the 0th flash memory crystal grain 400, can comprise and get mode bit and actual busy condition position soon, wherein getting mode bit soon is to represent whether the 0th flash memory crystal grain 400 has been ready to receive the next one more and has write data, and actual busy condition position is to represent whether the 0th flash memory crystal grain 400 is in actual busy condition at present.Thus, whether flash controller 204 can judge rightly the 0th flash memory crystal grain 400 just in the sequencing data by the information in the confirmation.In the example of Fig. 4 A and Fig. 4 B, after busy time B3, though the 0th flash memory crystal grain 400 has been replied and has been ready, so, memory management unit 208 finishes the action of assigning programmed instructions because having write instruction to this All hosts that is received by the NCQ agreement, therefore memory management unit 208 can continue to confirm that sequencing that the 0th flash memory crystal grain 400 finished all data (promptly, memory management unit 208 can confirm that the 0th flash memory crystal grain 400 has been in non-actual busy condition) afterwards, reply the executing state that each main frame writes instruction to host computer system 290.
Fig. 5 is the illustrated process flow diagram of assigning programmed instructions of exemplary embodiment according to the present invention.
Please refer to Fig. 5, at first, flash memory 200 receives main frame and writes instruction from host computer system 290 in step S501.Specifically, in this exemplary embodiment, host computer system 290 is to use the NCQ agreement to transmit a plurality of main frames and writes instruction (writing instruction as described 2 main frames of Fig. 4 A).Therefore, flash memory 200 can receive host computer system 290 earlier and estimates that a plurality of main frames of assigning write instruction in step S501.
Then, memory management unit 208 can write the pairing logical address of instruction according to the main frame that is received and assign instruction sequences in step S503.Specifically, in the present embodiment, receive a plurality of main frames when writing instruction from host computer system 290 when memory management unit 208 uses the NCQ agreements, memory management unit 208 can write logical address in the instruction according to main frame and sort and write the order of instruction with the execution main frame of decision expection.What deserves to be mentioned is that in another exemplary embodiment of this example, memory management unit 208 also can not rearrange the order that received main frame writes instruction, produce and assign instruction sequences and assign order that main frame writes instruction originally with host computer system 290.
Memory management unit 208 can send the instruction sequences of assigning that is produced to host computer system in step S505.Afterwards, memory management unit 208 can then ground receive these a little main frames and writes and instruct the data that write that write instruction with corresponding these a little main frames according to assigning one of instruction sequences from host computer system 290 in step S507.
Afterwards, memory management unit 208 can be assigned fast program fetch instruction (for example, with " instruction W1 ", " physical address ", " writing data " and programmed instructions that character string is formed such as " instruction W3 ") to flash chip 220 in step S509.Afterwards, memory management unit 208 can wait and receive the affirmation information of flash chip 220 in step S511, and judges whether that in step S513 finishing the All hosts that host computer system 290 is desired to assign in step S501 writes instruction.If judge that in step S513 also not finishing the All hosts that host computer system 290 is desired to assign in step S501 writes when instructing, then execution in step S507 continuation receives next main frame and writes instruction.
If judge that in step S513 having finished the All hosts that host computer system 290 is desired to assign in step S501 writes when instructing, and judges in step S515 then whether flash chip 220 is in actual busy condition.If judging in step S515 that flash chip 220 is non-is in actual busy condition, execution in step S517 response host computer system 290 and finish the flow process of Fig. 5 then, otherwise, then continue execution in step S511.
Based on above-mentioned, receiving a plurality of main frames that come from host computer system 290 in use NCQ agreement writes in the example of instruction, memory management unit 208 can in the All hosts that this batch assigned according to the NCQ agreement write instruction all complete after, write the executing state (for example, whether the sequencing of generation mistake being arranged) of instruction to host computer system 290 repayment All hosts.Particularly, memory management unit 208 can wait flash chip 220 when the actual busy condition of carrying out last main frame and writing instruction is replied to armed state, just writes the executing state of instruction to host computer system 290 repayment All hosts.
In sum, the programmed instructions method of assigning of exemplary embodiment of the present invention only uses fast program fetch instruction to come the flash chip sequencing, can significantly shorten thus and carry out the time that main frame writes instruction.In addition, the programmed instructions method of assigning of exemplary embodiment of the present invention more utilizes the NCQ agreement to come move instruction between host computer system and flash memory, can avoid host computer system each main frame that can't judge rightly to write the actual executing state of instruction thus.Moreover, in above-mentioned exemplary embodiment, more utilize the NCQ agreement to come to write logical address that instruction desires to write and rearrange and assign the order that main frame writes instruction according to main frame, can more shorten thus and carry out main frame and write and instruct the required time.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (21)

1.一种对闪存下达程序化指令的方法，用于将来自于一主机系统的数据写入至一闪存芯片中，所述下达程序化指令的方法包括：1. A method for issuing programming instructions to flash memory, for writing data from a host system into a flash memory chip, the method for issuing programming instructions includes: 提供一闪存控制器；providing a flash memory controller; 由所述闪存控制器使用一原生指令排序协议从所述主机系统中接收多个主机写入指令；receiving, by the flash memory controller, a plurality of host write commands from the host system using a native command sequencing protocol; 由所述闪存控制器依据所述主机写入指令传送一下达指令顺序给所述主机系统；以及transmitting an instruction sequence to the host system according to the host write instruction by the flash memory controller; and 依据所述下达指令顺序从所述主机系统中依序地接收所述主机写入指令与对应所述主机写入指令的多个写入数据，并且分别地向所述闪存芯片下达一快取程序化指令以将所述写入数据写入至所述闪存芯片中。Sequentially receive the host write command and a plurality of write data corresponding to the host write command from the host system according to the order of issuing commands, and issue a cache program to the flash memory chip respectively write instructions to write the write data into the flash memory chip. 2.根据权利要求1所述的对闪存下达程序化指令的方法，其中由所述闪存控制器依据所述主机写入指令传送所述下达指令顺序给所述主机系统的步骤包括：2. The method for issuing programmed instructions to flash memory according to claim 1, wherein the step of sending the sequence of instructions issued by the flash memory controller to the host system according to the host write instruction comprises: 由所述闪存控制器依据所述主机系统下达所述主机写入指令的顺序来决定所述下达指令顺序；以及The order of issuing instructions is determined by the flash memory controller according to the order in which the host system issues the host write instructions; and 将所述下达指令顺序传送所述主机系统。and sequentially transmitting the issued instructions to the host system. 3.根据权利要求1所述的对闪存下达程序化指令的方法，其中由所述闪存控制器依据所述主机写入指令传送所述下达指令顺序给所述主机系统的步骤包括：3. The method for issuing programmed instructions to flash memory according to claim 1, wherein the step of sending the sequence of instructions issued by the flash memory controller to the host system according to the host write instruction comprises: 由所述闪存控制器依据对应所述主机写入指令的多个逻辑地址来决定所述下达指令顺序；以及The order of issuing commands is determined by the flash memory controller according to a plurality of logical addresses corresponding to the host write commands; and 将所述下达指令顺序传送所述主机系统。and sequentially transmitting the issued instructions to the host system. 4.根据权利要求1所述的对闪存下达程序化指令的方法，还包括：4. The method for issuing programming instructions to flash memory according to claim 1, further comprising: 在所述闪存控制器完成所有所述主机写入指令后传送对应所述主机写入指令的执行状态给所述主机系统。After the flash memory controller completes all the host write commands, it transmits the execution status corresponding to the host write commands to the host system. 5.根据权利要求4所述的对闪存下达程序化指令的方法，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则由所述闪存控制器从所述主机系统重新接收所述主机写入指令之中对应所述至少一程序化错误的主机写入指令与写入数据。5. The method for issuing programming instructions to flash memory according to claim 4, wherein when at least one programming error is included in the execution state corresponding to the host write instruction, then the The host system re-receives a host write command and write data corresponding to the at least one programming error among the host write commands. 6.根据权利要求4所述的对闪存下达程序化指令的方法，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则由所述闪存控制器从所述主机系统重新接收所有所述主机写入指令与所述写入数据。6. The method for issuing programming instructions to flash memory according to claim 4, wherein when at least one programming error is included in the execution state corresponding to the host write instruction, the The host system re-receives all the host write commands and the write data. 7.根据权利要求1所述的对闪存下达程序化指令的方法，其中所述闪存芯片包括一第一缓冲区、一第二缓冲区与一储存区，7. The method for issuing programming instructions to flash memory according to claim 1, wherein said flash memory chip comprises a first buffer area, a second buffer area and a storage area, 其中依据所述下达指令顺序从所述主机系统中依序地接收所述主机写入指令与对应所述主机写入指令的所述写入数据，并且分别地向所述闪存芯片下达所述快取程序化指令以将所述写入数据写入至所述闪存芯片中的步骤包括：Wherein, the host system write command and the write data corresponding to the host write command are sequentially received from the host system according to the order of issuing commands, and the flash memory chip is issued to the flash memory chip respectively. The step of fetching the programmed instruction to write the write data into the flash memory chip includes: 从所述主机系统中接收所述主机写入指令之中的一第一主机写入指令以及所述写入数据之中对应所述第一主机写入指令的一第一写入数据；receiving a first host write command among the host write commands and a first write data corresponding to the first host write command among the write data from the host system; 由所述闪存控制器向所述闪存芯片下达所述快取程序化指令将所述第一写入数据传输至所述第一缓冲区，其中所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区；The flash memory controller issues the cache programming instruction to the flash memory chip to transfer the first write data to the first buffer, wherein the first write data is transferred from the first buffer a region is moved to the second buffer and written from the second buffer to the storage region; 从所述主机系统中接收所述主机写入指令之中的一第二主机写入指令以及所述写入数据之中对应所述第二主机写入指令的一第二写入数据；以及receiving a second host write command among the host write commands and a second write data corresponding to the second host write command among the write data from the host system; and 由所述闪存控制器向所述闪存芯片下达所述快取程序化指令以将所述第二写入数据传输至所述第一缓冲区，其中所述第二写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区，The flash memory controller issues the cache programming instruction to the flash chip to transfer the second write data to the first buffer, wherein the second write data is transferred from the first a buffer is moved to the second buffer and written from the second buffer to the storage area, 其中当所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区之后，所述第二写入数据被传输至所述第一缓冲区中。Wherein after the first write data is moved from the first buffer to the second buffer, the second write data is transferred to the first buffer. 8.一种闪存控制器，用于将来自于一主机系统的数据写入至一闪存芯片中，所述闪存控制器包括：8. A flash memory controller for writing data from a host system into a flash memory chip, the flash memory controller comprising: 一微处理器单元；a microprocessor unit; 一缓冲存储器，电性连接至所述微处理器单元；a buffer memory electrically connected to the microprocessor unit; 一闪存接口单元，电性连接至所述微处理器单元，用以连接所述闪存芯片；A flash memory interface unit electrically connected to the microprocessor unit for connecting to the flash memory chip; 一主机接口单元，电性连接至所述微处理器单元，用以连接所述主机系统，其中所述主机接口单元支持一原生指令排序协定；以及a host interface unit electrically connected to the microprocessor unit for connecting to the host system, wherein the host interface unit supports a native instruction ordering protocol; and 一内存管理单元，电性连接至所述微处理器单元，用以通过所述主机接口单元使用所述原生指令排序协议从所述主机系统中接收多个主机写入指令，a memory management unit electrically connected to the microprocessor unit for receiving a plurality of host write commands from the host system through the host interface unit using the native instruction ordering protocol, 其中所述内存管理单元通过所述主机接口单元依据所述主机写入指令传送一下达指令顺序给所述主机系统，Wherein, the memory management unit transmits an instruction sequence to the host system through the host interface unit according to the host write command, 其中所述内存管理单元透过所述主机接口单元依据所述下达指令顺序从所述主机系统中依序地接收所述主机写入指令与对应所述主机写入指令的多个写入数据，并且分别地向所述闪存芯片下达一快取程序化指令以将所述写入数据写入至所述闪存芯片中。wherein the memory management unit sequentially receives the host write command and a plurality of write data corresponding to the host write command from the host system through the host interface unit according to the order of the issued commands, And issue a cache programming instruction to the flash memory chips respectively to write the write data into the flash memory chips. 9.根据权利要求8所述的闪存控制器，其中所述内存管理单元依据所述主机系统下达所述主机写入指令的顺序来决定所述下达指令顺序。9. The flash memory controller according to claim 8, wherein the memory management unit determines the command order according to the order in which the host system issues the host write commands. 10.根据权利要求8所述的闪存控制器，其中所述内存管理单元依据对应所述主机写入指令的多个逻辑地址来决定所述下达指令顺序。10. The flash memory controller according to claim 8, wherein the memory management unit determines the order of issuing commands according to a plurality of logical addresses corresponding to the host write commands. 11.根据权利要求8所述的闪存控制器，其中所述内存管理单元在完成所有所述主机写入指令后传送对应所述主机写入指令的执行状态给所述主机系统。11. The flash memory controller according to claim 8, wherein the memory management unit transmits an execution status corresponding to the host write command to the host system after completing all the host write commands. 12.根据权利要求11所述的闪存控制器，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则所述内存管理单元从所述主机系统中重新接收所述主机写入指令之中对应所述至少一程序化错误的主机写入指令与写入数据。12. The flash memory controller according to claim 11, wherein when at least one programming error is included in the execution state corresponding to the host write command, the memory management unit receives the A host write command and write data corresponding to the at least one programming error among the host write commands. 13.根据权利要求11所述的闪存控制器，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则所述内存管理单元从所述主机系统中重新接收所述主机写入指令与所述写入数据。13. The flash memory controller according to claim 11, wherein when at least one programming error is included in the execution state corresponding to the host write command, the memory management unit receives the The host write command and the write data. 14.根据权利要求11所述的闪存控制器，其中所述闪存芯片包括一第一缓冲区、一第二缓冲区与一储存区，14. The flash memory controller according to claim 11, wherein said flash memory chip comprises a first buffer area, a second buffer area and a storage area, 其中所述内存管理单元从所述主机系统中接收所述主机写入指令之中的一第一主机写入指令以及所述写入数据之中对应所述第一主机写入指令的一第一写入数据，The memory management unit receives a first host write command among the host write commands and a first host write command corresponding to the first host write command among the write data from the host system. data input, 其中所述内存管理单元向所述闪存芯片下达所述快取程序化指令将所述第一写入数据从所述缓冲存储器中传输至所述第一缓冲区，其中所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区，Wherein the memory management unit issues the cache programming instruction to the flash memory chip to transfer the first write data from the buffer memory to the first buffer, wherein the first write data moved from the first buffer to the second buffer and written from the second buffer to the storage area, 其中所述内存管理单元从所述主机系统中接收所述主机写入指令之中的一第二主机写入指令以及所述写入数据之中对应所述第二主机写入指令的一第二写入数据，Wherein the memory management unit receives a second host write command among the host write commands and a second host write command corresponding to the second host write command among the write data from the host system. data input, 其中所述内存管理单元向所述闪存芯片下达所述快取程序化指令以将所述第二写入数据从所述缓冲存储器中传输至所述第一缓冲区，其中所述第二写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区，以及Wherein the memory management unit issues the cache programming instruction to the flash memory chip to transfer the second write data from the buffer memory to the first buffer memory, wherein the second write data is moved from the first buffer to the second buffer and written from the second buffer to the storage area, and 其中当所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区之后，所述第二写入数据被传输至所述第一缓冲区中。Wherein after the first write data is moved from the first buffer to the second buffer, the second write data is transferred to the first buffer. 15.一种闪存储存系统，用于储存来自于一主机系统的数据，包括：15. A flash storage system for storing data from a host system, comprising: 一连接器，用以电性连接所述主机系统，其中所述连接器支持一原生指令排序协定；a connector for electrically connecting the host system, wherein the connector supports a native instruction ordering protocol; 一闪存芯片；以及a flash memory chip; and 一闪存控制器，电性连接至所述连接器与所述闪存芯片，用以通过所述连接器使用所述原生指令排序协议从所述主机系统中接收多个主机写入指令，a flash memory controller, electrically connected to the connector and the flash memory chip, for receiving a plurality of host write commands from the host system through the connector using the native instruction sequencing protocol, 其中所述闪存控制器依据所述主机写入指令传送一下达指令顺序给所述主机系统，wherein the flash memory controller transmits a sequence of instructions to the host system according to the host write command, 其中所述闪存控制器通过所述连接器依据所述下达指令顺序从所述主机系统中依序地接收所述主机写入指令与对应所述主机写入指令的多个写入数据，并且分别地向所述闪存芯片下达一快取程序化指令以将所述写入数据写入至所述闪存芯片中。Wherein the flash memory controller sequentially receives the host write command and a plurality of write data corresponding to the host write command from the host system through the connector according to the order of the issued commands, and respectively issue a cache programming instruction to the flash memory chip to write the write data into the flash memory chip. 16.根据权利要求15所述的闪存储存系统，其中所述闪存控制器依据所述主机系统下达所述主机写入指令的顺序来决定所述下达指令顺序。16. The flash memory storage system according to claim 15, wherein the flash memory controller determines the order of issuing the commands according to the order in which the host system issues the host write commands. 17.根据权利要求15所述的闪存储存系统，其中所述闪存控制器依据对应所述主机写入指令的多个逻辑地址来决定所述下达指令顺序。17. The flash memory storage system according to claim 15, wherein the flash memory controller determines the order of issuing commands according to a plurality of logical addresses corresponding to the host write commands. 18.根据权利要求15所述的闪存储存系统，其中所述闪存控制器在完成所有所述主机写入指令后传送对应所述主机写入指令的执行状态给所述主机系统。18. The flash memory storage system according to claim 15, wherein the flash memory controller transmits an execution status corresponding to the host write command to the host system after completing all the host write commands. 19.根据权利要求18所述的闪存储存系统，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则所述闪存控制器从所述主机系统中重新接收所述主机写入指令之中对应所述至少一程序化错误的主机写入指令与写入数据。19. The flash memory storage system according to claim 18, wherein when at least one programming error is included in the execution state corresponding to the host write command, the flash memory controller re-receives the written command from the host system. A host write command and write data corresponding to the at least one programming error among the host write commands. 20.根据权利要求18所述的闪存储存系统，其中当对应所述主机写入指令的执行状态之中包括至少一程序化错误时，则所述闪存控制器从所述主机系统中重新接收所述主机写入指令与所述写入数据。20. The flash memory storage system according to claim 18, wherein when at least one programming error is included in the execution status corresponding to the host write command, the flash memory controller re-receives the written command from the host system. The host write command and the write data. 21.根据权利要求15所述的闪存储存系统，其中所述闪存芯片包括一第一缓冲区、一第二缓冲区与一储存区，21. The flash memory storage system according to claim 15, wherein said flash memory chip comprises a first buffer zone, a second buffer zone and a storage area, 其中所述闪存控制器从所述主机系统中接收所述主机写入指令之中的一第一主机写入指令以及所述写入数据之中对应所述第一主机写入指令的一第一写入数据，Wherein the flash memory controller receives a first host write command among the host write commands and a first host write command corresponding to the first host write command among the write data from the host system. data input, 其中所述闪存控制器向所述闪存芯片下达所述快取程序化指令将所述第一写入数据从所述缓冲存储器中传输至所述第一缓冲区，其中所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区，Wherein the flash memory controller issues the cache programming instruction to the flash chip to transfer the first write data from the buffer memory to the first buffer, wherein the first write data moved from the first buffer to the second buffer and written from the second buffer to the storage area, 其中所述闪存控制器从所述主机系统中接收所述主机写入指令之中的一第二主机写入指令以及所述写入数据之中对应所述第二主机写入指令的一第二写入数据，Wherein the flash memory controller receives a second host write command among the host write commands and a second host write command corresponding to the second host write command among the write data from the host system. data input, 其中所述闪存控制器向所述闪存芯片下达所述快取程序化指令以将所述第二写入数据从所述缓冲存储器中传输至所述第一缓冲区，其中所述第二写入数据从所述第一缓冲区被搬移至所述第二缓冲区并且从所述第二缓冲区被写入至所述储存区，以及Wherein the flash memory controller issues the cache programming instruction to the flash memory chip to transfer the second write data from the buffer memory to the first buffer memory, wherein the second write data is moved from the first buffer to the second buffer and written from the second buffer to the storage area, and 其中当所述第一写入数据从所述第一缓冲区被搬移至所述第二缓冲区之后，所述第二写入数据被传输至所述第一缓冲区中。Wherein after the first write data is moved from the first buffer to the second buffer, the second write data is transferred to the first buffer.
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