CN102024689B - Method for improving aligning performance in polysilicon grid making technology - Google Patents
Method for improving aligning performance in polysilicon grid making technology Download PDFInfo
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- CN102024689B CN102024689B CN200910195579A CN200910195579A CN102024689B CN 102024689 B CN102024689 B CN 102024689B CN 200910195579 A CN200910195579 A CN 200910195579A CN 200910195579 A CN200910195579 A CN 200910195579A CN 102024689 B CN102024689 B CN 102024689B
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- Prior art keywords
- alignment mark
- zero
- semiconductor substrate
- polysilicon
- manufacture craft
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 47
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000012545 processing Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Abstract
A method for improving aligning performance in polysilicon grid making technology comprises the steps of: providing a semiconductor substrate, wherein the semiconductor substrate has a zero-aligning mark, a gate oxide layer and a polysilicon layer used for making polysilicon grid; forming a mask pattern on the polysilicon layer, wherein an opening of the mask pattern is correspond to the zero-aligning mark; etching the polysilicon layer, the gate oxide layer to the zero-aligning mark successively; removing the mask pattern; and aligning the zero-aligning mark on the semiconductor substrate with an aligning mark on the mask board. The method avoids the imperfect alignment phenomenon caused by unclear zero-aligning mark, and improves the accuracy of alignment.
Description
Technical field
The present invention relates to semiconductor device and making field, relate in particular to and improve the method for aiming at performance in the polysilicon gate manufacture craft.
Background technology
Along with the development of semiconductor technology, the area of semiconductor chip is more and more littler, and the live width in the chip is also constantly dwindled, so the test that the semiconductor technology ability receives is also increasing, and the control of the precision of technology and technology variation also becomes more important.In the technology of making semiconductor chip; Most important technical process is exactly photoetching; Said photoetching promptly is through series of steps such as aligning, exposure, etchings mask pattern to be transferred to the technical process on the wafer, so the quality of photoetching process can directly have influence on the performance of final formation chip.
In photoetching process, correctly to transfer on the wafer for making mask pattern, critical step is with mask and wafer alignment, promptly calculates the position of mask with respect to wafer, to satisfy the requirement of lithographic accuracy.When characteristic size more and more hour, also increasingly high to the requirement of lithographic accuracy and consequent requirement to alignment precision.
In order to accomplish the effect of aligning; As shown in Figure 1, before carrying out photoetching process, all can in wafer 10, etch some patterns earlier, as zero alignment mark (Zero Mark) 12; Follow-up carry out resist exposure each time before, need to use zero alignment mark to carry out aiming at of mask and wafer.
For EEPROM (Electrically Erasable Programmable ReadOnly Memory; EEPROM), in the manufacturing process of polysilicon gate, often generation can't be distinguished the zero alignment mark that is positioned on the wafer; Cause wafer to be return; Perhaps zero alignment mark is fuzzyyer, though do not return, yet in manufacture craft; Also be difficult to mask on zero alignment mark aim at the situation generation of the accuracy decline that causes aiming at fully.
Summary of the invention
The problem that the present invention solves provides a kind of method of aiming at performance in the polysilicon gate manufacture craft that improves, in order to improve the alignment accuracy in the polysilicon manufacture craft.
For addressing the above problem; The present invention provides a kind of method of aiming at performance in the polysilicon gate manufacture craft that improves; Comprise: Semiconductor substrate is provided, has zero alignment mark on the described Semiconductor substrate, gate oxide and the polysilicon layer that is used for the manufacturing polycrystalline silicon grid; On said polysilicon layer, form mask pattern, the opening of said mask pattern is corresponding with zero alignment mark; The said polysilicon layer of etching, gate oxide are to zero alignment mark successively; Remove said mask pattern; Alignment mark on the mask of the zero alignment mark of said Semiconductor substrate and manufacturing polycrystalline silicon grid is aimed at.
Compared with prior art, such scheme has the following advantages:
Aim at the method for performance in the raising polysilicon gate manufacture craft according to the invention; Before the aligning that carries out the polysilicon gate making, through etching technics the zero alignment mark on the described Semiconductor substrate is come out earlier, carry out the Alignment Process of the mask of Semiconductor substrate and manufacturing polycrystalline silicon grid subsequently again; Avoided zero alignment mark unintelligible; The phenomenon that can't aim at has fully improved the accuracy of aiming at, thereby has improved the yield of product.
Description of drawings
Fig. 1 is the sketch map of existing zero alignment mark;
Fig. 2 is the alignment quality of zero alignment mark in each processing step of prior art;
Fig. 3 is that shape of the present invention is improved the embodiment flow chart of aiming at the method for performance in the polysilicon gate manufacture craft;
Fig. 4 to Fig. 8 is that shape of the present invention is improved the sketch map of aiming at the method for performance in the polysilicon gate manufacture craft;
Fig. 9 is the alignment quality of zero alignment mark in each processing step of the present invention.
Embodiment
Inventor of the present invention discovers that in the manufacture craft of semiconductor device, only the zero alignment mark on the Semiconductor substrate is unintelligible in the technology that forms polysilicon gate; Therefore, the accuracy rate of aligning is very low, shown in accompanying drawing 2; Be the alignment quality of zero alignment mark in each processing step, the abscissa among the figure is represented the alignment quality of zero alignment mark in each different step, and the AA among the figure representes the active area manufacture craft; P1 representes the described polysilicon gate manufacture craft of present embodiment, and P2 representes to form the polysilicon gate manufacture craft behind the control gate, and CT representes the manufacture craft of contact; M1 representes the manufacture craft of ground floor metal interconnecting wires; V1 representes the manufacture craft of first dielectric layer on first interconnection line, and M2 representes the manufacture craft of second layer metal interconnection line, and V2 representes the manufacture craft of second dielectric layer on second interconnection line; M3 representes the manufacture craft of three layer metal interconnect line; V3 representes the manufacture craft of the 3rd dielectric layer on the 3rd interconnection line, and ordinate is represented the quality of zero alignment mark, and said data adopt following mode to obtain: through the zero alignment mark of scanning device scanning wafer; The conversion of signals of scanning device being obtained through instrument is a digital signal; With the fiducial value of the signal strength signal intensity of the zero alignment mark that detects and setting relatively, the numerical value that obtains is the zero alignment mark quality of corresponding processing step, therefore, it typically is a percent value, as 40 promptly representing 40% in the accompanying drawing.The accuracy rate of as can be seen from Figure 2, aiming in the technology of formation polysilicon gate is minimum.
Therefore, present embodiment provides a kind of method of aiming at performance in the polysilicon gate manufacture craft that improves, and has improved the accuracy of aiming at.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Fig. 3 is that the present invention improves the embodiment flow chart of aiming at the method for performance in the polysilicon gate manufacture craft, and said method comprises:
Step S101 provides Semiconductor substrate, the polysilicon layer that has zero alignment mark and be used for the manufacturing polycrystalline silicon grid on the described Semiconductor substrate; As shown in Figure 4, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 materials are silicon for example, germanium, silicon-on-insulators etc. are formed with isolation structure in the described Semiconductor substrate, N trap, P trap etc.
In the both sides of said Semiconductor substrate, also form odd alignment mark 110, said zero alignment mark is 2, is positioned at relative 2 sides of Semiconductor substrate.Described zero alignment key pattern is confirmed according to the technological design needs.On Semiconductor substrate 100, be formed with gate oxide 120 and polysilicon layer 130 successively.Described gate oxide material is silica etc. for example.
Step S102, as shown in Figure 5, on said polysilicon layer 130, form mask pattern 140, the opening of said mask pattern 140 is corresponding with zero alignment mark 110 positions;
In one embodiment; Described mask pattern 140 adopts following method to form; On described polysilicon layer 130, adopt spin coating proceeding to form photoresist layer; Afterwards, on described photoresist, form opening through exposure, developing process, the position of said opening is all corresponding with size with the position of zero alignment mark 110 with size.
Step S103, as shown in Figure 6, the said polysilicon layer 130 of etching, gate oxide 120 is to exposing zero alignment mark 110; Described etching technics is a prior art well known to those skilled in the art, repeats no more at this.
Step S104, as shown in Figure 7, remove said mask pattern 140; The technology of removing said mask pattern for example is cineration technics.
To step S104, the zero alignment mark that is positioned under the polysilicon layer 130 is come out fully through above-mentioned steps S101, and the zero alignment mark of having avoided possibly causing in the prior art is unclear, can't accurately carry out the defective of Alignment Process.
Step S105, as shown in Figure 8, the zero alignment mark 210 on the mask 200 of the zero alignment mark 110 of said Semiconductor substrate 100 and manufacturing polycrystalline silicon grid is aimed at.Because the zero alignment mark 110 on the Semiconductor substrate 100 has come out fully, therefore, can aim at fully with the zero alignment mark 210 on the mask.
Shown in accompanying drawing 9; After the described method of employing present embodiment, the alignment quality of zero alignment mark in each processing step, the abscissa among the figure is represented the alignment quality of zero alignment mark in each different step; AA among the figure representes the active area manufacture craft; P1 representes the described polysilicon gate manufacture craft of present embodiment, and P2 representes to form the polysilicon gate manufacture craft behind the control gate, and SAB representes to make the processing step of metal silicide; The accuracy rate of as can be seen from the figure, aiming in the technology of formation polysilicon gate is minimum.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (3)
1. one kind is improved the method for aiming at performance in the polysilicon gate manufacture craft, comprising:
Semiconductor substrate is provided, has zero alignment mark and gate oxide on the described Semiconductor substrate, be used for the polysilicon layer of manufacturing polycrystalline silicon grid;
On said polysilicon layer, form mask pattern, the opening of said mask pattern is corresponding with zero alignment mark;
The said polysilicon layer of etching, gate oxide are to zero alignment mark successively;
Remove said mask pattern;
Alignment mark on the mask of the zero alignment mark of said Semiconductor substrate and manufacturing polycrystalline silicon grid is aimed at.
2. according to the method for aiming at performance in the said raising polysilicon gate of claim 1 manufacture craft, it is characterized in that said gate oxide material is a silica.
3. according to the method for aiming at performance in the said raising polysilicon gate of claim 1 manufacture craft, it is characterized in that said zero alignment mark is 2, is positioned at relative 2 sides of Semiconductor substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910195579A CN102024689B (en) | 2009-09-11 | 2009-09-11 | Method for improving aligning performance in polysilicon grid making technology |
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| CN200910195579A CN102024689B (en) | 2009-09-11 | 2009-09-11 | Method for improving aligning performance in polysilicon grid making technology |
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| CN102024689A CN102024689A (en) | 2011-04-20 |
| CN102024689B true CN102024689B (en) | 2012-09-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105244261B (en) * | 2014-06-18 | 2019-06-28 | 上海华力微电子有限公司 | The preparation method of semiconductor devices |
| CN111415859B (en) * | 2020-03-30 | 2025-05-27 | 北京华镁钛科技有限公司 | A method for manufacturing a glass through hole with precise alignment of substrate |
| CN113013236A (en) * | 2021-02-22 | 2021-06-22 | 上海华力集成电路制造有限公司 | Monitoring method for forming process of nitrogen-doped gate oxide layer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573151B1 (en) * | 2000-08-22 | 2003-06-03 | Advanced Micro Devices, Inc. | Method of forming zero marks |
| CN1506768A (en) * | 2002-09-20 | 2004-06-23 | Asml | Alignment systems and methods for lithography systems |
| TW200741948A (en) * | 2006-04-24 | 2007-11-01 | Taiwan Semiconductor Mfg Co Ltd | Method and system for wafer backside alignment |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6573151B1 (en) * | 2000-08-22 | 2003-06-03 | Advanced Micro Devices, Inc. | Method of forming zero marks |
| CN1506768A (en) * | 2002-09-20 | 2004-06-23 | Asml | Alignment systems and methods for lithography systems |
| TW200741948A (en) * | 2006-04-24 | 2007-11-01 | Taiwan Semiconductor Mfg Co Ltd | Method and system for wafer backside alignment |
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| CN102024689A (en) | 2011-04-20 |
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