CN102006160B - Jitter Generator for Dithered Clock Signals - Google Patents

Abstract

The invention provides a jitter generator for generating a jitter clock signal, which comprises a jitter control signal generator and a jitter clock generator. The jitter control signal generator is used for selecting a digital code from a plurality of candidate digital codes at different time points and respectively outputting a plurality of selected different digital codes; the jitter clock generator is coupled to the jitter control signal generator and is used for generating the jitter clock signal, wherein the jitter clock generator dynamically adjusts the jitter clock signal according to the plurality of different digital codes respectively.

Description

Jitter Generator for Dithered Clock Signals

The present invention is a divisional application of the following patent application: application number: 200710160159.X, application date: December 24, 2007, invention name: jitter generator for generating jitter clock signals

technical field

The present invention relates to a jitter generator (jitter generator), in particular to a jitter generator capable of generating a jitter clock signal to be applied to a built-in self-test (built-in-self-test, BIST) in a chip .

Background technique

In digital communication systems, the receiver's tolerance to timing jitter is an important parameter to measure the performance of the entire system, especially in high-speed communication systems. The so-called time jitter refers to when the position where the data or clock signal rising edge/falling edge should appear is shifted (that is, the phase shift), which may cause the receiver's bit error rate (bit error rate, BER) rises. Known solutions usually use a clock and data recovery (CDR) circuit in the receiver to reduce the impact of jitter on the receiver.

Therefore, how to test the jitter tolerance of the receiver has always been an important issue. A common test architecture uses a jitter generator to generate a frequency signal containing time jitter, and inputs a series of random test data bits to a D-type flip-flop (D-type flip-flop), and the D-type flip-flop The operation is triggered by the frequency signal with time jitter; thus, the D-type flip-flop can output a series of data bits with time jitter. Then, the data bit stream with time jitter is input to the receiver, and the output of the receiver is compared with the input test data bit stream to know the jitter tolerance of the receiver.

However, a good jitter generator must be able to control the frequency of the jitter and the magnitude of the jitter amplitude; where the jitter amplitude refers to the magnitude of the phase shift of the data or clock signal, and the jitter frequency refers to the number of times the phase shift occurs . Although there are ready-made test instruments on the market to meet this requirement, such test instruments are expensive and are not conducive to batch testing. Another alternative is to use a signal generator and a mixer to modulate a frequency signal with jitter, and this method is relatively low in cost.

Contents of the invention

The purpose of the present invention is to provide a jitter generator that can be used in the built-in self-test in the chip, so as to save the machine cost during batch testing.

An embodiment of the present invention provides a jitter generator for generating a jittered clock signal, which includes a jitter control signal generator and a jitter clock generator. The jitter control signal generator is used to select a digital code from multiple candidate digital codes at different time points, and output the selected multiple different digital codes respectively; and the jitter clock generator is coupled to the jitter control signal generator A device is used to generate the jitter clock signal, wherein the jitter clock generator dynamically adjusts the jitter clock signal according to the plurality of different digital codes, wherein the clock locking circuit is a delay locked loop, and the delay locked loop includes : a phase comparator, used to generate a comparison result based on the clock input signal and the clock feedback signal; a control signal generator, coupled to the phase comparator, used to generate a control signal based on the comparison result; and a delay circuit, coupled to In the phase comparator and the control signal generator, the clock input signal is delayed to generate the clock feedback signal, including: a first delay module, used to generate the jitter clock signal at the second node according to the first delay amount control signal and a second delay module, coupled between the first node and the second node, used to generate the clock feedback signal at the first node according to the second delay amount control signal, wherein a phase adjustment circuit according to the The control signal and the dithering control signal are used to generate the first and second delay amount control signals respectively.

Another embodiment of the present invention provides a jitter generator for generating a jitter clock signal, including a jitter control signal generator and a jitter clock generator. The jitter control signal generator is used to generate a jitter control signal; and the jitter clock generator is coupled to the jitter control signal generator, which includes a clock locking circuit, which is used to execute a clock according to a clock input signal and a clock feedback signal. Clock locking operation, to generate the clock feedback signal at the first node and generate the jitter clock signal at the second node, wherein the clock locking circuit is a phase-locked loop, and the phase-locked loop includes: a phase comparator for according to The clock input signal and the clock feedback signal generate a comparison result; a control signal generator, coupled to the phase comparator, is used to generate a control signal according to the comparison result; and a ring oscillator, coupled to the phase comparator and the phase comparator. The control signal generator is used to generate the clock feedback signal, including: an inversion module; a first delay module, used to generate the jitter clock signal at the second node according to the first delay amount control signal; and a second delay module , coupled between the first node and the second node, used to generate the clock feedback signal at the first node according to the second delay amount control signal, wherein a phase adjustment circuit is based on the control signal and the jitter control signal to generate the first and second delay amount control signals respectively.

Description of drawings

Fig. 1 is the functional block diagram of the jitter generator of the first embodiment of the present invention;

FIG. 2 is a schematic diagram of a digital code output by the jitter control signal generator shown in FIG. 1;

FIG. 3 is a schematic diagram of a jitter clock signal output by the jitter generator shown in FIG. 1;

4 is a schematic diagram of multiple clock output signals with the same frequency but different phases output by the multi-phase clock generator shown in FIG. 1;

5 is a functional block diagram of a jitter generator according to a second embodiment of the present invention;

6 is a functional block diagram of a jitter generator according to a third embodiment of the present invention;

Fig. 7 is a functional block diagram of the phase interpolation delay-locked loop shown in Fig. 6;

FIG. 8 is a functional block diagram of a jitter generator according to a fourth embodiment of the present invention;

Fig. 9 is a functional block diagram of the phase interpolation phase-locked loop shown in Fig. 8;

Fig. 10 is a functional block diagram of the jitter generator of the fifth embodiment of the present invention; and

FIG. 11 is a functional block diagram of a jitter generator according to a sixth embodiment of the present invention.

Detailed ways

Please refer to FIG. 1 , which is a functional block diagram of a jitter generator 10 according to a first embodiment of the present invention. The jitter generator 10 includes a jitter clock generator 100 and a jitter control signal generator 110 , and the jitter clock generator 100 includes a multi-phase clock generator 102 and a phase selector 104 . The jitter control signal generator 110 is used to select at least one group of digital codes from multiple sets of candidate digital codes at different time points, and output the selected multiple different digital codes respectively. In this embodiment, the jitter control signal generator 110 is implemented by a direct digital frequency synthesizer (DDFS) 112 . The direct digital frequency synthesizer 112 is a component for generating digitized arbitrary waveforms. The operation principle of the direct digital frequency synthesizer is known to those skilled in the art, so the related details will not be repeated here. According to the jitter frequency control signal J _freq and the jitter amplitude control signal J _amp , the direct digital frequency synthesizer 112 can be controlled to sequentially generate the required digital waveform signal, and the digital waveform signal is used as the digital code SEL (as shown in FIG. 2 ). The jitter clock generator 100 is used to generate the jitter clock signal J _out and dynamically adjust the jitter clock signal J _out according to the digital code SEL (as shown in FIG. 3 ). In this embodiment, the jitter clock generator 100 is composed of a multi-phase clock generator 102 and a phase selector 104; wherein, the multi-phase clock generator 102 generates multiple candidate clock output signals CLK _out according to the clock input signal CLK _{in (n)} , wherein the multiple clock output signals CLK _out(n) are clock signals with the same frequency but different phases (in this embodiment, n=0～3, that is, four clock signals with different phases can be generated ,As shown in Figure 4). In this embodiment, the multi-phase clock generator 102 is realized by a multi-phase phase-locked loop (multi-phase phase locked loop, multi-phase PLL) 106. Please note that this is only for demonstration purposes, not for this purpose. The constraint of the invention is that any circuit that can generate multiple clock signals with the same frequency but different phases can be used to realize the desired multi-phase clock generator 102 . The phase selector 104 is coupled to the multi-phase clock generator 102 and the phase selection control signal generator 110, and is used to output the signal CLK _out(n) from n candidate clocks according to the digital code SEL output by the jitter control signal generator 110 A specific clock output signal is selected to generate the dithered clock signal J _out . Since the direct digital frequency synthesizer 112 will generate digital signals with different amplitudes at different time points, that is, output different digital codes SEL; in this way, the phase of the clock output signal selected by the phase selector 104 at each time point is also are not the same, so a frequency signal J _out with time jitter will be generated (as shown in FIG. 3 ).

Please refer to FIG. 5 , which is a functional block diagram of the jitter generator 20 according to the second embodiment of the present invention. The jitter generator 20 includes a jitter clock generator 200 and a jitter control signal generator 210, wherein the jitter clock generator 200 includes a multi-phase clock generator 202 and a phase selector 204, and the jitter control signal generator 210 includes A direct digital frequency synthesizer 212 and a decoder 214 . The circuit structure of Figure 5 is roughly the same as that of Figure 1, the only difference from Figure 1 is that the jitter control signal generator 210 in Figure 5 has an additional decoder 214; the decoder 214 is used for direct digital frequency The digital waveform signal output by the synthesizer 212 is decoded to be converted into a digital code SEL.

Please note that the implementations of the jitter control signal generators disclosed in the first embodiment and the second embodiment of the present invention are only illustrative examples, and are not intended as limitations of the present invention. Therefore, any implementation that can generate the jitter control signal according to the jitter frequency control signal J _freq and the jitter amplitude control signal J _amp falls within the scope of the present invention.

Please refer to FIG. 6 , which is a functional block diagram of the jitter generator 30 according to the third embodiment of the present invention. The jitter generator 30 includes a jitter control signal generator 320 for generating a jitter control signal J _ctl and a jitter clock generator 300 for generating a jitter clock signal J _out according to the jitter control signal J _ctl . In this embodiment, the jitter control signal generator 320 includes a direct digital frequency synthesizer 322 and a digital/analog converter (digital/analog converter, DAC) 324 . The jitter frequency control signal J _freq and the jitter amplitude control signal J _amp can control the direct digital frequency synthesizer 322 to synthesize the required digital waveform signal, and the digital waveform signal will be converted by the digital/analog converter 324 to output a The jitter control signal J _ctl of continuous waveform, that is, the jitter control signal J _ctl is an analog signal.

In this embodiment, the jitter clock generator 300 is implemented by a phase interpolated delay locked loop (PI DLL) 400 . Please refer to FIG. 7 , which is a functional block diagram of the phase interpolation DLL 400 shown in FIG. 6 . The phase interpolation DLL 400 is a clock locking circuit for performing a clock locking operation according to the clock input signal CLK _in and the clock feedback signal CLK _fb to generate the clock feedback signal CLK _fb and the dithered clock signal J _out . The phase interpolation delay locked loop 400 includes: a phase comparator 402, which is used to generate a comparison result according to the clock input signal CLK _in and the clock feedback signal CLK _fb ; a control signal generator 404, coupled to the phase comparator 402, for Generate a control signal CTL according to the comparison result; and a delay circuit 406 , coupled to the phase comparator 402 and the control signal generator 404 , is used to process the clock input signal CLK _in to generate a clock feedback signal CLK _fb . As shown in the figure, the delay circuit 406 includes: a first delay module 408, which is used to generate a jitter clock signal J _out according to the first delay control signal CTL ₁ ; and a second delay module 410, which is used to control the signal CTL according to the second delay. The signal CTL ₂ is controlled to generate the clock feedback signal CLK _fb . In this embodiment, each delay module is implemented by a voltage control delay line (VCDL). Since the details of using a delay-locked loop to perform a clock-locked operation are known to those skilled in the art, they are not repeated here. repeat. It should be noted that the difference between the first delay control signal CTL ₁ and the second delay control signal CTL ₂ in this embodiment is that one of the delay control signals is obtained by adding the control signal CTL and the jitter control signal J _ctl , and another delay amount control signal is obtained by subtracting the control signal CTL from the jitter control signal J _ctl , so that the effect of adding one and subtracting one equals the effect of the combined effect of the first delay module 408 and the second delay module 410 It is equivalent to a delay module that controls the amount of delay according to the control signal CTL, so the two delay modules in the delay circuit 406 will not change the original clock-locked operation function of the phase interpolation delay-locked loop, and the final feedback signal CLK _fb The phase will still be the same as the phase of the clock input signal CLK _in through the clock locking operation. However, the dithered clock signal J _out output from between the first delay module 408 and the second delay module 410 has the same frequency as the feedback signal CLK _fb (ie, the clock input signal CLK _in ) but a different phase. Since the jitter control signal J _ctl is a continuous waveform signal whose amplitude is constantly changing, the delay generated by the first delay module 408 will constantly change, that is, the phase difference between the jitter clock signal J _out and the clock input signal CLK _in will continue to change. Therefore, the jitter clock signal J _out has the effect of time jitter. Please also note that in an embodiment, the control signal generator 404 may be implemented by a charge pump and a low-pass filter.

Please refer to FIG. 8 , which is a functional block diagram of a jitter generator 50 according to a fourth embodiment of the present invention. Please compare with FIG. 6 , the structures of the two are roughly the same, the only difference is that the jitter clock generator 500 in FIG. 8 is realized by a phase interpolated phase-locked loop (PI PLL) 600 . Please refer to FIG. 9 , which is a functional block diagram of the phase interpolation PLL 600 shown in FIG. 8 . The phase interpolation phase-locked loop 600 is also a clock-locked circuit, including: a phase comparator 602, which is used to generate a comparison result according to the clock input signal CLK _in and the clock feedback signal CLK _fb0 ; a control signal generator 604, coupled to The phase comparator 602 is used to generate the control signal CTL according to the comparison result; the ring oscillator 606 is coupled to the phase comparator 602 and the control signal generator 604 to generate the clock feedback signal CLK _fb ; and the frequency divider 614 is used for To divide the frequency of the clock feedback signal CLK _fb , and output the clock feedback signal CLK _fb0 so that the frequencies of the two clock feedback signals have a multiple relationship, and the clock input signal CLK _in and the clock feedback signal CLK _fb0 also have a multiple relationship. In addition, the ring oscillator 606 includes: an inversion module 612; a first delay module 608, used to generate a jitter clock signal J _out according to the first delay amount control signal _CTL 1; The control signal CTL ₂ is delayed by an amount to generate the clock feedback signal CLK _fb . In this embodiment, each delay module is implemented by a voltage control delay line (VCDL). Since the details of using a phase-locked loop to perform a clock-locked operation are already known to those skilled in the art, it will be described here No longer. It should be noted that the difference between the first delay control signal CTL ₁ and the second delay control signal CTL ₂ in this embodiment is that one of the delay control signals is obtained by adding the control signal CTL and the jitter control signal J _ctl , and another delay control signal is obtained by subtracting the control signal CTL from the jitter control signal J _ctl , so that the effect of adding one and subtracting one equals the effect of the combined effect of the first delay module 608 and the second delay module 610 It is equivalent to a delay module that controls the delay amount according to the control signal CTL, so the two delay modules in the delay circuit 606 will not change the clock-locked operation function of the phase interpolation PLL. However, the jitter clock signal J _out output from the first delay module 608 and the second delay module 610 has the same frequency as the feedback signal CLK _fb but a different phase. Since the jitter control signal J _ctl is a continuous waveform signal whose amplitude is constantly changing, the delay generated by the first delay module 608 will constantly change, that is, the phase difference between the jitter clock signal J _out and the clock input signal CLK _in will continue to change. Therefore, the jitter clock signal J _out has the effect of time jitter.

In addition, in the third embodiment of the present invention, the jitter size that can be generated by using the phase interpolation DLL is plus or minus 0.5 unit intervals (unit interval, UI); this is because when the delay locked in FIG. 7 When the loop 400 locks the phase of the clock input signal CLK _in , the delay amount of the rear clock feedback signal CLK _fb via the two-stage voltage-controlled delay line will be exactly one cycle different from the clock input signal CLK _in . As shown in Figure 9, in the fourth embodiment of the present invention, the phase interpolation delay-locked loop of the third embodiment of the present invention is replaced by a phase interpolation phase-locked loop, although the function is the same, the jitter amplitude generated by it can be Not limited by a unit interval; this is because there is an additional frequency divider 614 in the phase interpolation phase-locked loop 600, so that the frequency of the clock input signal CLK _in can be an integer multiple of the clock feedback signal CLK _fb , so the jitter clock signal The magnitude of the jitter generated by J _out can exceed one unit interval.

Please refer to FIG. 10 , which is a functional block diagram of a jitter generator 70 according to a fifth embodiment of the present invention. Please compare with FIG. 6 , the structures of the two are roughly the same, the only difference is that the dithering control signal generator 720 in FIG. 10 is composed of an oscillator 722 and a variable gain amplifier 724 . The oscillator 722 is used to generate the oscillating signal SW according to the jitter frequency control signal J _freq , and the variable gain amplifier 724 is coupled to the oscillator 722 for converting the oscillating signal SW into a jitter control signal J according to the jitter amplitude control signal J _{amp ctl} . The jitter control signal J _ctl generated in this embodiment is the same as the jitter control signal J _ctl generated in the third embodiment in FIG. Magnitude signal with time jitter.

Please refer to FIG. 11 , which is a functional block diagram of a jitter generator 80 according to a sixth embodiment of the present invention. Please compare with FIG. 10 , the structures of the two are roughly the same, the only difference is that the jitter clock generator 800 in FIG. 11 is realized by a phase interpolation PLL 810 . Since the phase interpolation PLL 810 in FIG. 11 is exactly the same as the phase interpolation PLL 600 in FIG. 9 , and the jitter control signal generator 820 is completely the same as the jitter control signal generator 720 in FIG. This will not repeat them.

The dithering circuit disclosed by the invention is beneficial to be implemented in the chip to achieve the purpose of built-in self-test, thereby saving machine cost during batch testing. If the circuit of the transmitter is contained in the chip, then the method of the present invention can be used to share part of the hardware circuit with the transmitter (such as a multi-phase phase-locked loop, a phase interpolation delay-locked loop, or a phase interpolation phase-locked loop) when building in self-test. ring) to further save chip area and reduce production costs.

The above descriptions are only examples of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (8)

1. shake generator that is used for producing dithering clock signal comprises:

Jitter control signal generator is used for producing dither control signal; And

The jitter clock generator, be coupled to this jitter control signal generator, comprise the clock lock circuit, be used for carrying out the clock lock operation according to clock input signal and clock feedback signal, to produce this clock feedback signal in first node and to produce this dithering clock signal in Section Point

Wherein this clock lock circuit is a delay lock loop, and this delay lock loop comprises:

Phase comparator is used for producing comparative result according to this clock input signal and this clock feedback signal;

The control signal generator is coupled to this phase comparator, is used for producing control signal according to this comparative result; And

Delay circuit is coupled to this phase comparator and this control signal generator, postpones this clock input signal to produce this clock feedback signal, comprising:

First Postponement module is used for producing this dithering clock signal according to the first retardation control signal in this Section Point; And

Second Postponement module, be coupled between this first node and this Section Point, be used for the foundation second retardation control signal to produce this clock feedback signal in this first node, and wherein a phase-adjusting circuit produces this first, second retardation control signal respectively according to this control signal and this dither control signal.

2. shake generator as claimed in claim 1, wherein this phase-adjusting circuit adds that with this control signal this dither control signal produces in this first, second retardation control signal, and this control signal is deducted this dither control signal produces in this first, second retardation control signal another.

3. shake generator as claimed in claim 1, wherein this jitter control signal generator comprises:

Direct Digital Frequency Synthesizers is used for producing a digital code according to chattering frequency control signal and jitter amplitude control signal; And

Digital/analog converter is coupled to this Direct Digital Frequency Synthesizers and this phase-adjusting circuit, is used for converting this digital code to this dither control signal.

4. shake generator as claimed in claim 1, wherein this jitter control signal generator comprises:

Oscillator is used for according to the chattering frequency control signal to produce oscillator signal; And

Variable gain amplifier is coupled to this oscillator, is used for converting this oscillator signal to this dither control signal according to the jitter amplitude control signal.

5. shake generator that is used for producing dithering clock signal comprises:

Jitter control signal generator is used for producing dither control signal; And

The jitter clock generator, be coupled to this jitter control signal generator, comprise the clock lock circuit, be used for carrying out the clock lock operation according to clock input signal and clock feedback signal, to produce this clock feedback signal in first node and to produce this dithering clock signal in Section Point

Wherein this clock lock circuit is a phase-locked loop, and this phase-locked loop comprises:

Phase comparator is used for producing comparative result according to this clock input signal and this clock feedback signal;

The control signal generator is coupled to this phase comparator, is used for producing control signal according to this comparative result; And

Ring oscillator is coupled to this phase comparator and this control signal generator, is used for producing this clock feedback signal, comprising:

Anti-phase module;

First Postponement module is used for according to the first retardation control signal to produce this dithering clock signal in this Section Point; And

Second Postponement module, be coupled between this first node and this Section Point, be used for the foundation second retardation control signal to produce this clock feedback signal in this first node, and wherein a phase-adjusting circuit produces this first, second retardation control signal respectively according to this control signal and this dither control signal.

6. shake generator as claimed in claim 5, wherein this phase-adjusting circuit adds that with this control signal this dither control signal produces in this first, second retardation control signal, and this control signal is deducted this dither control signal produces in this first, second retardation control signal another.

7. shake generator as claimed in claim 5, wherein this jitter control signal generator comprises:

Direct Digital Frequency Synthesizers is used for producing a digital code according to chattering frequency control signal and jitter amplitude control signal; And

Digital/analog converter is coupled to this Direct Digital Frequency Synthesizers and this phase-adjusting circuit, is used for converting this digital code to this dither control signal.

8. shake generator as claimed in claim 5, wherein this jitter control signal generator comprises:

Oscillator is used for according to the chattering frequency control signal to produce oscillator signal; And

Variable gain amplifier is coupled to this oscillator, is used for converting this oscillator signal to this dither control signal according to the jitter amplitude control signal.

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