CN102005468A - Terminal of power semiconductor and manufacturing method of terminal - Google Patents
Terminal of power semiconductor and manufacturing method of terminal Download PDFInfo
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Abstract
本发明提供一种功率半导体器件的终端及其制作方法，所述功率半导体器件包括第一导电类型的第一半导体层，第一半导体层具有含有掺杂第二导电类型的阱区的有源区，所述终端位于第一半导体层中，其中，所述终端具有与有源区邻接的掺杂有第二导电类型的结终端扩展区，所述结终端扩展区的掺杂厚度随距有源区的距离增大而加大，所述结终端扩展区的掺杂浓度随距有源区的距离增大而减小。在本发明终端结构中，所述结终端扩展区的电阻率随着掺杂浓度的减小而增加，单位长度内的横截面积随掺杂厚度的增加而增加，缓解了由于掺杂浓度的递减引起的电阻的上升，从而使终端的电势分布均匀，有效的避免在局部出现过早击穿，提高了终端可承受的耐压。
The present invention provides a terminal of a power semiconductor device and a manufacturing method thereof. The power semiconductor device includes a first semiconductor layer of a first conductivity type, and the first semiconductor layer has an active region containing a well region doped with a second conductivity type. , the terminal is located in the first semiconductor layer, wherein the terminal has a junction terminal extension region doped with the second conductivity type adjacent to the active region, and the doping thickness of the junction termination extension region varies with the active region The doping concentration of the junction terminal extension region decreases with increasing distance from the active region. In the terminal structure of the present invention, the resistivity of the junction terminal extension region increases as the doping concentration decreases, and the cross-sectional area per unit length increases as the doping thickness increases, alleviating the The rise of the resistance caused by the decrease makes the potential distribution of the terminal uniform, effectively avoids premature breakdown in the local area, and improves the withstand voltage of the terminal.
Description
Technical field
The present invention relates to the terminal structure of semiconductor device, relate in particular to terminal of a kind of power semiconductor and preparation method thereof.
Background technology
Because the existence of knot buckling phenomenon, often there is the phenomenon of premature breakdown in the terminal of power semiconductor.Therefore, terminal protection structure is designed to power semiconductor, the important content of high-power device optimization design especially.
Current, more common terminal protection structure has a ring, field plate, knot termination extension district (JTE), oblique angle, groove or the like.Oblique angle, groove structure are realized difficulty, and it is big that the field is encircled, field plate consumes area, reduce the silicon chip utilance, and it is bigger influenced by interface charge.Fig. 4 is a kind of terminal structure schematic diagram in the prior art.With reference to Fig. 4, a kind of JTE structure 2 has been proposed in the prior art, the main knot 101 of described JTE structure 2 in active area 1 doping content far away more is low more, and junction depth is also shallow more.Show that by analysis junction depth that successively decreases and the doping content of successively decreasing effect simultaneously can cause the resistance of JTE outwards to increase rapidly along main knot, thereby be unfavorable for effective transmission of electromotive force; cause sharing too high electromotive force near the main knot; electric field is too high, thereby premature breakdown does not reach the purpose of effective protection.
Summary of the invention
The technical problem that the present invention mainly solves is the purpose that the terminal structure of power semiconductor does not reach effective protection in the prior art, thereby a kind of terminal of power semiconductor is provided.
Technical scheme provided by the invention:
A kind of terminal of power semiconductor, described power semiconductor comprises first semiconductor layer of first conduction type, first semiconductor layer has the active area of the well region that contains second conduction type that mixes, described terminal is arranged in first semiconductor layer, wherein, described terminal has the knot termination extension district that is doped with second conduction type with the active area adjacency, the doping thickness in described knot termination extension district strengthens with the distance increase of distance active area, and the doping content in described knot termination extension district reduces with the distance increase of distance active area.
The present invention also provides a kind of manufacture method of terminal of power semiconductor.
A kind of manufacture method of terminal of power semiconductor, comprise a Semiconductor substrate that possesses first conduction type is provided, described Semiconductor substrate has first area that is used to form active area, it is characterized in that, comprise that also second area that will be used to form described terminal on the described Semiconductor substrate is divided into the plurality of sections zone, and described plurality of sections zone according to the distance first area by carrying out diffusion of impurities successively as far as near order, the described terminal that possesses second conduction type with formation, wherein, the time of described diffusion of impurities reduces successively, and the employed diffuse source concentration of diffusion of impurities increases successively.
The beneficial effect of technical solution of the present invention:
In terminal structure of the present invention, the resistivity in described knot termination extension district increases along with reducing of doping content, cross-sectional area in the unit length increases with the increase of doping thickness, this shows, the doping thickness of Zeng Jiaing causes that the cross-sectional area in the unit length increases gradually, thereby alleviated because the rising of the resistance that reduces to cause of doping content, make resistance terminal being evenly distributed everywhere, thereby make the Potential Distributing of terminal even, the distribution of electric field is also along with being tending towards even, effectively avoid premature breakdown occurring, improved withstand voltage that terminal can bear in the part.
Description of drawings
Fig. 1 is the vertical view of the power semiconductor with terminal of the embodiment of the invention;
Fig. 2 has a semi-conductive profile of terminal power for first embodiment of the invention, and this figure dissects gained along the AB line among Fig. 1;
Fig. 3 is the profile of the power semiconductor with terminal of second embodiment of the invention, and this figure dissects gained along the AB line among Fig. 1;
Fig. 4 is a kind of terminal structure schematic diagram in the prior art;
Fig. 5 is the simulation result puncture voltage comparison diagram of embodiments of the invention terminal structure and prior art.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Power semiconductor of the present invention comprises power diode, ambipolar isolated-gate field effect transistor (IGFET) (IGBT), metal oxide isolated-gate field effect transistor (IGFET) (MOS), thyristor devices such as (SCR).
According to majority carrier decision in the semiconductor, determine semi-conductive type.If the majority carrier of first conduction type is the hole, then first conduction type is the P type, and heavily doped first conduction type is the P+ type, and the lightly doped first kind is the P-type; If the majority carrier of first conduction type is an electronics, then first conduction type is the N type, and heavily doped first conduction type is the N+ type, and the lightly doped first kind is the N-type.The majority carrier of second conduction type is second type of carrier, and the majority carrier of first conduction type is a first kind charge carrier.When first conduction type was the N type, then second conduction type was the P type.
The terminal of a kind of power semiconductor of the embodiment of the invention, described power semiconductor comprises first semiconductor layer of first conduction type, first semiconductor layer has the active area of the well region that contains second conduction type that mixes, described terminal is arranged in first semiconductor layer, wherein, described terminal has the knot termination extension district that is doped with second conduction type with the active area adjacency, the doping thickness in described knot termination extension district strengthens with the distance increase of distance active area, and the doping content in described knot termination extension district reduces with the distance increase of distance active area.
Further, the doping thickness in described knot termination extension district increases with the distance of distance active area and strengthens continuously gradually, and the doping content in described knot termination extension district increases with the distance of distance active area and reduces continuously gradually.
Further, the doping thickness in described knot termination extension district increases and interruption increasing gradually with the distance of distance active area, and the doping content in described knot termination extension district reduced with being interrupted gradually apart from increasing of distance active area.
Further, described terminal also has the channel cutoff ring of first conduction type, and described channel cutoff ring is positioned at a distance outside the described knot termination extension district.
Further, the distance between described channel cutoff ring and the termination extension district is between 100 microns to 400 microns.
Further, the varied in thickness in described knot termination extension district can be even variation, also can be non-uniform change.The doping content in described knot termination extension district changes can be even variation, also can be non-uniform change.Described even variation is: when tying 101 variable in distance one regular length along with distance is main, variable quantity (for example doping content or doping thickness) also changes a fixed amount.The electric field that helps terminal so evenly distributes.
Fig. 1 is the vertical view of the power semiconductor with terminal of the embodiment of the invention.With reference to Fig. 1, the embodiment of the invention have the terminal power semiconductor device comprise active area 1 that the well region (following abbreviation well region) that contains second conduction type (for example P type) that mixes is arranged on first semiconductor layer that is formed at first conduction type (for example N type) and with the terminal 2 of active area 1 adjacency, described terminal 2 has the knot termination extension district that is doped with second conduction type with the active area adjacency, the doping thickness in described knot termination extension district strengthens with the distance increase of distance active area, and the doping content in described knot termination extension district reduces with the distance increase of distance active area.The PN junction that forms between the well region that active area 1 middle distance terminal 2 is nearest and first semiconductor layer is called main knot 101.Main knot 101 has been born the main puncture voltage of power semiconductor, so need to increase terminal to share puncture voltage, to reduce the breakdown possibility of power semiconductor in power semiconductor.
Computing formula according to resistance:
Wherein ρ is the resistivity of material, and S is that cross-sectional area, the l of material is the length of material.In this terminal structure, described knot termination extension district resistivity increases along with reducing of doping content, cross-sectional area in the unit length increases with the increase of doping thickness, this shows, the doping thickness of Zeng Jiaing causes that the cross-sectional area in the unit length increases gradually, thereby alleviated the rising of the resistance that causes owing to successively decreasing of doping content to a certain extent, make resistance in knot termination extension district being evenly distributed everywhere, thereby make the Potential Distributing of terminal even, the distribution of electric field is also along with being tending towards even, effectively avoid premature breakdown occurring, improved withstand voltage that terminal can bear in the part.
Embodiment one
Fig. 2 is the profile with power semiconductor of first embodiment of the invention terminal, and this figure dissects gained along the AB line among Fig. 1.In the present embodiment, first conduction type is the N type, second conduction type is the P type, terminal has the knot termination extension district (JTE structure) that is doped with second conduction type (P type), the doping thickness in described knot termination extension district with the distance of distance active area increase strengthen, the doping content in described knot termination extension district increases with the distance of distance active area and reducing.The doping thickness in described knot termination extension district, promptly the degree of depth of JTE structure is called for short the JTE junction depth.As shown in Figure 2, the power semiconductor with first embodiment of the invention terminal comprises the active area 1 with heavily doped P+ type well region, and with the main P type JTE structure 210 of tying 101 adjacency of active area 1, described first semiconductor layer is lightly doped N-tagma 3.The terminal of present embodiment also comprises heavily doped N+ channel cutoff ring 220, described N+ channel cutoff ring 220 is positioned at outside the P type JTE structure 210 and with P type JTE structure 210 and keeps certain distances, this distance is between 100 microns to 400 microns, preferred 200 microns, be oppositely arranged with active area 1, be used to prevent semiconductor device surface generation transoid and contamination ion that can the collection semiconductor device surface, make device more stable.
The characteristics of the present embodiment are, described P type JTE structure 210 is suitable with the junction depth of main knot 101 near near the JTE junction depths the main knot 101, and are the darkest at the JTE junction depth away from an end of main knot 101, and the JTE junction depth of this P type JTE structure 210 be evenly variation continuously; This P type JTE structure 210 is higher near the region doping concentration of main knot 101, and lower away from the region doping concentration of main knot 101, and doping content evenly changes continuously.Describedly evenly be changed to continuously: along with the distance of the main knot 101 of distance changes a regular length continuously, variable quantity (for example doping content or doping thickness) also changes a fixed amount continuously.P type JTE structure 210 is between 3 microns to 10 microns near the JTE junction depth of main knot 101, and preferred 5 microns, doping content is 1E16/cm
3To 1E19/cm
3Between, preferred 1E17/cm
3P type JTE structure 210 is between 8 microns to 20 microns away from the JTE junction depth of main knot 101 1 ends, and preferred 10 microns, doping content is 1E14/cm
3To 1E16/cm
3Between, preferred 1E15/cm
3
The beneficial effect of present embodiment:
The introducing of JTE terminal structure generally can be introduced one second peak value electric field in the termination environment.
The employing doping content of the embodiment of the invention is successively decreased, and the JTE structure that the JTE junction depth increases progressively makes the inner formation of JTE barrier Distribution, thereby makes the distribution of current potential and electric field more even.Because the JTE junction depth increases progressively, near improving main knot 101, also increased the radius of curvature of JTE structure outermost end depletion layer in the depletion layer curvature, effectively reduced second peak value electric field, improve withstand voltage level, and since the position that peak value electric field occurs away from the surface, interfacial state and interface charge are able to effective inhibition to withstand voltage influence, slowed down the withstand voltage degeneration that high pressure and high temperature cause, do not need by improving whole doping content, sacrifice maximum withstand voltage and guarantee the reliability of device, effective optimization this trade-off relation.
Embodiment two
Fig. 3 is the profile with power semiconductor of second embodiment of the invention terminal, and this figure dissects gained along the AB line among Fig. 1.As shown in Figure 3, the difference of the technical scheme of the technical scheme of present embodiment and first embodiment is: P type JTE structure 210 is divided into the plurality of sections zone, the JTE junction depth is identical in every section zone, but the JTE junction depth of all sections is deepened gradually, simultaneously, doping content during P type JTE structure 210 also satisfies every section is identical, and the doping content in main knot 101 distances that section zone far away more is low more.P type JTE structure 210 in the present embodiment is divided into 4 sections, is respectively first section 211, second sections 212, the 3rd sections 213, the 4th sections 214, the JTE junction depth of all sections be increase progressively, doping content be successively decrease and every section in doping content be identical.This P type JTE structure 210 is higher near first section 211 doping content of main knot 101 and be lower than main knot 101, second section 212 doping content be lower than first section 211, the three sections 213 mix be lower than second section 212, the four sections 214 mix and be lower than the 3rd section 213, and in each section, doping content is identical; Be that doping content is a Gradient distribution, local concentration is even, and overall density is successively decreased.
The beneficial effect of present embodiment:
Can know that according to semi-conductive theory the depletion layer peak electric field appears at the knot knee.The JTE junction depth that increases progressively gradually increases the radius of curvature of finishing, thereby makes knot crooked away from the surface, effectively avoided the influence of surface charge to peak value electric field, even under harsh and unforgiving environments such as HTHP, withstand voltage level obvious degeneration can not occur yet, has improved the reliability of device.
And as can be known according to the computing formula of above-mentioned resistance, in the structure of termination environment of the present invention, the resistivity of JTE structure increases along with reducing of doping content, cross-sectional area in the unit length increases with the increase of doping thickness, this shows, the junction depth of Zeng Jiaing causes that the cross-sectional area in the unit length increases gradually, thereby alleviated the rising of the resistance that causes owing to successively decreasing of doping content to a certain extent, make resistance terminal being evenly distributed everywhere, thereby make the Potential Distributing of termination environment even, the distribution of electric field also evenly effectively avoids premature breakdown occurring in the part along with being tending towards, and improved withstand voltage that terminal can bear.
Fig. 5 is the simulation result puncture voltage comparison diagram of terminal structure of the present invention and prior art.The tagma of two kinds of terminal structures of this emulation (i.e. first semiconductor layer) doping content equates that the terminal overall size is 300um.With reference to Fig. 5,100 pairing terminals are JTE structure in the prior art among the figure, the shared 150um that is of a size of of JTE structure doped region, and the darkest JTE junction depth is 11 microns, and the most shallow JTE junction depth is 5 microns, and average JTE junction depth is 7.5 microns, and withstand voltage is 1310V; 200 pairing terminals are the JTE structure of the embodiment of the invention, the shared 150um that is of a size of of JTE structure, arranging of the distributing order of described JTE junction depth and 100 pairing prior aries is just the opposite, at the JTE junction depth away from the position of active area is 11 microns, junction depth and active area near active area are suitable, be 5um, withstand voltage is 1575V.As we can see from the figure, the withstand voltage of the terminal of the doped structure of the embodiment of the invention is higher than the withstand voltage of prior art.
In conjunction with the structure of Fig. 3, the terminal manufacture method of the power semiconductor of the embodiment of the invention is described:
At first, provide low-doped first conduction type (for example N-type) Semiconductor substrate, be used to form active area and terminal; Described first area is used to form active area, and described second area is used to form described terminal; Secondly, described second area is divided into some terminal areas, in the present embodiment, be divided into four sections, be respectively the first section termination zone 211, the second section termination zone 212, the 3rd section termination zone 213, the 4th section termination zone 214 successively, the described first section termination zone 211 is nearest from first area, and described the 4th section termination zone 214 from first area farthest.Once more, earlier make its formation be doped with second type of carrier (for example hole) the 4th section termination zone 214 to carry out diffusion of impurities from first area that section termination zone farthest, handle successively by the order that draws near from first area distance, make formation be doped with second type of carrier (for example hole), the first section termination zone 211 to carry out diffusion of impurities from that nearest section termination zone of first area at last, thereby form terminal.
The step that every section zone is handled is as follows: utilize existing photoetching technique that Semiconductor substrate is handled earlier, make the terminal area that needs diffusion exposed, all the other zones are covered by photoresist, inject again the method for diffusion of impurities by impurity source diffusion or first ion, form second conduction type (for example P type) terminal area of certain JTE junction depth and doping content.The impurity source diffusion promptly directly contacts with the object of impurity source with the band diffusion, because the concentration gradient relation, impurity just enters in the object.Because being doped with the 4th terminal area 214 of second type of carrier (for example hole) just forms before in the 3rd terminal area 213 that making is doped with second type of carrier (for example hole), so, when impurity spreads in the 3rd terminal area 213, impurity in the 4th terminal area 214 also can further spread, the time that impurity spreads in the 3rd terminal area 213 will be lacked than the time that impurity spreads in the 4th terminal area 214, so guaranteed that the JTE junction depth of the 4th terminal 214 is more amid a sharp increase than the JTE junction depth of the 3rd terminal area 213, handle the 3rd terminal area 213 by using than the 4th terminal area 214 higher impurity source concentration or bigger ion implantation dosages, that is to say, the concentration of the diffuse source that the diffusion of impurities of the 3rd terminal area 213 is used is higher, guarantees the height of the doping content of the 3rd terminal area 213 than the 4th terminal area 214; In like manner, profit second terminal area 212 and first terminal area 211 that makes that use the same method meets the demands.Like this, having the JTE junction depth increases progressively the novel JTE terminal structure that successively decreases with doping content and is achieved.
Certainly utilize said method, those skilled in the art can obtain the manufacture method of JTE junction depth and doping content continually varying JTE structure without creative work, because as long as the zone that is used to make terminal on the substrate is divided into the more terminal area of number, then as long as the quantity of terminal area reaches some when (being about 50 zones), the variation of JTE junction depth of Zhi Zuoing and doping content just is tending towards continuous according to the method described above.
Impurity source in the described impurity source diffusion technology can be solid, also can be liquid, can also be gas.
The power semiconductor that the manufacture method of utilizing JTE structure of the present invention obtains in conjunction with the manufacture method of power semiconductor in the prior art with terminal, because junction depth increases progressively, near improving main knot in the depletion layer curvature, also increased simultaneously the radius of curvature of JTE terminal outermost end depletion layer, effectively reduced second peak value electric field, improve withstand voltage level, and since the position that peak value electric field occurs away from the surface, interfacial state and interface charge are able to effective inhibition to withstand voltage influence, slowed down the withstand voltage degeneration that high pressure and high temperature cause, do not need by improving whole doping content, sacrifice maximum withstand voltage and guarantee the reliability of device, effective optimization this trade-off relation.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.All any modifications of being done within the spirit and principles in the present invention, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
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Cited By (7)
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| CN102768947A (en) * | 2012-07-20 | 2012-11-07 | 深圳深爱半导体股份有限公司 | Power semiconductor device with junction termination extension structure and manufacturing method of junction termination extension structure |
| CN103855200A (en) * | 2012-11-30 | 2014-06-11 | 上海联星电子有限公司 | Semiconductor device and manufacturing method thereof |
| WO2014086011A1 (en) * | 2012-12-06 | 2014-06-12 | 中国科学院微电子研究所 | Rb-igbt manufacturing method |
| US20220157951A1 (en) * | 2020-11-17 | 2022-05-19 | Hamza Yilmaz | High voltage edge termination structure for power semicondcutor devices and manufacturing method thereof |
| CN115295545A (en) * | 2022-08-11 | 2022-11-04 | 江苏捷捷微电子股份有限公司 | Unidirectional silicon controlled rectifier and manufacturing method thereof |
| CN117790536A (en) * | 2023-12-26 | 2024-03-29 | 南京芯干线科技有限公司 | Junction terminal structure, preparation method thereof and semiconductor device |
| CN119342875A (en) * | 2024-12-20 | 2025-01-21 | 北京怀柔实验室 | Terminal structure of semiconductor power device and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1635397A1 (en) * | 2004-09-14 | 2006-03-15 | STMicroelectronics S.r.l. | Integrated high voltage power device having an edge termination of enhanced effectiveness |
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| CN102768947A (en) * | 2012-07-20 | 2012-11-07 | 深圳深爱半导体股份有限公司 | Power semiconductor device with junction termination extension structure and manufacturing method of junction termination extension structure |
| CN102768947B (en) * | 2012-07-20 | 2015-03-18 | 深圳深爱半导体股份有限公司 | Power semiconductor device with junction termination extension structure and manufacturing method of junction termination extension structure |
| CN103855200A (en) * | 2012-11-30 | 2014-06-11 | 上海联星电子有限公司 | Semiconductor device and manufacturing method thereof |
| CN103855200B (en) * | 2012-11-30 | 2016-11-23 | 上海联星电子有限公司 | A kind of semiconductor device and its manufacturing method |
| WO2014086011A1 (en) * | 2012-12-06 | 2014-06-12 | 中国科学院微电子研究所 | Rb-igbt manufacturing method |
| US20220157951A1 (en) * | 2020-11-17 | 2022-05-19 | Hamza Yilmaz | High voltage edge termination structure for power semicondcutor devices and manufacturing method thereof |
| US12087831B2 (en) | 2020-11-17 | 2024-09-10 | Taiwan Semiconductor Co., Ltd. | High voltage edge termination structure for power semiconductor devices and manufacturing method thereof |
| CN115295545A (en) * | 2022-08-11 | 2022-11-04 | 江苏捷捷微电子股份有限公司 | Unidirectional silicon controlled rectifier and manufacturing method thereof |
| CN115295545B (en) * | 2022-08-11 | 2025-07-18 | 江苏捷捷微电子股份有限公司 | A unidirectional thyristor and a method for manufacturing the same |
| CN117790536A (en) * | 2023-12-26 | 2024-03-29 | 南京芯干线科技有限公司 | Junction terminal structure, preparation method thereof and semiconductor device |
| CN117790536B (en) * | 2023-12-26 | 2025-03-18 | 南京芯干线科技有限公司 | A junction terminal structure and preparation method thereof, and semiconductor device |
| CN119342875A (en) * | 2024-12-20 | 2025-01-21 | 北京怀柔实验室 | Terminal structure of semiconductor power device and manufacturing method thereof |
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Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |