CN102004711B - A Single Interrupt Real-time Data Transmission Method Based on FPGA - Google Patents

Abstract

The invention relates to a data transmission method, in particular to a real-time data transmission method in which the data of a plurality of asynchronous data sources is buffered through single-interrupt data transmission equipment based on an FPGA (Field Programmable Gate Array) and then sent to an upper computer, belonging to the technical field of real-time signal processing. The real-time data transmission method comprises the following steps of: firstly selecting an appropriate interrupt cycle according to a conditional inequality of data transmission without data loss; then establishing data buffers in the FPGA, and establishing writing state registers of the data buffers; and then generating a cyclic interrupt signal according to half full and full signals sent by the data buffers, wherein the upper computer triggers an interrupt service routine by responding to the cyclic interrupt signal so as to achieve the purpose of real-time continuous transmission. Compared with a multi-interrupt source trigger mode, the real-time data transmission method reduces the programming and debugging complexity of software and hardware and enhances the reliability of a system; in addition, the magnitude of data quantity generated by each interrupt is relatively stable, therefore the data is more convenient for intensive batch transmission and post processing.

Description

A Single Interrupt Real-time Data Transmission Method Based on FPGA

technical field

The invention relates to a data transmission method, in particular to a real-time data transmission method that caches data from multiple asynchronous data sources through an FPGA-based single-interruption data transmission device, and then sends them to a host computer, belonging to the technical field of real-time signal processing .

Background technique

Modern communication systems such as military communication and reconnaissance systems often need to quickly search, intercept, measure, analyze, identify, monitor and other operations on various non-cooperative signals. mission accomplished. High-speed real-time digital signal processing architectures such as FPGA+DSP/MCU/CPU are very common in digital signal processing systems that require high real-time performance such as communications and radar systems. Therefore, the efficient and reliable transmission of high-speed data between FPGA and DSP/MCU/CPU and other modules is particularly important. As a parallel high-speed hard-wire logic device that implements complex digital algorithm logic, FPGA is usually used as a high-speed data source. As a relatively low-speed but flexible digital signal analysis and processing device, DSP/MCU/CPU is often at the data receiving end (or host computer). The characteristics of the data flow generated by the FPGA are divided into the following situations: uninterrupted continuous data flow, aperiodic burst data flow, periodic burst data flow, etc., and various data flows may have different data rates.

For these asynchronous data sources with different rates, to complete real-time continuous data transmission, the traditional method is to generate multiple different interrupt signals for different asynchronous data sources to the host computer to complete real-time continuous data transmission. However, the software and hardware programming and debugging based on multiple interrupt sources are relatively complicated, and it is easy to cause various system stability and reliability problems such as system crashes.

Invention content:

The present invention mainly aims at the shortcomings of complex software and hardware programming and debugging and poor reliability of the traditional multi-interrupt source real-time data transmission method, and proposes a single-interrupt real-time continuous data transmission method based on FPGA. This method not only reduces the number of interruptions, Moreover, the interrupt interval has a fixed period, which improves the efficiency of data transmission and simplifies the complexity of design.

The FPGA-based single interrupt real-time data transmission method is to construct n data buffers (B1, B2, ..., Bn) corresponding to various asynchronous data sources on the FPGA first, and then adopt a suitable single interrupt source and n The write status pointer of each data buffer is used to assist in the completion of real-time continuous data transmission. First, one of the n asynchronous data sources should be selected to establish a data buffer using the method of ping-pong buffering; secondly, a non-ping-pong ordinary data buffer should be established for the remaining n-1 asynchronous data sources. The data buffer creates a write status pointer register, wherein the write status pointer of the non-ping-pong buffer is the current write operation address value, and the status pointer of the ping-pong buffer can only use 0 or 1 to represent the upper/lower data being written Buffer half area; then, establish a periodic single interrupt source data transmission trigger mechanism for the only ping-pong buffer; finally, complete the host computer interrupt service subroutine programming, it should be noted that in the host computer program also need to establish a The write status pointer of the data buffer stores the variable to save the data buffer write status pointer obtained at the time of the last interrupt.

It may be assumed that the B1 buffer is selected as a ping-pong buffer, that is, the B1 buffer is divided into upper and lower half areas B1L and B1H with the same storage depth, and the half-full and full-full signals are used to generate interrupt signals. Assuming that the write data rate of the B1 data buffer is W1 byte/s, and the data storage capacity of the B1 ping-pong buffer B1L or B1H is S0 bytes, then the required storage time T1 for the B1L or B1H buffer to be full is:

T1=S1/W1

Obviously, T1 is also the interrupt period of the interrupt source. The time required for the host computer to read the B1L or B1H buffer data is:

T1'=S1/R

Among them, R is the read data rate of the upper computer, and the unit is also byte/second.

In this way, the amount of data stored in the B2 buffer within the T1 time is S2=W2×T1, W2 is the write data rate; and the time required for the host computer to read the data is: T2'=S2/R. In the same way, the amount of data stored in the Bk data buffer (k=1, 2, ..., n) in the T1 time is Sk=Wk*T1, and the time required for the upper computer to read all the data is Tk'=Sk/ R, where k=1, 2, . . . , n. It should be noted that the size of each data buffer must be greater than or equal to twice its data storage capacity Sk (k=1, 2, . . . , n) within T1.

The time Ts required for the host computer to completely read all the data stored in the B1, B2, ..., Bn buffers within the time T1 is:

Ts=T1'+T2'+...+Tn'

=S1/R+S2/R+...+Sn/R

=(W1+W2+...+Wn)×I1/R

Obviously, to ensure real-time continuous data transmission without data loss, the following conditions need to be met:

Ts<T1,

That is, the conditions need to be met:

W1+W2+...+Wn<R

An FPGA-based single interrupt real-time continuous data transmission method, comprising the following specific steps:

Step 1: Choose an appropriate interrupt period

According to the write data rate Wk of each asynchronous data source 1, 2, ..., n and the read data rate R of the host computer, using the real-time continuous data transmission condition inequality W1+W2+...+Wn<R without data loss, first confirm system implementation feasibility. On the premise that the system can be realized, and then according to the size of the FPGA hardware resources and other constraints, select the appropriate interrupt period T1, because the total number of bytes of each data buffer is at least (W1+W2+...+Wn)× T1×2.

Step 2: Create a data buffer

According to the write data rate Wk and the interrupt period T1 of each asynchronous data source 1, 2,..., n, determine the buffer storage size of each asynchronous data source as Wk×T1×2, and establish n for these n asynchronous data sources Data buffer, and determine that one of the data buffers is a ping-pong buffer. It may be assumed that B1 is selected as a ping-pong buffer. The buffer is an ordinary data buffer.

Step 3: Create a write status pointer register for each data buffer

When creating the write status pointer registers of each data buffer, the write status pointer value of the ping-pong buffer B1 among them is the value of the highest bit of the current write operation address, which may be 0 or 1, while the write status pointers of other data buffers It is the address value of the current write operation.

Step 4: Generate a periodic interrupt signal

According to the buffer half-full and full-full signals generated by the write operation of the ping-pong buffer B1, a periodic interrupt signal corresponding to the host computer is generated, and the interrupt signal is sent to the host computer to trigger the interrupt service subroutine, thereby completing the read FPGA Data operations in each data buffer.

Step 5: Establish bus interfaces between the host computer and each data buffer (B1, B2, . . . , Bn) in the FPGA.

Convert the read clock C, read operation address A and read enable signals contained in the read operation instruction of the host computer into the read clock C, read enable (E1, E2,..., En) and read address of each data buffer (A1R, A2R,..., AnR) signal and the read address signal AR of the write state pointer register of each buffer zone, etc. to read the data in the above storage space.

Step 6: Create the host computer interrupt service subroutine

The working process of the interrupt service subroutine of the host computer is as follows: After the interrupt service subroutine of the host computer receives the hardware interrupt signal, it first makes a judgment whether to initialize: if the system has just been reset after power-on or other forms, then the FPGA buffer The area write address and the history write pointer register value of the upper computer are initialized to their corresponding start addresses, otherwise, this initialization step is skipped. Then read the current write state pointer register value of each data buffer, and the write state pointer register value of each data buffer stored during the last interruption is saved in the host computer program, which may be called the historical write state pointer register value. The interrupt service subroutine then uses a temporary backup of the current write status pointer and the historical write status pointer saved by the host computer to complete reading the data in the corresponding address segment of each data buffer in the FPGA, and after the backup of the historical write status pointer register value and Before the read operation of the upper computer, update the historical write status pointer register value to the current write status pointer register value to ensure that the data in the corresponding address segment of each buffer can be read correctly when the next interruption occurs. After the host computer interrupt service subroutine executes the read operation, it ends and enters the state of waiting for the next interrupt.

Step 7: Under the trigger of the periodic interrupt signal, the upper computer cyclically calls the interrupt service subroutine described in step 6, so as to achieve the purpose of real-time continuous data transmission.

Beneficial effect

Compared with the traditional data transmission method triggered by multiple interrupt sources, the method of the present invention greatly reduces the complexity of software and hardware programming and debugging. Due to the single interrupt, the real-time data transmission of the system is more stable and reliable, and the possibility of system instability is reduced. The amount of data generated by each interrupt is relatively stable, and the data is more convenient for centralized batch transmission and post-processing.

Description of drawings:

Figure 1 - Schematic diagram of a single-interrupt real-time data transmission device;

Figure 2 - Flowchart of host computer interrupt service subroutine.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

Suppose there is a real-time data transmission device as shown in Figure 1. The write data rates of the asynchronous data sources 1, 2, . . . , n under the action of respective write clocks C1, C2, . Let us assume that the number of asynchronous data sources is 3, that is, n=3, and set the write data rates of data sources 1, 2, and 3 to 50KB/s, 100KB/s, and 150KB/s, respectively. At the same time, set the read data rate of the host computer processor to 1200KB/s.

Step 1: Judging whether the real-time data transmission condition without data loss is satisfied. Obviously, since the sum W1+W2+W3 of the write data rates of the three data sources is equal to 300KB/s, which is far less than the host computer’s read data rate of 1200KB/s, continuous real-time data transmission without data loss can be realized. In addition, we assume that FPGA resources are sufficient, and choose the interrupt period to be 10ms, that is, 0.01s.

Step 2: Determine the size of each data buffer, and establish three data buffers. We might as well choose the buffer of data source 1 as the ping-pong buffer. Obviously, the size of the buffer B1 of the data source 1 should be W1×T1×2, wherein, T1, that is, the period of the interrupt source is 0.01s, W1=50KB/s, so the total size of the ping-pong buffer of the data source 1 is 1KB. Similarly, the buffer size of data source 2 is W2×T1×2=2KB, and the buffer size of data source 3 is W3×T1×2=3KB. Since the buffers of data sources 2 and 3 are non-ping-pong buffers and do not need to be used to generate interrupt signals, the buffer size selection can be slightly larger than 2KB and 3KB to better ensure data continuity and avoid new data being read It is overwritten by subsequent data before fetching.

Step 3: Create the storage registers for the write status pointers of the data buffers B1, B2, and B3. Wherein, the write status pointer value of the data buffer B1 is equal to the value of the highest bit of the current write operation address A1W, and the write status pointer values of the data buffer B2 and B3 are equal to their current write operation addresses A2W and A3W.

Step 4: Use the half-full or full-full signal of the ping-pong data buffer B1 to generate an interrupt signal. The half-full or full-full signal of the B1 buffer is obviously related to the value of its write operation address. Assuming that the data width of the B1 buffer is 1 byte and the storage depth is 1KB, the address range of the write operation address A1W of the B1 buffer is 0 to 1023. Obviously, the B1 buffer is half full when the address of the write operation is 511, and the buffer is full when the address of the write operation is 1023. When the B1 buffer is half full or full, an interrupt pulse signal should be generated and sent to the host computer. In Fig. 1, the interrupt generation module generates a pulse interrupt signal to the host computer processor according to whether the size of the write operation address A1W of the B1 buffer is equal to 511 or 1023.

Step 5: Establish bus interface modules between the host computer and the data buffers B1, B2, and B3 in the FPGA, as shown in Figure 1. The bus interface module is used to convert the read clock C, read address A and read enable E contained in the read operation command from the host computer into the read clock C and read address of each data buffer and its write status pointer storage register. A1R, A2R, A3R, AR and read enable signals such as E1, E2, E3 to realize the smooth reading of readable data in these storage spaces by the host computer.

Step 6: Create the host computer interrupt service subroutine, the flow chart of which is shown in Figure 2. At the moment of interruption, first complete the protection site. Secondly, it is judged whether the current system has just performed a power-on reset or other forms of reset operation, and if so, executes the initialization operation of the history writing state pointer register, otherwise skips the initialization step. Then, the system first reads the value of the current write status pointer storage register in the FPGA, and then backs up the historical write status pointer register value saved in the interrupt service subroutine to a temporary variable for subsequent host computer read operations. Then, the system updates the value of the historical write status pointer register, that is, assigns the result of the FPGA current write status pointer register just read to the historical write status pointer register for the next interrupt. Next, the host computer calculates the range of the read operation address A that generated this interrupt based on the current write status pointer register value read in the previous steps and the historical write status pointer register value backed up in the temporary variable, and then executes according to the address range Read operation function. After the data is read, execute the scene recovery operation, the interrupt service subroutine ends and exits, and waits for the arrival of the next interrupt.

Step 7: Triggered by periodic interrupt signals, the host computer repeatedly executes the interrupt service subroutine described in step 6 to complete real-time continuous data transmission of multiple asynchronous data sources.

Claims (1)

1. a single interruption real-time data transmission method based on FPGA, is characterized in that comprising following concrete steps: Step 1: Choose an appropriate interrupt period According to the write data rate Wk of each asynchronous data source 1, 2, ..., n and the read data rate R of the host computer, using the real-time continuous data transmission condition inequality W1+W2+...+Wn<R without data loss, first confirm Feasibility of system implementation, on the premise that the system can be realized, and then according to the size of FPGA hardware resources and other constraints, select the appropriate interrupt cycle T1, because the total number of bytes of each data buffer is at least (W1+W2+. ..+Wn)×T1×2; Step 2: Create a data buffer According to the write data rate Wk and the interrupt period T1 of each asynchronous data source 1, 2,..., n, determine the buffer storage size of each asynchronous data source as Wk×T1×2, and establish n for these n asynchronous data sources data buffer, and determine that one of the data buffers is a ping-pong buffer. It may be assumed that B1 is selected as a ping-pong buffer. The buffer is an ordinary data buffer; Step 3: Create a write status pointer register for each data buffer When creating the write status pointer registers of each data buffer, the write status pointer value of the ping-pong buffer B1 among them is the value of the highest bit of the current write operation address, which may be 0 or 1, while the write status pointers of other data buffers is the address value of the current write operation; Step 4: Generate a periodic interrupt signal According to the buffer half-full and full-full signals generated by the write operation of the ping-pong buffer B1, a periodic interrupt signal corresponding to the host computer is generated, and the interrupt signal is sent to the host computer to trigger the interrupt service subroutine, thereby completing the read FPGA Data operation in each data buffer; Step five: establish the bus interface between the host computer and each data buffer B1, B2, ..., Bn in the FPGA; Convert the read clock C, read operation address A and read enable signal contained in the read operation instruction of the host computer to the read clock C, read enable E1, E2,..., En and read address A1R, A2R of each data buffer ,..., AnR signal and the read address signal AR of the write state pointer register of each buffer zone, to read the data in the above-mentioned storage space; Step 6: Create the host computer interrupt service subroutine The working process of the interrupt service subroutine of the host computer is as follows: After the interrupt service subroutine of the host computer receives the hardware interrupt signal, it first makes a judgment whether to initialize: if the system has just been reset after power-on or other forms, then the FPGA buffer The area write address and the history write pointer register value of the host computer are initialized to their corresponding start addresses, otherwise the initialization step is skipped, and then the current write status pointer register value of each data buffer is read, and the host computer program saves the The write status pointer register value of each data buffer stored at the last interrupt may be called the historical write status pointer register value, and the interrupt service subroutine then uses the current write status pointer and a temporary backup of the historical write status pointer saved by the host computer To complete the reading of the data in the corresponding address segment of each data buffer in the FPGA, and after the historical write status pointer register value is backed up and before the upper computer read operation, the historical write status pointer register value is updated to the current write status pointer register value to Ensure that the data in the corresponding address segment of each buffer can be read correctly when the next interrupt is interrupted, and the interrupt service subroutine of the host computer ends after the read operation is completed, and enters the state of waiting for the next interrupt; Step 7: Under the trigger of the periodic interrupt signal, the upper computer cyclically calls the interrupt service subroutine described in step 6, so as to achieve the purpose of real-time continuous data transmission.

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